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2013-10-17i2c: Zynq: Support for TI PCA9548 bus multiplexerMichael Burr
(Interface is not quite the same as Phillips PCA9547.) Signed-off-by: Michael Burr <michael.burr@logicpd.com> Cc: Heiko Schocher <hs@denx.de> Cc: Michal Simek <monstr@monstr.eu>
2013-10-17i2c: update config using mxc driver to new subsystemtrem
Signed-off-by: Philippe Reynes <tremyfr@yahoo.fr>
2013-10-17i2c: mxc: move to new subsystemtrem
Signed-off-by: Philippe Reynes <tremyfr@yahoo.fr>
2013-10-17i2c: fix init on generic boardtrem
On generic board, the i2c init initialize only one bus. But the new i2c subsystem allow to manage severals i2c bus. So in the case, instead of initializing a bus, we just set the current i2c bus. The initialization will be done in the i2c command. Signed-off-by: Philippe Reynes <tremyfr@yahoo.fr>
2013-10-17serial: sh: Add support R8A7791Nobuhiro Iwamatsu
This adds the preset value to register for R8A7791. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2013-10-17serial: sh: Add support R8A7790Nobuhiro Iwamatsu
This adds the preset value to register, and setup of baudrate. Signed-off-by: Kouei Abe <kouei.abe.cp@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2013-10-17sh: boards: Change clock definition of SCIF and TMUNobuhiro Iwamatsu
This changes clock definition of SCIF from CONFIG_SYS_CLK_FREQ to CONFIG_SH_SCIF_CLK_FREQ, and clock definition of TMU from CONFIG_SYS_CLK_FREQ to CONFIG_SH_TMU_CLK_FREQ for boards. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> CC: Albert Aribaud <albert.u.boot@aribaud.net>
2013-10-17serial: sh: Change definition of clock of SCIFNobuhiro Iwamatsu
The former SH/SCIF driver had calculated baudrate based on CONFIG_SYS_CLK_FREQ. The newest SH/SCIF needs calculation of the clock for SCIF. This patch defines clock CONFIG_SH_SCIF_CLK_FREQ for SCIF and changes it to CONFIG_SH_SCIF_CLK_FREQ from CONFIG_SYS_CLK_FREQ. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> CC: Albert Aribaud <albert.u.boot@aribaud.net>
2013-10-17sh: timer: Change definition of clock of TMUNobuhiro Iwamatsu
The former SH/TMU driver had calculated timer based on CONFIG_SYS_CLK_FREQ. The newest SH/TMU newly needs calculation of the clock for TMU. This patch defines clock CONFIG_SH_TMU_CLK_FREQ for TMU and changes it to CONFIG_SH_TMU_CLK_FREQ from CONFIG_SYS_CLK_FREQ. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2013-10-17sh: cache: Change cache API to defines as U-BootNobuhiro Iwamatsu
A chache API of SH is developped by reference in linux kernel. And API was the same as the linux kernel. This patch change cache API to defines as U-Boot. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2013-10-17sh: timer: Remove static global variableNobuhiro Iwamatsu
"static u16 bit" is not necessary to use this as static global variable. This patch fixes this. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2013-10-17sh: timer: Mask bit of timer prescalerNobuhiro Iwamatsu
timer_init function sets timer prescaler bit. The previous code so did not mask this bit, this function was to overwrite the bit. This will fix this problem. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2013-10-16PCIe:change the method to get the address of a requested capability in ↵Zhao Qiang
configuration space. Previously, the address of a requested capability is define like that "#define PCI_DCR 0x78" But, the addresses of capabilities is different with regard to PCIe revs. So this method is not flexible. Now a function to get the address of a requested capability is added and used. It can get the address dynamically by capability ID. The step of this function: 1. Read Status register in PCIe configuration space to confirm that Capabilities List is valid. 2. Find the address of Capabilities Pointer Register. 3. Find the address of requested capability from the first capability. Signed-off-by: Zhao Qiang <B45475@freescale.com>
2013-10-16boards/c29xpcie: Update TLB and LAW size for IFC NAND, CPLDPrabhakar Kushwaha
NAND,CPLD AMASK register is programmed for 64K size. so Update TLB & LAW size accordingly. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2013-10-16powerpc/mpc85xx: Add workaround for erratum A006379York Sun
Erratum A006379 says CPCHDBCR0 bit field [10:14] has incorrect default value after POR. The workaround is to set this field before enabling CPC to 0x1e. Erratum A006379 applies to T4240 rev 1.0 B4860 rev 1.0, 2.0 Signed-off-by: York Sun <yorksun@freescale.com>
2013-10-16powerpc/p1010rdb: add p1010rdb-pb support with updating p1010rdb-paShengzhou Liu
- Rename old P1010RDB board as P1010RDB-PA. - Add support for new P1010RDB-PB board. - Some optimization. For more details, see board/freescale/p1010rdb/README. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> [York Sun: fix conflicts in boards.cfg] Acked-by: York Sun <yorksun@freescale.com>
2013-10-16board/p1010rdb: add pin mux and sdhc support in any bootShengzhou Liu
Since pins multiplexing, SDHC shares signals with IFC, with this patch: To enable SDHC in case of NOR/NAND/SPI boot a) For temporary use case in runtime without reboot system run 'mux sdhc' in u-boot to validate SDHC with invalidating IFC. b) For long-term use case set 'esdhc' in hwconfig and save it. To enable IFC in case of SD boot a) For temporary use case in runtime without reboot system run 'mux ifc' in u-boot to validate IFC with invalidating SDHC. b) For long-term use case set 'ifc' in hwconfig and save it. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
2013-10-16powerpc/eeprom: update MAX_NUM_PORTS to adapt non-256-bytes EEPROMShengzhou Liu
Some boards use System EEPROM with 128-bytes instead of 256-bytes. Since we regard 256-bytes EEPROM as standard EEPROM with default value for MAX_NUM_PORTS. For those non-256-bytes EEPROM, we can redefine MAX_NUM_PORTS in board-specific file to override the default MAX_NUM_PORTS. This patch doesn't impact on previous existing boards. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
2013-10-16powerpc/p1010rdb: remove unused cpld_showShengzhou Liu
Function cpld_show() was for debug and not called, so clean it. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
2013-10-16powerpc/t1040qds: Add T1040QDS boardPrabhakar Kushwaha
T1040QDS is a high-performance computing evaluation, development and test platform supporting the T1040 QorIQ Power Architecture™ processor. T1040QDS board Overview ----------------------- - Four e5500 cores, each with a private 256 KB L2 cache - 256 KB shared L3 CoreNet platform cache (CPC) - Interconnect CoreNet platform - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support - Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions: - Packet parsing, classification, and distribution - Queue management for scheduling, packet sequencing, and congestion management - Cryptography Acceleration - RegEx Pattern Matching Acceleration - IEEE Std 1588 support - Hardware buffer management for buffer allocation and deallocation - Ethernet interfaces - Integrated 8-port Gigabit Ethernet switch - Four 1 Gbps Ethernet controllers - SERDES Connections, 8 lanes supporting: — PCI Express: supporting Gen 1 and Gen 2; — SGMII — QSGMII — SATA 2.0 — Aurora debug with dedicated connectors - DDR Controller 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and Interleaving -IFC/Local Bus - NAND flash: 8-bit, async, up to 2GB. - NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB - GASIC: Simple (minimal) target within Qixis FPGA - PromJET rapid memory download support - Ethernet - Two on-board RGMII 10/100/1G ethernet ports. - PHY #0 remains powered up during deep-sleep - QIXIS System Logic FPGA - Clocks - System and DDR clock (SYSCLK, “DDRCLK”) - SERDES clocks - Power Supplies - Video - DIU supports video at up to 1280x1024x32bpp - USB - Supports two USB 2.0 ports with integrated PHYs — Two type A ports with 5V@1.5A per port. — Second port can be converted to OTG mini-AB - SDHC - SDHC port connects directly to an adapter card slot, featuring: - Supporting SD slots for: SD, SDHC (1x, 4x, 8x) and/or MMC — Supporting eMMC memory devices - SPI - On-board support of 3 different devices and sizes - Other IO - Two Serial ports - ProfiBus port - Four I2C ports Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: fix conflict in boards.cfg] Acked-by-by: York Sun <yorksun@freescale.com>
2013-10-16powerpc: Fix CamelCase warnings in DDR related codePriyanka Jain
Some DDR related structures present in fsl_ddr_dimm_params.h, fsl_ddr_sdram.h, ddr_spd.h has various parameters with embedded acronyms capitalized that trigger the CamelCase warning in checkpatch.pl Convert those variable names to smallcase naming convention and modify all files which are using these structures with modified structures. Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
2013-10-16powerpc/tool/pbl: fix pbl image compiling processShaohui Xie
Previous process of compiling a PBL boot image is: 1: make <board_name_config> 2: make u-boot.pbl for example: make T4240QDS_SDCARD_config make u-boot.pbl Now the process is: 1: make <board_name> for example: make T4240QDS_SDCARD Also, updated README.pblimage. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
2013-10-16powerpc/B4860: enable PBL tool for B4860Shaohui Xie
Use a default RCW of protocol 0x2A_0x98, and a PBI configure file which uses CPC1 as 512KB SRAM, then PBL tool can be used on B4860 to build a pbl boot image. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
2013-10-16powerpc/t4240: updated rcw_cfg to align with default hardware configurationShaohui Xie
Default configuration has been changed, the most important one is DDR ref_clock which is changed from 66.67MHz to 133.33MHz. so the ratio need to change from 24x to 12x to keep the DDR frequency. There are also some other optimise to align with default configuration. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
2013-10-16powerpc/usb: Mention usb1 before usb2 inside default hwconfig stringramneek mehresh
For USB device-tree fix-up to work properly, its necessary to mention USB1 options before that of USB2 inside default hwconfig string Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
2013-10-16board/bsc9131rdb: Update IFC timings for NAND flashPrabhakar Kushwaha
Current IFC timings for NAND flash are not able to support existing K9F1G08U0B and new K9F1G08U0D flash. so Update the timings to support both. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2013-10-16powerpc: p1_p2_rdb_pc: add TPL for p1_p2_rdb_pc nand bootYing Zhang
Enable TPL for p1_p2_rdb_pc nand boot. Signed-off-by: Ying Zhang <b40530@freescale.com>
2013-10-16powerpc : p1_p2_rdb_pc : Enable p1_p2_rdb_pc to start from eSPI with SPLYing Zhang
Enable p1_p2_rdb_pc to start from eSPI with SPL. Signed-off-by: Ying Zhang <b40530@freescale.com>
2013-10-16powerpc: p1_p2_rdb_pc: Enable p1_p2_rdb_pc to boot from SD Card with SPLYing Zhang
Enable p1_p2_rdb_pc to start from eSDHC with SPL. Signed-off-by: Ying Zhang <b40530@freescale.com>
2013-10-16SGMII:fix PHY addresses for QSGMII Riser Card working in SGMII modeZhao Qiang
Fix PHY addresses for QSGMII Riser Card working in SGMII mode on board P3041/P5020/P4080/P5040/B4860. QSGMII Riser Card can work in SGMII mode, but having the different PHY addresses. So the following steps should be done: 1. Confirm whether QSGMII Riser Card is used. 2. If yes, set the proper PHY address. Generally, the function is_qsgmii_riser_card() is for step 1, and set_sgmii_phy() for step 2. However, there are still some special situations, take P5040 and B4860 as examples, the PHY addresses need to be changed when serdes protocol is changed, so it is necessary to confirm the protocol before setting PHY addresses. Signed-off-by: Zhao Qiang <B45475@freescale.com>
2013-10-16Corenet/p5040/SGMII:fix the problem for SGMII5/6Zhao Qiang
SGMII5/6 and SGMII7/8 are not on the same slot on P5040 according to the serdes protocol. So it is not proper to organize SGMII5/6 and SGMII7/8 on one bus and SGMII5/6 can't work. So a new bus SUPER_HYDRA_FM3_SGMII_MDIO is added for SGMII5/6 Signed-off-by: Zhao Qiang <B45475@freescale.com>
2013-10-16powerpc/mpc85xx:Avoid fix clk groups for Cluster & HW acceleratorPrabhakar Kushwaha
CHASSIS2 architecture never fix clock groups for Cluster and hardware accelerator like PME, FMA. These are SoC defined. SoC defines :- - NUM of PLLs present in the system - Clusters and their Clock group - hardware accelerator and their clock group if no clock group, then platform clock divider for FMAN, PME Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2013-10-16powerpc/mpc85xx:Update processor defines for T1040Prabhakar Kushwaha
T1040 SoC has - DDR controller ver 5.0 - 2 PLLs - 8 IFC Chip select - FMAN Muram 192K - No Srio - Sec controller ver 5.0 - Max CPU update for its personalities So, update the defines accordingly. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2013-10-16powerpc/mpc85xx:Make L2 cache type independent of CHASSIS2Prabhakar Kushwaha
CHASSIS2 architecture never defines type of L2 cache present in SoC. it is dependent upon the core present in the SoC. for example, - e6500 core has L2 cluster (Kibo) - e5500 core has Backside L2 Cache Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2013-10-16powerpc/c29xpcie: modify DDR parameter to make DDR more stablePo Liu
DDR parameters clk_adjust were changed. This can make the DDR run more stable. The new value were gotten by the DDR testing tool. Signed-off-by: Po Liu <Po.Liu@freescale.com>
2013-10-16powerpc:c29xpcie: make ifc timing parameter flexiblePo Liu
This patch re-config the NOR flash timing parameters which could make the ifc timing more flexible for NOR flash. The new parameters could fix the problem of hanging at "Flash:" occasionally when booting the board. Signed-off-by: Po Liu <Po.Liu@freescale.com>
2013-10-16powerpc: add CONFIG_SECURE_BOOT condition into fsl_secure_boot.hPo Liu
This patch is for board config file not to add CONFIG_SECURE_BOOT condition for include the asm/fsl_secure_boot.h. Signed-off-by: Po Liu <Po.Liu@freescale.com>
2013-10-16Prepare v2013.10Tom Rini
Signed-off-by: Tom Rini <trini@ti.com>
2013-10-16microblaze: Fix watchdog initializationMichal Simek
The patch: "blackfin: Move blackfin watchdog driver out of the blackfin arch folder." (sha1: e9a389a18477c1c57a0b30e9ea8f4d38c6e26e63) changed hw_watchdog_init() prototype which didn't match with Microblaze one. This patch fixes the driver and Microblaze initialization. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-10-16common: fsl: Fix broken SPDX-License-Identifier changeMichal Simek
This bug was introduced by: "Add GPL-2.0+ SPDX-License-Identifier to source files" (sha1: 1a4596601fd395f3afb8f82f3f840c5e00bdd57a) Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2013-10-15mtd: fix warnings due to 64-bit partition supportScott Wood
commit 39ac34473f3c96e77cbe03a49141771ed1639486 ("cmd_mtdparts: use 64 bits for flash size, partition size & offset") introduced warnings in a couple places due to printf formats or pointer casting. This patch fixes the warnings pointed out here: http://lists.denx.de/pipermail/u-boot/2013-October/164981.html Signed-off-by: Scott Wood <scottwood@freescale.com> Cc: York Sun <yorksun@freescale.com> Cc: Stefan Roese <sr@denx.de> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Tom Rini <trini@ti.com>
2013-10-16spi: mxc_spi: Fix double incrementing read pointer for unaligned buffersTimo Herbrecher
If dout buffer is not 32 bit-aligned or data to transmit is not multiple of 32 bit the read data pointer is already incremented on single byte reads. Signed-off-by: Timo Herbrecher <t.herbrecher@gateware.de> Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2013-10-16sf: probe: Add missing Atmel at25df321 flashBo Shen
As the spi flash transfer to multiple parts, it is forgot to add Atmel AT25DF321 spi flash support, which broken several Atmel EK boards which this chip. So, add it Signed-off-by: Bo Shen <voice.shen@atmel.com> Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
2013-10-16spi: Add GPL-2.0+ SPDX-License-Identifier for missing filesJagannadha Sutradharudu Teki
Added GPL-2.0+ SPDX-License-Identifier for missed spi source files. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2013-10-16sf: Add GPL-2.0+ SPDX-License-Identifier for missing onesJagannadha Sutradharudu Teki
Added GPL-2.0+ SPDX-License-Identifier for missed sf source files. Signed-off-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Signed-off-by: Bo Shen <voice.shen@atmel.com>
2013-10-16sf: Minor cleanups.Jagannadha Sutradharudu Teki
- Add comments. - Renamed few macros. - Add tabs. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Signed-off-by: Bo Shen <voice.shen@atmel.com>
2013-10-16sf_ops: Unify bank_sel calculation codeJagannadha Sutradharudu Teki
Unified the bank_sel calculation code for erase and write ops. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
2013-10-15buildman: Use env to pick the python from $PATHJagannadha Sutradharudu Teki
python used in buildman doesn't need to be placed in /usr/bin/python, So use env to ensure that the interpreter will pick the python from environment. Usefull with several versions of python's installed on system. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Acked-by: Simon Glass <sjg@chromium.org>
2013-10-14Merge branch 'buildman' of git://git.denx.de/u-boot-x86Tom Rini
2013-10-14cmd_sandbox.c: Update for do_(load|save) not taking a number baseTom Rini
Signed-off-by: Tom Rini <trini@ti.com>
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