summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2008-03-2685xx: Fix merge duplicationKumar Gala
ft_fixup_cpu() got duplicated in some merge snafu. Remove the duplicate. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-03-2685xx: Expand CCSR space with more DDR controller registers.James Yang
Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-03-2685xx: Speed up get_ddr_freq() and get_bus_freq()James Yang
get_ddr_freq() and get_bus_freq() used get_sys_info() each time they were called. However, get_sys_info() recalculates extraneous information when called each time. Have get_ddr_freq() and get_bus_freq() return memoized values from global_data instead. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-03-2685xx: Show DDR memory data rate in addition to the memory clock frequency.James Yang
Show the DDR memory data rate in addition to the memory clock frequency. For DDR/DDR2 memories the memory data rate is 2x the memory clock. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-03-2685xx: get_tbclk() speed up and rounding fixJames Yang
Speed up get_tbclk() by referencing pre-computed bus clock frequency value from global data instead of sys_info_t. Fix rounding of result to nearest; previously it was rounding upwards. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-03-26Update SVR numbers to expand supportAndy Fleming
FSL has taken to using SVR[16:23] as an SOC sub-version field. This is used to distinguish certain variants within an SOC family. To account for this, we add the SVR_SOC_VER() macro, and update the SVR_* constants to reflect the larger value. We also add SVR numbers for all of the current variants. Finally, to make things neater, rather than use an enormous switch statement to print out the CPU type, we create and array of SVR/name pairs (using a macro), and print out the CPU name that matches the SVR SOC version. Signed-off-by: Andy Fleming <afleming@freescale.com>
2008-03-26Add the Freescale PCI device IDsAndy Fleming
Signed-off-by: Andy Fleming <afleming@freescale.com>
2008-03-2685xx: Added support for multicore boot mechanismKumar Gala
Added the cpu command that provides a generic mechanism to get status, reset, and release secondary cores in multicore processors. Added support for using the ePAPR defined spin-table mechanism on 85xx. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com>
2008-03-2685xx: Added support for multicore boot mechanismKumar Gala
Added the cpu command that provides a generic mechanism to get status, reset, and release secondary cores in multicore processors. Added support for using the ePAPR defined spin-table mechanism on 85xx. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-03-2685xx: Add the concept of CFG_CCSRBAR_PHYSKumar Gala
When we go to 36-bit physical addresses we need to keep the concept of the physical CCSRBAR address seperate from the virtual one. For the majority of boards CFG_CCSBAR_PHYS == CFG_CCSRBAR Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-03-26Coding style cleanup.Wolfgang Denk
Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-03-26Add CFG_RTC_DS1337_NOOSC to turn off OSC outputJoakim Tjernlund
The default settings for RTC DS1337 keeps the OSC output, 32,768 Hz, on. This add CFG_RTC_DS1337_NOOSC to turn it off. Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
2008-03-26Cleanup coding style, update CHANGELOGWolfgang Denk
Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-03-26Merge branch 'master_merge_new-image' of /home/tur/git/u-bootWolfgang Denk
2008-03-26README: update documentation (availability, links, etc.)Wolfgang Denk
Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-03-26Merge branch 'new-image' of git://www.denx.de/git/u-boot-testingBartlomiej Sieka
Conflicts: common/cmd_bootm.c cpu/mpc8xx/cpu.c Signed-off-by: Bartlomiej Sieka <tur@semihalf.com>
2008-03-26USB Storage, add meaningful return valueAras Vaichas
This patch changes the "usb storage" command to return success if it finds a USB storage device, otherwise it returns error. Signed-off-by: Markus Klotzbuecher <mk@denx.de>
2008-03-2583xx/fdt_support: let user specifiy FSL USB Dual-Role controller roleAnton Vorontsov
Linux understands "host" (default), "peripheral" and "otg" (broken). Though, U-Boot doesn't restrict dr_mode variable to these values (think of renames in future). Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-03-25tsec: fix link detection for the RTL8211B PHYAnton Vorontsov
RTL8211B sets link state register after autonegotiation complete, so with bootdelay=0 RTL8211B will report lack of the link. To fix this, we should wait for aneg to complete, even if the link is currently down. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-03-25mpc83xx: add "fsl,soc" and "fsl,immr" compatible fixupsAnton Vorontsov
device_type = "soc" is being deprecated, newer device trees will use "fsl,soc" and/or "fsl,immr" for the soc nodes. This patch also adds clock-frequency property for soc nodes (the same value as bus-frequency). Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
2008-03-25Modified the DDR SDRAM clock control register to delay MCK/MCK_B 3/4 clockJoe D'Abbraccio
With the original value of 1/2 clock cycle delay, the system ran relatively stable except when we run benchmarks that are intensive users of memory. When I run samba connected disk with a HDBENCH test, the system locks-up or reboots sporadically. Signed-off by: Joe D'Abbraccio <Joe.D'abbraccio@freescale.com>
2008-03-25mpc83xx: Set PCI I/O bus-address base to zero.Scott Wood
The device trees for these boards describe PCI I/O as starting from address zero from the device's perspective. Placing I/O elsewhere may cause problems with certain PCI boards, and may cause problems with Linux. Signed-off-by: Scott Wood <scottwood@freescale.com>
2008-03-25mpc83xx: MPC8360E-RDK: use 33.3(3)MHz CLKIN/SYS_CLKAnton Vorontsov
At least on the "33MHz Pilot" board crystal is actually 33.3MHz. This patch fixes "system time drifting" problem. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
2008-03-25mpc83xx: MPC8360E-RDK: define CONFIG_OF_STDOUT_VIA_ALIASAnton Vorontsov
This is needed to update /choosen/linux,stdout-path properly. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
2008-03-25mpc83xx: MPC8360E-RDK: add dhcp commandAnton Vorontsov
Plus modify environment to use it and remove bootfile env variable, it is internal and CONFIG_BOOTFILE is used for these purposes. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
2008-03-25mpc83xx: MPC8360E-RDK: rework ddr setup, enable eccAnton Vorontsov
Current DDR setup easily causes memory corruption, this patch fixes it. Also fix TIMING_CFG0_MRS_CYC definition. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
2008-03-25mpc83xx: MPC8360E-RDK: configure pario pins for AD7843 and FHCIAnton Vorontsov
This patch adds qe pario pins configuration for AD7843 ADC/Touchscreen controller and FHCI (QE USB). Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
2008-03-25mpc83xx: MPC8360E-RDK: add support for NANDAnton Vorontsov
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
2008-03-25mpc83xx: MPC8360E-RDK: use RGMII_RXID interface modeAnton Vorontsov
This is needed for BCM PHYs to work on this board. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
2008-03-25uec: add support for Broadcom BCM5481 Gigabit PHYAnton Vorontsov
This patch adds basic support for Broadcom BCM5481 PHY. RXD-RXC delay quirk comes from MPC8360E-RDK BSP source, author is Peter Barada <peterb@logicpd.com>. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
2008-03-25uec: add support for RGMII_RXID interface modeAnton Vorontsov
PHY drivers will use it to setup software delay between RXD and RXC signals. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
2008-03-25uec: add support for gbit mii status readingsAnton Vorontsov
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
2008-03-2583xx: define CONFIG_OF_STDOUT_VIA_ALIAS for the MPC837XERDB boardsAnton Vorontsov
This is primarily for the early console support. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
2008-03-2583xx: initialize serdes for MPC837XRDB boardsAnton Vorontsov
On the MPC8377ERDB: 2 SATA and 2 PCI-E. On the MPC8378ERDB: 2 PCI-E On the MPC8379ERDB: 4 SATA Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
2008-03-2583xx: serdes setup routinesAnton Vorontsov
This patch adds few routines to configure serdes on 837x targets. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
2008-03-2583xx: split COBJS onto separate linesAnton Vorontsov
..plus get rid of some #ifdefs in the .c files. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
2008-03-2583xx: nand support for MPC837XRDB boardsAnton Vorontsov
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
2008-03-25Enable CONFIG_FLASH_SHOW_PROGRESS on the MPC8360EMDS.Jerry Van Baren
Signed-off-by: Gerald Van Baren <vanbaren@cideas.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-03-25mpc8323erdb: remove RTC and add EEPROMMichael Barkowski
There's no on-board RTC on the MPC8323ERDB, but there is an EEPROM. Signed-off-by: Michael Barkowski <michael.barkowski@freescale.com> Acked-by: Kim Phillips <kim.phillips@freescale.com>
2008-03-25mpc8323erdb: Improve the system performanceMichael Barkowski
The following changes are based on kernel UCC ethernet performance: 1. Make the CSB bus pipeline depth as 4, and enable the repeat mode 2. Optimize transactions between QE and CSB. Added CFG_SPCR_OPT switch to enable this setting. The following changes are based on the App Note AN3369 and verified to improve memory latency using LMbench: 3. CS0_CONFIG[AP_n_EN] is changed from 1 to 0 4. CS0_CONFIG[ODT_WR_CONFIG] set to 1. Was a reserved setting previously. 5. TIMING_CFG_1[WRREC] is changed from 3clks to 2clks (based on Twr=15ns, and this was already the setting in DDR_MODE) 6. TIMING_CFG_1[PRETOACT] is changed from 3clks to 2clks. (based on Trp=15ns) 7. TIMING_CFG_1[ACTTOPRE] is changed from 9clks to 6clks. (based on Tras=40ns) 8. TIMING_CFG_1[ACTTORW] is changed from 3clks to 2clks. (based on Trcd=15ns) 9. TIMING_CFG_1[REFREC] changed from 21 clks to 11clks. (based on Trfc=75ns) 10. TIMING_CFG_2[FOUR_ACT] is changed from 10 clks to 7clks. (based on Tfaw=50ns) 11. TIMING_CFG_2[ADD_LAT] and DDR_MODE[AL] changed from 0 to 1 (based on CL=3 and WL=2). Signed-off-by: Michael Barkowski <michael.barkowski@freescale.com> Acked-by: Kim Phillips <kim.phillips@freescale.com>
2008-03-25mpc8323erdb: use readable DDR config macrosMichael Barkowski
Use available shift/mask macros to define DDR configuration. Signed-off-by: Michael Barkowski <michael.barkowski@freescale.com> Acked-by: Kim Phillips <kim.phillips@freescale.com>
2008-03-2583xx: Add Vitesse VSC7385 firmware uploadingTimur Tabi
Update the MPC8349E-mITX, MPC8313E-RDB, and MPC837XE-RDB board files to upload the Vitesse VSC7385 firmware. Changed CONFIG_VSC7385 to CONFIG_VSC7385_ENET. Cleaned up the board header files to make selecting the VSC7385 easier to control. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-03-25NET: Add Vitesse VSC7385 firmware uploadingTimur Tabi
The Vitesse VSC7385 is a 5-port switch found on the Freescale MPC8349E-mITX and other boards. A small firwmare must be uploaded to its on-board memory before it can be enabled. This patch adds the code which uploads firmware (but not the firmware itself). Previously, this feature was provided by a U-Boot application that was made available only on Freescale BSPs. The VSC7385 firmware must still be obtained separately, but at least there is no longer a need for a separate application. Signed-off-by: Timur Tabi <timur@freescale.com> Acked-by: Ben Warren <biggerbadderben@gmail.com>
2008-03-26Coding Style cleanyp; update CHANGELOGWolfgang Denk
Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-03-26Merge branch 'master' of git://www.denx.de/git/u-boot-mipsWolfgang Denk
2008-03-26Merge branch 'master' of git://www.denx.de/git/u-boot-mpc86xxWolfgang Denk
2008-03-26Remove deprecated CONFIG_OF_HAS_UBOOT_ENV and CONFIG_OF_HAS_BD_TJerry Van Baren
These defines embedded the u-boot env variables and/or the bd_t structure in the fdt blob. The conclusion of discussion on the u-boot email list was that embedding these in the fdt blob is not useful: there are better ways of passing the data (in fact, the fdt blob itself replaces the bd_t struct). The only board that enables these is the stxxtc and they don't appear to be used by linux. Signed-off-by: Gerald Van Baren <vanbaren@cideas.com> Acked-by: Kim Phillips <kim.phillips@freescale.com>
2008-03-26rtc: Remove 2nd reference to max6900.o in drivers/rtc/MakefileStefan Roese
Signed-off-by: Stefan Roese <sr@denx.de>
2008-03-26Add Flex-OneNAND booting supportKyungmin Park
Flex-OneNAND is a monolithic integrated circuit with a NAND Flash array using a NOR Flash interface. This on-chip integration enables system designers to reduce external system logic and use high-density NAND Flash in applications that would otherwise have to use more NOR components. Flex-OneNAND enables users to configure to partition it into SLC and MLC areas in more flexible way. While MLC area of Flex-OneNAND can be used to store data that require low reliability and high density, SLC area of Flex-OneNAND to store data that need high reliability and high performance. Flex-OneNAND can let users take advantage of storing these two different types of data into one chip, which is making Flex-OneNAND more cost- and space-effective. Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
2008-03-25MPC5200: support setup without FECAndré Schwarz
Include FEC specific nodes in ft_cpu_setup only if CONFIG_MPC5xxx_FEC is defined. Systems without FEC, i.e. no FEC node in DTB, should be possible. Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de> Acked-by: Grant Likely <grant.likely@secretlab.ca>
generated by cgit (git 2.34.1) at 2024-12-26 06:28:41 +0000