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2018-05-29ARM: kirkwood: Add device-tree for lschlv2 & lsxhlChris Packham
Import the dts files from Linux 4.17 and enable CONFIG_OF_CONTROL. Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-29ARM: kirkwood: Add device-tree for ds109Chris Packham
Import the dts files from Linux 4.17 and enable CONFIG_OF_CONTROL. Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-29ARM: kirkwood: Add device-tree for dreamplugChris Packham
Import the dts file from Linux 4.17 and enable CONFIG_OF_CONTROL. Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-29ARM: kirkwood: Add device-tree for d2net_v2 & net2big_v2Chris Packham
Import the dts files from Linux 4.17 and enable CONFIG_OF_CONTROL. Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-29board: turris_mox: Add fixed regulator support to defconfigMarek Behún
Without this USB3 won't work in U-Boot. Signed-off-by: Marek Behun <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-29sf: Add Macronix MX25U25635F IDMarek Vasut
Add ID for the Macronix MX25U25635F flash. Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-05-29sf: Add Winbond W25Q256 IDMarek Vasut
Add ID for the Winbond W25Q256 flash. Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-05-28configs: orangepi-prime: Enable USB OTG peripheral modeJagan Teki
Enable USB_MUSB_GADGET which operate OTG in peripheral mode Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Jun Nie <jun.nie@linaro.org>
2018-05-28arm64: allwinner: h5: orangepi-prime: Sync usb otg nodes from LinuxJagan Teki
orangepi-prime has usb otg routed host with either EHCI0/OHCI0 sync the same from Linux. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Jun Nie <jun.nie@linaro.org>
2018-05-28configs: orangepi-pc2: Enable USB OTG peripheral modeJagan Teki
Enable USB_MUSB_GADGET which operate OTG in peripheral mode Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Jun Nie <jun.nie@linaro.org>
2018-05-28arm64: allwinner: h5: orangepi-pc2: Sync usb otg nodes from LinuxJagan Teki
orangepi-pc2 has usb otg routed host with either EHCI0/OHCI0 sync the same from Linux. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Jun Nie <jun.nie@linaro.org>
2018-05-28arm64: allwinner: h5: orangepi-pc2: Order nodes in alphabeticJagan Teki
Order sun50i-h5-orangepi-pc2.dts nodes in alphabetic Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Jun Nie <jun.nie@linaro.org>
2018-05-28configs: bananapi-m2-plus: Enable USB OTG peripheral modeJagan Teki
Enable USB_MUSB_GADGET which operate OTG in peripheral mode Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Jun Nie <jun.nie@linaro.org>
2018-05-28ARM: dts: sun8i-h3: bananapi-m2-plus: Sync usb otg nodes from LinuxJagan Teki
Bananapi-m2-plus has usb otg routed host with either EHCI0/OHCI0 sync the same from Linux. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Jun Nie <jun.nie@linaro.org>
2018-05-28arm64: allwinner: a64: bananapi-m64: Sync usb host nodes from LinuxJagan Teki
Sync bananapi-m64 usb host nodes from Linux. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Jun Nie <jun.nie@linaro.org>
2018-05-28ARM: dts: sun8i: a83t: Sync usbphy node from LinuxJagan Teki
Sync sun8i-a83t usbphy node details from Linux. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Jun Nie <jun.nie@linaro.org>
2018-05-28configs: bananapi-m64: Enable USB OTG peripheral modeJagan Teki
Enable USB_MUSB_GADGET which operate OTG in peripheral mode Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Jun Nie <jun.nie@linaro.org>
2018-05-28arm64: allwinner: a64: bananapi-m64: Sync usb_otg node from LinuxJagan Teki
Sync bananapi-m64 usb_otg node from Linux. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Jun Nie <jun.nie@linaro.org>
2018-05-28sunxi: h3: Sync OTG and HCI nodes from Linux DTJun Nie
Allwinner H3 have a dual-routed USB PHY0 -- routed to either OHCI/EHCI or MUSB controller. Signed-off-by: Jun Nie <jun.nie@linaro.org> Reviewed-by: Jagan Teki <jagan@openedev.com> Acked-by: Jun Nie <jun.nie@linaro.org>
2018-05-28sunxi: Drop legacy usb_phy.cJagan Teki
Allwinner PHY USB code is now part of generic-phy framework, so drop existing legacy handling like arch/arm/mach-sunxi.c and related code areas. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Jun Nie <jun.nie@linaro.org>
2018-05-28usb: sunxi: Switch to use generic-phyJagan Teki
Allwinner USB PHY handling can be done through driver-model generic-phy so add the generic-phy ops to relevant places on host and musb sunxi driver and enable them in respective SOC's. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Jun Nie <jun.nie@linaro.org>
2018-05-28phy: sun4i-usb: Add a sunxi specific function for setting squelch-detectJagan Teki
The sunxi otg phy has a bug where it wrongly detects a high speed squelch when reset on the root port gets de-asserted with a lo-speed device. The workaround for this is to disable squelch detect before de-asserting reset, and re-enabling it after the reset de-assert is done. Add a sunxi specific phy function to allow the sunxi-musb glue to do this. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Jun Nie <jun.nie@linaro.org>
2018-05-28board: sunxi: Use generic-phy for board_usb_cable_connectedJagan Teki
Allwinner PHY USB code is now part of generic-phy framework, so use it in board_usb_cable_connected. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Jun Nie <jun.nie@linaro.org>
2018-05-28device-tree-bindings: phy: Sync sun4i-usb-phy bindingsJagan Teki
Sync sun4i-usb-phy bindings from Linux, since the drivers/phy/allwinner/phy-sun4i-usb.c follow similar. Sync changes from Linux with below commit: "phy: sun4i-usb: add support for R40 USB PHY" (sha1: f3d96f8d23d8e6d0b7642ee946b9b2ac3418fb4d) Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Jun Nie <jun.nie@linaro.org>
2018-05-28phy: sun4i-usb: Add A23 USB PHY configJagan Teki
Allwinner A23 has 2 USB PHY's and 0x04 has phy ctrl offset. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Jun Nie <jun.nie@linaro.org>
2018-05-28phy: sun4i-usb: Add A33 USB PHY configJagan Teki
Allwinner A33 has 2 USB PHY's and 0x10 has phy ctrl offset. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Jun Nie <jun.nie@linaro.org>
2018-05-28phy: sun4i-usb: Add A31 PHY configJagan Teki
Allwinner A31 has 3 USB PHY's and rest similar to A10. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Jun Nie <jun.nie@linaro.org>
2018-05-28phy: sun4i-usb: Add A10/A13/A20 PHY configJagan Teki
Add PHY configs for Allwinner A10/A13/A20 which are SUN4I. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Jun Nie <jun.nie@linaro.org>
2018-05-28phy: sun4i-usb: Add A83T USB PHY configJagan Teki
Unlike, other Allwinner SUN4I Phy supporting SOC, A83T has 2 USB PHY's and second one is HSIC. So phy control need to configure to handle these HSIC and SIDDQ requirement. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Jun Nie <jun.nie@linaro.org>
2018-05-28phy: sun4i-usb: Add V3S PHY configJagan Teki
V3S has 1 USB PHY, rest are similar to A64. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Jun Nie <jun.nie@linaro.org>
2018-05-28phy: sun4i-usb: Add H3/H5 PHY configJagan Teki
H3/H5 has 4 USB PHY, rest are similar to A64. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Jun Nie <jun.nie@linaro.org>
2018-05-28phy: sun4i-usb: Add id_detect and vbus_detect opsJagan Teki
ID and VBUS detection code require when musb changing between Host and/or Peripheral modes. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Jun Nie <jun.nie@linaro.org>
2018-05-28phy: Add Allwinner A64 USB PHY driverJagan Teki
USB PHY implementation for Allwinner SOC's can be handling in to single driver with different phy configs. This driver handle all Allwinner USB PHY's start from 4I to 50I(except 9I). Currently added A64 compatibility more will add in next coming patches. Current implementation is unable to get pinctrl, clock and reset details from DT since the dm code on these will add it future. Driver named as phy-sun4i-usb.c since the same PHY logic work for all Allwinner SOC's start from 4I to A64 except 9I with different phy configurations. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Jun Nie <jun.nie@linaro.org>
2018-05-28musb: sunxi: Add support for H3/H5/A64Jagan Teki
Like other Allwinner SoC, the H3/H5/A64 is missing the config register from the musb hardware block. Use a known working value for it like other SoC. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Jun Nie <jun.nie@linaro.org>
2018-05-28sunxi: clock: Fix OHCI clock gating for H3/H5Chen-Yu Tsai
Clock gating bits on H43/H5 were wrong, fix them. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Jun Nie <jun.nie@linaro.org>
2018-05-28musb: sunxi: Use BIT instead of numerical shiftJagan Teki
Use BIT is possible areas instead of numerical shift. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Jun Nie <jun.nie@linaro.org>
2018-05-28musb: sunxi: Add OTG device clkgate and reset for H3/H5Jagan Teki
Add OTG device clkgate and reset for H3/H5 through driver_data. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Jun Nie <jun.nie@linaro.org>
2018-05-28sunxi: clock: Fix clock gating for H3/H5/A64Jagan Teki
clock gating bits on a64 are different than H3_H5, so fixed only required bits on clock_sun6i.h. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Jun Nie <jun.nie@linaro.org>
2018-05-28musb: sunxi: Add fifo configJagan Teki
Unlike other Allwinner SOC's H3/H5/V3s OTG support 4 endpoints with relevant fifo configs, rest all have 5 endpoints. So add the fifo configs and defer them based on driver_data. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Jun Nie <jun.nie@linaro.org>
2018-05-28musb: sunxi: Use simple way to fill musb_hdrc pdataJagan Teki
Filling musb_hdrc pdata using structure will unnecessary add extra ifdefs, so fill them inside probe call for better code understanding and get rid ifdefs using devicetree compatible. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Jun Nie <jun.nie@linaro.org>
2018-05-28musb: sunxi: Add proper macros instead of numericalsJagan Teki
- add proper macros for musb_config members - use bool 'true' for multipoint and dyn_fifo instead of numerical 1 Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Jun Nie <jun.nie@linaro.org>
2018-05-28usb: sunxi: Simplify ccm reg base codeJagan Teki
Move struct sunxi_ccm_reg pointer to private structure so-that accessing ccm reg base become more proper way and avoid local initialization in each function. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Jun Nie <jun.nie@linaro.org>
2018-05-26add FIT data-position & data-offset property supportKelvin Cheung
Add FIT data-position & data-offset property support for bootm, which were already supported in SPL. Signed-off-by: Kelvin Cheung <keguang.zhang@gmail.com>
2018-05-26malloc: Use malloc simple before malloc is fully initialized in memalign()Ley Foon Tan
Follow implementation in mALLOc(). Check GD_FLG_FULL_MALLOC_INIT flag and use malloc_simple if GD_FLG_FULL_MALLOC_INIT is unset. Adjust the malloc bytes to align with the requested alignment. The original memalign() function will access mchunkptr struct to adjust the alignment if there is misalignment happen, but mchunkptr struct is not being initialized before full malloc is initialized. This cause the system crash. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Marek Vasut <marek.vasut@gmail.com>
2018-05-26mmc: stm32_sdmmc2: Fix stm32_sdmmc2_start_cmd()Patrice Chotard
SDMMC_CMD_CPSMEN bit is wrongly check and set in SDMMC_ARG register instead of SDMMC_CMD register. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-05-26stm32mp1: use OTP to configure MAC address and serial numberPatrick Delaunay
Use OTP57 and 58 for MAC address - OTP57 = MAC address bits [31:0] - OTP58 = MAC address bit [47:32] stored in OTP LSB's Use manufacture information in OTP13 to OTP15 to build unique chip id saved in env variable "serial#" (used for USB device enumeration) Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-05-26stm32mp1: add FUSE command supportPatrick Delaunay
Add support of fuse command (read/write/program/sense) on bank 0 to access to BSEC SAFMEM (4096 OTP bits). Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-05-26stm32mp1: add bsec driverPatrick Delaunay
Add a MISC driver with read and write access to BSEC IP (Boot and Security and OTP control) - offset 0: shadowed values - offset 0x80000000: OTP fuse box values (SAFMEM) Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-05-26stm32mp1: remove the second TAMP_BOOT_CONTEXT updatePatrick Delaunay
The register TAMP_BOOT_CONTEXT is already updated in get_bootmode() in cpu.c and no need to be done twice. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-05-26stm32mp1: Allow to activate CONFIG_DEBUG_UARTPatrick Delaunay
Add the needed information to enable the debug uart to have printf before the serial driver probe (so before probe for clock, pincontrol and reset drivers) To enable the debug on uart 4 (default console): + CONFIG_DEBUG_UART=y + CONFIG_DEBUG_UART_STM32=y Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
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