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2019-01-24net: mvgbe: fallback phy-mode to GMIIChris Packham
Some existing device trees don't specify a phy-mode so fallback to GMII when a phy-mode is not provided. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24net: phy: micrel: fix KSZ9031 clock skew for values greater 0psAndreas Pretzsch
For KSZ9021, all skew register fields are 4-bit wide. For KSZ9031, the clock skew register fields are 5-bit wide. The common code in ksz90x1_of_config_group calculating the combined register value checks if the requested value is above the maximum and uses this maximum if so. The calculation of this maximum uses the register width, but the check itself does not. It uses a hardcoded value of 0xf, which is too low in case of the 5-bit clock (0x1f). This detail was probably lost during driver unification. Effect (only for KSZ9031 clock skews): For values greater 900 (== 0ps), this silently results in 1860 (== +960ps) instead of the requested one. Fix the check by using the bit width instead of hardcoded value(s). Signed-off-by: Andreas Pretzsch <apr@cn-eng.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24net: fix env flags for eth10addr and aboveSimon Goldschmidt
With CONFIG_REGEX enabled, ETHADDR_WILDCARD is set up for up to 10 interfaces (0..9) as the number can only have one digit. On boards with more than 10 interfaces, this leads to the protection and format checks being absent for eth10addr and above. Fix this by changing ETHADDR_WILDCARD from "\\d?" to "\\d*" to allow more than one digit. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24net: remove duplicate definition of ETHADDR_WILDCARDSimon Goldschmidt
ETHADDR_WILDCARD is defined as the same value in both env_flags.h and env_callback.h As env_callback.h includes env_flags.h, remove the duplicate definition from env_callback.h Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24net: explicitly assign errno to return code in case of network failureThomas RIENOESSL
When dealing with two ethernet ports and having "netretry" set to "once", it could occur that the connection (e.g. an ARP request) failed, hence the status of the netloop was "NETLOOP_FAIL". Due to the setting of "netretry", the network logic would then switch to the other network interface, assigning "ret" with the return value of "net_start_again()". If this call succeeded we would return 0 (i.e. success) to the caller when in reality the network action failed. Signed-off-by: Thomas RIENOESSL <thomas.rienoessl@bachmann.info> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24net: mvpp2: mdio device per portBaruch Siach
Current code forces all ports on a given Ethernet device to use the same mdio device. In practice different ports might be wired to separate mdio devices. Move the mdio device from the container struct mvpp2 to the per port struct mvpp2_port. Cc: Ken Ma <make@marvell.com> Cc: Stefan Chulski <stefanc@marvell.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Stefan Roese <sr@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24net: mvpp2: fix lookup of mdio registers base addressBaruch Siach
Current mdio base lookup code relies on a 'reg' property at the upper CP node. There is no 'reg' property there in current DT files of Armada CP110. Use ofnode_get_addr() instead since it provides proper DT address translation. Cc: Ken Ma <make@marvell.com> Cc: Stefan Chulski <stefanc@marvell.com> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Stefan Roese <sr@denx.de> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24net: designware: clear padding bytesSimon Goldschmidt
Short frames are padded to the minimum allowed size of 60 bytes. However, the designware driver sends old data in these padding bytes. It is common practice to zero out these padding bytes ro prevent leaking memory contents to other hosts. Fix the padding code to zero out the padded bytes at the end. Tested on socfpga gen5. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24net: designware: fix tx packet lengthSimon Goldschmidt
The designware driver has a bug in setting the tx length into the dma descriptor: it always or's the length into the descriptor without zeroing out the length mask before. This results in occasional packets being transmitted with a length greater than they should be (trailer). Due to the nature of Ethernet allowing such a trailer, most packets seem to be parsed fine by remote hosts, which is probably why this hasn't been noticed. Fix this by correctly clearing the size mask before setting the new length. Tested on socfpga gen5. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-01-24net: phy: Add clause 45 identifier to phy_devicePankaj Bansal
The phy devices can be accessed via clause 22 or via clause 45. This information can be deduced when we read phy id. if the phy id is read without giving any MDIO Manageable Device Address (MMD), then it conforms to clause 22. otherwise it conforms to clause 45. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24Merge tag 'xilinx-for-v2019.04' of git://git.denx.de/u-boot-microblazeTom Rini
Xilinx changes for v2019.04 tools: - Fix zynqmpimage generation zynq: - Some configs/Kconfig/DT updates - Enable REMAKE_ELF and OF_SEPARATE - Topic boards update - i2c cleanups and conversion to DM_I2C zynqmp: - Some configs/Kconfig/DT updates - Board config cleanup - Move arch folder to mach-zynqmp versal: - Enable DM_I2C, CMD_DM zynq-gem: - Fix driver cache handling i2c: - Live tree simple update phy: - Fixed phy cleanup travis: - Wire Versal SoC
2019-01-24ARM: zynq: Convert Topic Miami to DM_I2CMichal Simek
Both boards have only controllers enabled that's why move to DM_I2C is easy. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24ARM: zynq: Disable i2c for Zybo/Zybo Z7Michal Simek
There is no i2c connected in base DT that's why disable I2C commands. Also remove zynq_zybo which is not needed now. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24ARM: zynq: Remove unused GEM addressesMichal Simek
With DM in place there is no need to have GEM addresses in headers. None is using them. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24arm64: zynqmp: Remove unused GEM addressesMichal Simek
With DM in place there is no need to have GEM addresses in headers. None is using them. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24zynq: Kconfig: extend the bootstrap malloc() poolAnton Gerasimov
Most of the memory is being consumed by device binding code, more space needed for other data structures. Z-turn board has already hit the limit, others may follow soon. Measuring only the memory consumed in device_bind_common, I've got the following results (in decimal): root_driver: 108 mod_exp_sw: 108 amba: 120 serial@e0000000 aka uart0: 112 serial@e0001000 aka uart1: 88 spi@e000d000 aka qspi: 120 sdhci@e0100000 aka mmc0: 455 sdhci@e0100000.blk: 208 slcr@f8000000: 96 clkc@100: 72 (total) 1487 = 0x5cf of 0x600 Signed-off-by: Anton Gerasimov <tossel@gmail.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24board: topic-miamiplus: Run IO PLL at 1000 MHzMike Looijmans
The miamiplus can use GEM0 through MIO pins, which requires a 125 MHz TX clock to be generated. With the IO PLL at 1200 MHz this isn't possible, so change it to run at 1000 and adjust the divisors accordingly. Also set the GEM0 clock source to MIO instead of EMIO. Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24topic-miamiplus: Run CPU at 800MHz for speedgrade-2Mike Looijmans
The miamiplus contains a speedgrade-2 device, which may run the CPU at 800MHz. Change the PLL setting to 800MHz, and adapt the setpoints in the devicetree. Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24i2c: cdns: Convert to livetree functionMichal Simek
Update cadence i2c driver to support livetree Similar changes were done by: "net: zynq_gem: convert to use livetree" (sha1: 26026e695afa794ac018a09e79a48120d322b60d) Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24arm64: versal: Enable dm commandMichal Simek
It is useful to have this command enable to see which devices are bind/probed. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24arm64: versal: Enable i2c cadence controller and i2c commandMichal Simek
Enable communication over i2c. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24arm64: zynqmp: Move SoC sources to mach-zynqmpMichal Simek
Similar changes was done for Zynq in past and this patch just follow this pattern to separate cpu code from SoC code. Move arch/arm/cpu/armv8/zynqmp/* -> arch/arm/mach-zynqmp/* And also fix references to these files. Based on "ARM: zynq: move SoC sources to mach-zynq" (sha1: 0107f2403669f764ab726d0d404e35bb9447bbcc) Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24ARM: zynq: Convert all boards to OF_SEPARATEMichal Simek
Build warning was added by: "fdt: Add warning about CONFIG_OF_EMBED" (sha1: 841d5fbae4e993476fa87d8933db0cd58d3c2d41) Zynq mini configurations are not moved yet and it is questionable if make sense to move them too. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24arm: zynq: Enable CONFIG_REMAKE_ELFSiva Durga Prasad Paladugu
This patch enables CONFIG_REMAKE_ELF for Zynq platform so that it generates u-boot.elf from binary which works for all Zynq boards with OF_SEPARATE option enabled. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24arm64: zynqmp: Convert all reference boards to OF_SEPARATEMichal Simek
Build warning was added by: "fdt: Add warning about CONFIG_OF_EMBED" (sha1: 841d5fbae4e993476fa87d8933db0cd58d3c2d41) ZynqMP mini configurations are not moved yet and it is questionable if make sense to move them too. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24arm64: zynqmp: Align u-boot-spl.bin for boot.bin creationMichal Simek
Bootrom is not capable to work with non align bootloader partition that's why it is necessary to align it before boot.bin creation. The patch is creating new spl/u-boot-spl-align.bin which is used only for boot.bin. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-01-24tools: zynqmpimage: Align image_size/image_stored_sizeMichal Simek
Bootrom is not capable to work with non aligned bootloader sizes. SPL with OF_SEPARATE generates non-align images quite often that's why this change is required before OF_SEPARATE enableding. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24travis: Wire Xilinx Versal Virt platformMichal Simek
Test Xilinx Versal Virt platform running on the v3.1.0 Qemu. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24arm64: zynqmp: Disable MMC for for zc12xx_revA boardsMichal Simek
All these boards have no SD enabled. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24arm64: zynqmp: Enable FPGA_LOAD_SECURE commandMichal Simek
Enable fpga load secure feature for xilinx platforms. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24arm64: zynqmp: Enable ISSI flash for some platformsMichal Simek
Enable ISSI flash for platforms. Xilinx reference boards are also used internally with different flash part to increase coverage that's why enable also ISSI parts for all these boards even if that board is released only with one part. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24arm64: zynqmp: Enable SPI on several boardsMichal Simek
Enable GQSPI driver, SF command and SPL support for some platforms. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24arm64: zynqmp: Setup proper SPI dependencyMichal Simek
Select DM_SPI/DM_SPI_FLASH for the whole SoC. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24ARM: zynqmp_r5: Setup DM_ETH/MMC if NET/MMC is enabledMichal Simek
Setup proper ETH/MMC dependency for the whole platform. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24arm64: zynqmp: Enable net configs for zc1275Siva Durga Prasad Paladugu
This patch enable net configs for zc1275 board. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24arm64: zynqmp: Setup DM_ETH/MMC if NET/MMC is enabledMichal Simek
Setup proper ETH/MMC dependency for the whole platform. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24arm64: versal: Setup DM_ETH/MMC if NET/MMC is enabledMichal Simek
Setup proper ETH/MMC dependency for the whole platform. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24fpga: zynqmp: show an error message when FPGA programming failsLuca Ceresoli
When FPGA programming fails, it does so silently, unless debugging code is enabled. This makes it hard to detect problems in production environments. Print the error message unconditionally so the error doesn't go unnoticed. Signed-off-by: Luca Ceresoli <luca@lucaceresoli.net> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24arm64: zynqmp: Fix tcminit help text alignmentMichal Simek
Trivial patch. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24net: phy: Move fixed link code to separate routineSiva Durga Prasad Paladugu
This patch moves fixed-link functionality code to a separate routine inorder to make it more modular and cleaner. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-01-24arm64: zynqmp: Fix mmc node names to be in sync with kernelSiva Durga Prasad Paladugu
This patches renames sd nodes in dts to be in line with kernel. This patch also modifies the references for the same in code. It checks mmc first to have no time penalty for new DT node names based on left-to-right expression evaluation. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24zynq-gem: Use appropriate cache flush/invalidate for RX and TXStefan Theil
The cache was only flushed before *transmitting* packets, but not when receiving them, leading to an issue where new packets were handed to the receive handler with old contents in cache. This only happens when a lot of packets are received without sending packages every now and then. Also flushing the receive buffers in the transmit function makes no sense and can be removed. Signed-off-by: Stefan Theil <stefan.theil@mixed-mode.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24arm64: zynqmp: Protect board_late_init functionMichal Simek
Function should be compiled only when CONFIG_BOARD_LATE_INIT is defined. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24arm64: zynqmp: Do not protect zynqmp_pmufw_version()Michal Simek
There is hard dependency for CLK_ZYNQMP to have zynqmp_pmufw_version() but also FPGA code is calling this function which is possible to use without actual CLK_ZYNQMP firmware driver to be enabled. This patch enables the case where only fixed-clock CLK setup is used. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24mmc: zynq: Remove unused pwrseq variableMichal Simek
This variable was incorrectly added by: "mmc: zynq_sdhci: Add support for SD3.0" (sha1: d1f4e39d58db32a4fd1a1b4085e0ede498bd773f) which had nothing to do with MMC power sequence provider. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24arm64: zynqmp: Enable 2 NAND chips for zc1751 dc2Michal Simek
This board contains 2 nand chips that's why enable this feature. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24mtd: nand: arasan_nfc: Add support for nand multi chip selectT Karthik Reddy
This patch adds support for nand multi chip select. Also adding CONFIG_SYS_NAND_MAX_CHIPS to Kconfig to specify maximum number of nand chips. Signed-off-by: Tummala Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24tools: zynqmpimage: round up partition sizeMichael Tretter
The FSBL copies "Total Partition Word Length" * 4 bytes from the boot.bin, which implies that the partition size is 4 byte aligned. When writing the partition, mkimage calculates "Total Partition Word Length" by dividing the size by 4. This implicitly cuts unaligned bytes at the end of the added binary. Instead of rounding down, the size must be round up to 4 bytes and the binary padded accordingly. Signed-off-by: Michael Tretter <m.tretter@pengutronix.de> Reviewed-by: Alexander Graf <agraf@suse.de> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-23Merge tag 'mips-pull-2019-01-23' of git://git.denx.de/u-boot-mipsTom Rini
- MIPS: mscc: ocelot: add ethernet switch and network support - MIPS: mscc: add support for ServalT SoC family - MIPS: mscc: add support for Serval SoC family
2019-01-23mpc85xx: Add support for -msingle-pic-baseJoakim Tjernlund
-msingle-pic-base is a new gcc(from 4.6) option for ppc and it reduces the size of my u-boot with about 4-5 KB. While at it, add -fno-jump-tables too to save a few more bytes. e5500 core: size u-boot.bef text data bss dec hex filename 473043 23772 307104 803919 c444f u-boot.bef size u-boot.aft text data bss dec hex filename 453195 23772 307104 784071 bf6c7 u-boot.aft e500 core: size u-boot.bef text data bss dec hex filename 292998 17868 24968 335834 51fda u-boot.bef size u-boot.aft text data bss dec hex filename 288002 17868 24968 330838 50c56 u-boot.aft Signed-off-by: Joakim Tjernlund <joakim.tjernlund@infinera.com> Reviewed-by: York Sun <york.sun@nxp.com>
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