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2016-06-12Merge branch 'master' of git://git.denx.de/u-boot-x86Tom Rini
2016-06-12x86: broadwell: gpio: Remove the codes to set up pin controlBin Meng
Now that we have set up pin control in cpu_init_r(), remove the duplicated codes in the broadwell gpio driver. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-06-12x86: Probe pinctrl driver in cpu_init_r()Bin Meng
At present pinctrl driver gets probed in ich6_gpio driver's probe routine, which has two issues: - Pin's PADs only gets configured when GPIO driver is probed, which is not done by default. This leaves the board in a partially functional state as we must initialize PADs correctly to get perepherals fully working. - The probe routine of pinctrl driver is called multiple times, as normally there are multiple GPIO controllers. It should really be called just once. Move the call to syscon_get_by_driver_data() from ich6_gpio driver to cpu_init_r(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: George McCollister <george.mccollister@gmail.com> Tested-by: George McCollister <george.mccollister@gmail.com>
2016-06-12x86: Enable regmap and syscon for coreboot and qemu-x86Bin Meng
These are generic and should be turned on on coreboot and qemu-x86. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-06-12x86: Update x86-pinctrl driver device-tree-bindings docBin Meng
This updates the device-tree-bindings doc for x86-pinctrl driver: - clarify "gpio-offset" is required only when "mode-gpio" is set - correct property name "pull-strength" - use tab instead of space at several places Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-06-12x86: baytrail: Configure card detect pin of the SD controllerBin Meng
As of today, the latest version FSP (gold4) for BayTrail misses the PAD configuration of the SD controller's Card Detect signal. The default PAD value for the CD pin sets the pin to work in GPIO mode, which causes card detect status cannot be reflected by the Present State register in the SD controller (bit 16 & bit 18 are always zero). Add a configuration for this pin in the pinctrl node. Note I've checked the PAD configuration for all the pins in all the 3 controllers (eMMC/SDIO/SD). Only this SDMMC3_CD_B pin does not get initialized to correct mode by FSP. With fsp,emmc-boot-mode set to 2 (eMMC 4.1), eMMC pins are initialized to func 1, but if we set fsp,emmc-boot-mode to 1 (auto), those pins are initialized to func 3 which is correct according to datasheet. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-06-12x86: baytrail: Change fsp, emmc-boot-mode to "auto"Bin Meng
At present all BayTrail boards configure fsp,emmc-boot-mode to 2, which means "eMMC 4.1" per FSP documentation. However, eMMC 4.1 only shows up on some early stepping silicon of BayTrail SoC. Newer stepping SoC integrates an eMMC 4.5 controller. Intel FSP provides a config option fsp,emmc-boot-mode which tells FSP which eMMC controller it initializes. Instead of hardcoded to 2, now we change it to 1 which means "auto". With this change, MinnowMax board (with a D0 stepping BayTrail SoC) can see the eMMC 4.5 controller at PCI address 00.17.00 via U-Boot 'pci' command. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-06-12x86: baytrail: Add 'reg' property in the pinctrl nodeBin Meng
Without a 'reg' property, pinctrl driver probe routine fails in its pre_probe() with a return value of -EINVAL. Add 'reg' property for all BayTrail boards. Note for BayleyBay, the pinctrl node is newly added. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-06-12x86: ich6_gpio: Output return value of syscon_get_by_driver_data()Bin Meng
The call to syscon_get_by_driver_data() does not save its return value. Print it out to aid debugging. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-06-12x86: acpi: Fix madt lapic generationGeorge McCollister
An accumulated length was incorrectly added to current each pass through the loop. On system with more than 2 cores this caused a corrupt MADT to be generated. Signed-off-by: George McCollister <george.mccollister@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-06-10armv8: ls2080aqds: Enable QSPI boot supportYuan Yao
This patch adds QSPI boot support for LS2080AQDS board. The QSPI boot image need to be programmed into the QSPI flash first. Then we can switch to booting from QSPI memory space. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-10configs: ls2080aqds_nand_defconfig: Enable QSPIYuan Yao
The Freescale QSPI driver has been converted to Driver Model. This patch enables FSL_QSPI and its dependence options, DM, DM_SPI, OF_CONTROL and so on. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-10configs: ls2080a: Increase load image len in NAND bootYuan Yao
Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-10armv8: ls2080aqds: Config QSPI pin mux via FPGA in NAND bootYuan Yao
Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-10dts: ls2080aqds: Add QSPI dts nodeYuan Yao
Add QSPI controller and slave dts node for LS2080AQDS board. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-10configs: ls2080aqds: Enable QSPI flash supportYuan Yao
Enable QSPI flash related configure options. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-10armv8: ls2080aqds: disable IFC NOR & QIXIS when QSPI enableYuan Yao
When QSPI is enabled, NOR flash and QIXIS can't be accessed through IFC due to pin mux. Enable I2C QIXIS access and I2C early init to read the sysclk and ddrclk. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-10configs: ls2080a_common: Remove duplicate NOR configsYuan Yao
The NOR flash related configure options appear in ls2080aqds.h and ls2080ardb.h, and the two files both includ ls2080a_common.h. This patch remove the duplicated options in ls2080a_common.h. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-10armv8: ls2080aqds: Select QSPI CLK div via SCFGYuan Yao
QSPI module output SCLK divisor value is configured through SCFG. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-10drivers: i2c: mxc: Add early initYuan Yao
Add early i2c init function with conservative divider when the exact clock rate is not available. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-10board: ls2080a: Add "mcinitcmd" env for MC & DPL deploymentPratiyush Mohan Srivastava
Environment variable mcinitcmd is defined to initiate MC and DPL deployment from the location where it is stored (NOR, NAND, SD, SATA, USB) during booting. If this variable is not defined then macro MC_BOOT_ENV_VAR will be null and MC will not be booted and DPL will not be applied during U-boot booting. Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-10armv8/ls2080a: configure PMU's PCTBENR to enable WDTYunhui Cui
The SP805-WDT module on LS2080A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2016-06-09siemens,am33x: add draco etamin boardHeiko Schocher
In the draco CPU board family, etamin is a new variant with bigger flash and more RAM. Due to new flash that uses larger pages (4K) some changes are necessary because it impacts the MTD partition layout and the ubi mount parameters. Signed-off-by: Samuel Egli <samuel.egli@siemens.com> Signed-off-by: Heiko Schocher <hs@denx.de> [trini: Move BOOTDELAY into defconfig, just always be 3 now] Signed-off-by: Tom Rini <trini@konsulko.com>
2016-06-09dfu, nand, ubi: fix erasing after write finishHeiko Schocher
writting to ubi nand partitions need after write ends an erase of the remaining sectors. This fail, if dfu write size was not a multiple of erasesize, example log: Failure erase: -1 Fix this error. Signed-off-by: Heiko Schocher <hs@denx.de>
2016-06-09am335x, dxr2: get ECC sType from I2C eepromHeiko Schocher
read the ECC Type field from the i2c eeprom, instead configuring it static in the U-Boot binary. see RM: Table 26-17. NAND Geometry Information on I2C EEPROM Signed-off-by: Heiko Schocher <hs@denx.de>
2016-06-09mtd: nand: omap: allow to switch to BCH16Heiko Schocher
support in omap_nand_switch_ecc() also an eccstrength from 16. Signed-off-by: Heiko Schocher <hs@denx.de>
2016-06-09nand: add nand mtd concat supportHeiko Schocher
add for nand devices mtd concat support. Generic MTD concat support is already ported to mainline, and used in the cfi_mtd driver. This patch adds it similiar for nand devices. Signed-off-by: Heiko Schocher <hs@denx.de>
2016-06-09ubi: add new ubi command "ubi detach"Heiko Schocher
simple detachs ubi from the mtd partition. Signed-off-by: Heiko Schocher <hs@denx.de>
2016-06-09siemens,am33x: add ubi fastmap supportSamuel Egli
From: Samuel Egli <samuel.egli@siemens.com> Signed-off-by: Heiko Schocher <hs@denx.de>
2016-06-09am335x, shc: add support for the am335x based bosch shc boardHeiko Schocher
U-Boot SPL 2016.03-rc3-00019-g6dfb4c2-dirty (Mar 09 2016 - 07:40:06) SHC C3-Sample MPU reference clock runs at 6 MHz Setting MPU clock to 594 MHz Enabling Spread Spectrum of 18 permille for MPU Trying to boot from MMC reading u-boot.img reading u-boot.img U-Boot 2016.03-rc3-00019-g6dfb4c2-dirty (Mar 09 2016 - 07:05:35 +0100) Watchdog enabled I2C: ready DRAM: 512 MiB reloc off 1f783000 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1 Net: cpsw U-Boot# Signed-off-by: Heiko Schocher <hs@denx.de>
2016-06-09doc, spl, am335x: update am335x-networkHeiko Schocher
on the shc board we see when booting in net boot mode, that the ROM bootloader sends "AM335x ROM" as vendor-class-identifier. U-Boots doc says "DM814x ROM". So, add the info to the doc, that there is also "AM335x ROM" possible. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-06-09armv7: omap-common: make SPL board_mmc_init() weakHeiko Schocher
make this function weak, so board code can setup in SPL MMC init with board special values. Signed-off-by: Heiko Schocher <hs@denx.de>
2016-06-09mmc: omap_hsmmc: enable 8bit interface for eMMC for AM33xxHeiko Schocher
Enable 8bit interface on HSMMC2 for am33xx to support 8bit eMMC chips. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-06-09mmc: revert mmc: Handle switch error status bit in MMC card statusHeiko Schocher
revert patch: commit: 6b2221b008e0: mmc: Handle switch error status bit in MMC card status to get eMMC working on shc board Signed-off-by: Heiko Schocher <hs@denx.de>
2016-06-09bootstage: call show_boot_progress also in SPLHeiko Schocher
show_boot_progress() is now called from SPL also. Signed-off-by: Heiko Schocher <hs@denx.de>
2016-06-09arm, am335x: Enable Spread Spectrum for the MPUHeiko Schocher
Enable Spread Spectrum for the MPU by calculating the required values and setting the registers accordingly. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-06-09am335x: add some missing CM_CLKMODE_DPLL_SSC macrosHeiko Schocher
add missing CM_CLKMODE_DPLL_SSC_ACK_MASK, CM_CLKMODE_DPLL_SSC_DOWNSPREAD_MASK and CM_CLKMODE_DPLL_SSC_TYPE_MASK defines. Used for enabling spread spectrum. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-06-09arm, am335x: add some missing GPIO register definitionsHeiko Schocher
add missing: OMAP_GPIO_IRQSTATUS_SET_0 and OMAP_GPIO_IRQSTATUS_SET_1 registers. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-06-09power, tps65217: add some definesHeiko Schocher
add the following defines, needed for the upcoming shc board support: Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-06-09tests: py: disable main_signon check for printenv cmdHeiko Schocher
if CONFIG_VERSION_VARIABLE is set, the U-Boot environment contains a "vers" variable with the current U-Boot version string. If now "printenv" is called, test/py fails as it detects the main_sign string, which is in this case correct. So check only the main_sign as an error, if CONFIG_VERSION_VARIABLE is not set. Signed-off-by: Heiko Schocher <hs@denx.de>
2016-06-09common: bootdelay: move CONFIG_BOOTDELAY into a Kconfig optionHeiko Schocher
move CONFIG_BOOTDELAY into a Kconfig option. Used for this purpose the moveconfig.py tool in tools. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Igor Grinberg <grinberg@compulab.co.il>
2016-06-09tiny-printf: Correct the snprintf() implementationSimon Glass
This current code passes the variable arguments list to sprintf(). This is not correct. Fix it by calling _vprintf() directly. This makes firefly-rk3288 boot again. Fixes: abeb272 ("tiny-printf: Support snprintf()") Reviewed-by: Stefan Roese <sr@denx.de> Acked-by: Marek Vasut <marex@denx.de> Signed-off-by: Simon Glass <sjg@chromium.org>
2016-06-09ARM: uniphier: insert dsb barrier to ensure visibility of storeMasahiro Yamada
I noticed secondary CPUs sometimes fail to wake up, and the root cause is that the sev instruction wakes up slave CPUs before the preceding the register write is observed by them. The read-back of the accessed register does not guarantee the order. In order to ensure the order between the register write and the sev instruction, a dsb instruction should be executed prior to the sev. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-06-09ARM: uniphier: do not erase when updating U-Boot image in eMMC deviceMasahiro Yamada
Unlike NAND, eMMC can be re-written without erasing. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-06-09ARM: uniphier: do not overwrite fdt_file environmentMasahiro Yamada
This code auto-detects the best-match FDT file name, but it should respect the user's choice if "fdt_file" environment is found in a saved set of environments. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-06-09ARM: uniphier: check return code of setenv()Masahiro Yamada
Because setenv() may fail, it is better to check its return code. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-06-09ARM: uniphier: fix boot mode for PH1-LD11Masahiro Yamada
This function is shared between PH1-LD11 and PH1-LD20. The difference is the boot-mode latch for the USB boot mode. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-06-09ARM: uniphier: support eMMC boot for PH1-LD11 and PH1-LD20Masahiro Yamada
The Boot ROM on PH1-LD11/LD20 exports built-in APIs to load images from an eMMC device. They are useful to reduce the memory footprint of SPL, rather than compiling the whole MMC framework. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-06-06Prepare v2016.07-rc1Tom Rini
Signed-off-by: Tom Rini <trini@konsulko.com>
2016-06-06Merge http://git.denx.de/u-boot-samsungTom Rini
Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: configs/peach-pi_defconfig configs/peach-pit_defconfig
generated by cgit (git 2.34.1) at 2025-01-23 18:36:38 +0000