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2020-06-30test/py: test_efi_fit: Update #size-cells to 1Bin Meng
test_efi_fit tests fail on RISC-V currently. This is due to the RISC-V arch_fixup_fdt() checks the #size-cells of the root node in order to correctly fix up the reserved memory node. Per the DT binding, the /reserved-memory node requires both <#address-cells> and <#size-cells> and they should use the same values as the root node. For the root node, it's not very useful if <#size-cells> is zero. Update #size-cells to 1 so tests can pass. Signed-off-by: Bin Meng <bin.meng@windriver.com>
2020-06-30efi_loader: incorrect check against FDT_ADDR_T_NONEHeinrich Schuchardt
With commit 0d7c2913fdf7 ("cmd: bootefi: Honor the address & size cells properties correctly") addr was replaced by fdt_addr. But not in the check against FDT_ADDR_T_NONE. Fixes: 0d7c2913fdf7 ("cmd: bootefi: Honor the address & size cells properties correctly") Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-06-29efi_loader: fix incorrect use of EFI_EXIT()Heinrich Schuchardt
efi_get_variable_common() does not use EFI_ENTRY(). So we should not use EFI_EXIT() either. Fixes: 767f6eeb01d3 ("efi_loader: variable: support variable authentication") Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-06-28Merge tag 'fixes-for-v2020.07' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-video - fix logo on mx6ul_14x14_evk with DM_VIDEO enabled - fix banner string overwriting the logo on small displays - fix splash warning when building for ARM64 - fix STM32 DSI driver to probe only on supported hardware - fix memory corruption with DSI panel drivers
2020-06-28Merge tag 'u-boot-rockchip-20200628' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip - rk3188 cpu init and APLL fix; - rk3399: Add BOOTENV_SF command; - rk3288 correct vop0 vop1 setting;
2020-06-28rockchip: correctly set vop0 or vop1Patrick Wildt
The EDP_LCDC_SEL bit has to be set correctly to select vop0 or vop1, but so far we have set it in both conditions, which is not correct. Can someone verify this is the correct way round? vop1 -> set, vop0 -> clear? Signed-off-by: Patrick Wildt <patrick@blueri.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-06-28video: orisetech_otm8009a: fill characteristics of DSI data linkYannick Fertre
Fill characteristics of DSI data link to platform data instead of mipi device to avoid memory corruption. Signed-off-by: Yannick Fertre <yannick.fertre@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-06-28video: raydium_rm68200: fill characteristics of DSI data linkYannick Fertre
Fill characteristics of DSI data link to platform data instead of mipi device to avoid memory corruption. Signed-off-by: Yannick Fertre <yannick.fertre@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-06-28video: stm32: stm32_dsi: copy DSI fieldsYannick Fertre
Copy the DSI data link characteristics from panel platform data to mipi DSI device. Signed-off-by: Yannick Fertre <yannick.fertre@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-06-28video: mipi update panel platform dataYannick Fertre
Add new fields "lanes, format & mode_flags" to structure mipi_dsi_panel_plat. Signed-off-by: Yannick Fertre <yannick.fertre@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-06-28video: check hardware version of DSIYannick Fertre
Check the hardware version of DSI. Versions 1.30 & 1.31 are only supported. Signed-off-by: Yannick Fertre <yannick.fertre@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Philippe Cornu <philippe.cornu@st.com>
2020-06-28splash: Fix build warning on 64 bits CPUYe Li
Get below warning on ARM64 platform, because the bmp_load_addr is defined to u32. common/splash.c: In function ‘splash_video_logo_load’: common/splash.c:74:9: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] 74 | memcpy((void *)bmp_load_addr, bmp_logo_bitmap, Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> # bpi-m1+, bpi-m64
2020-06-28video: vidconsole: avoid multiple lines overwrite logoYe Li
Fix the bug that multiple lines wraps to overwrite logo bmp display. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> # bpi-m1+, bpi-m64
2020-06-28video: bmp: support 8bits BMP drawing on 24/32 bpp framebufferYe Li
Update video bmp code so that we can display 8 bits logo on 24 or 32 bpp framebuffer. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> # bpi-m1+, bpi-m64
2020-06-27rockchip: clk: rk3188: change APLL to safe 600MHzAlexander Kochetkov
The commit 84a6a27ae3ff ("rockchip: rk3188: init CPU freq in clock driver") changed ARM clock from 600MHz to 1600MHz. It made boot unstable due to the fact that PMIC at the start generates insufficient voltage for operation. See also: commit f4f57c58b589 ("rockchip: rk3188: Setup the armclk in spl"). Fixes commit 84a6a27ae3ff ("rockchip: rk3188: init CPU freq in clock driver"). Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-06-27rockchip: rk3188: Fix back to BROM bootAlexander Kochetkov
Move the setting for noc remap out of SPL code. Changing noc remap inside SPL results in breaking back to BROM boot. Fixes commit c14fe2a8e192 ("rockchip: rk3188: Move SoC one time setting into arch_cpu_init()"). Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-06-27rk3399: Add BOOTENV_SF commandJagan Teki
Add missing BOOTENV_SF command in rk3399 config. Fix it. Fixes: f263b860acf8 ("rk3399: Enable SF distro bootcmd") Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reported-by: Suniel Mahesh <sunil@amarulasolutions.com> Tested-by: Suniel Mahesh <sunil@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-06-26Merge branch 'for-tom' of https://github.com/lftan/u-bootTom Rini
- arm: socfpga: misc_s10: Fix EMAC register address calculation
2020-06-26arm: socfpga: misc_s10: Fix EMAC register address calculationLey Foon Tan
Fix EMAC register address calculation, address need to multiply with sizeof(u32) or 4. This fixes write to invalid address. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-06-25Merge tag 'efi-2020-07-rc6' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-efi Pull request for UEFI sub-system for efi-2020-07-rc6 Corrections for variable definitions are provided: * Correct size of secure boot related UEFI variables. * Do not use int for storing an enum. * Replace fdt_addr by fdt_size where needed.
2020-06-25ARM: dts: imx6q-tbs2910: Fix Ethernet regressionFabio Estevam
Since commit: commit 6333cbb3817ed551cd7d4e92f7359c73ccc567fc Author: Michael Walle <michael@walle.cc> Date: Thu May 7 00:11:58 2020 +0200 phy: atheros: ar8035: remove static clock config We can configure the clock output in the device tree. Disable the hardcoded one in here. This is highly board-specific and should have never been enabled in the PHY driver. If bisecting shows that this commit breaks your board it probably depends on the clock output of your Atheros AR8035 PHY. Please have a look at doc/device-tree-bindings/net/phy/atheros.txt. You need to set "clk-out-frequency = <125000000>" because that value was the hardcoded value until this commit. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com> , the clock output setting for the AR803x driver is removed from being hardcoded in the PHY driver and should be passed via device tree instead. Update the device tree with the "qca,clk-out-frequency" property so that Ethernet can work again. Reported-by: Soeren Moch <smoch@web.de> Signed-off-by: Fabio Estevam <festevam@gmail.com> Tested-by: Soeren Moch <smoch@web.de>
2020-06-24efi_loader: size of secure boot variablesHeinrich Schuchardt
The variables SetupMode, AuditMode, DeployedMode are explicitly defined as UINT8 in the UEFI specification. The type of SecureBoot is UINT8 in EDK2. Use variable name secure_boot instead of sec_boot for the value of the UEFI variable SecureBoot. Avoid abbreviations in function descriptions. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-06-24efi_loader: type of efi_secure_modeHeinrich Schuchardt
Variable efi_secure_mode is meant to hold a value of enum efi_secure_mode. So it should not be defined as int but as enum efi_secure_mode. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-06-24cmd: bootefi: Fix fdt_size variable type in efi_carve_out_dt_rsv()Bin Meng
Variable fdt_size should be of type 'fdt_size_t', not 'fdt_addr_t'. Fixes 0d7c2913fdf7: ("cmd: bootefi: Honor the address & size cells properties correctly") Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-06-24Merge tag 'mmc-2020-6-24' of https://gitlab.denx.de/u-boot/custodians/u-boot-mmcTom Rini
- Fix fsl_esdhc_imx tunning mask - Disable CMD CRC for normal tuning for fsl_esdhc_imx - Retry CM1 until emmc ready - Fix sdhci HISPD handling - Cache-aligned extcsd reading
2020-06-24mmc: sdhci: Fix HISPD bit handlingJagan Teki
SDHCI HISPD bits need to be configured based on desired mmc timings mode and some HISPD quirks. So, handle the HISPD bit based on the mmc computed selected mode(timing parameter) rather than fixed mmc card clock frequency. Linux handle the HISPD similar like this in below commit but no SDHCI_QUIRK_BROKEN_HISPD_MODE, commit <501639bf2173> ("mmc: sdhci: fix SDHCI_QUIRK_NO_HISPD_BIT handling") This eventually fixed the mmc write issue observed in rk3399 sdhci controller. Bug log for refernece, => gpt write mmc 0 $partitions Writing GPT: mmc write failed ** Can't write to device 0 ** ** Can't write to device 0 ** error! Cc: Kever Yang <kever.yang@rock-chips.com> Cc: Peng Fan <peng.fan@nxp.com> Peng Fan: added back "ctrl &= ~SDHCI_CTRL_HISPD;" per Jaehoon's suggestion Tested-by: Suniel Mahesh <sunil@amarulasolutions.com> # roc-rk3399-pc Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2020-06-24mmc: retry CMD1 in mmc_send_op_cond() until the eMMC is readyHaibo Chen
According to eMMC specification v5.1 section 6.4.3, we should issue CMD1 repeatedly in the idle state until the eMMC is ready even if mmc_send_op_cond() send CMD1 with argument = 0. Otherwise some eMMC devices seems to enter the inactive mode after mmc_complete_op_cond() issued CMD0 when the eMMC device is busy. Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2020-06-24mmc: fsl_esdhc_imx: disable the CMD CRC check for standard tuningHaibo Chen
In current code, we add 1ms dealy after each tuning command for standard tuning method. Adding this 1ms dealy is because USDHC default check the CMD CRC and DATA line. If detect the CMD CRC, USDHC standard tuning IC logic do not wait for the tuning data sending out by the card, trigger the buffer read ready interrupt immediately, and step to next cycle. So when next time the new tuning command send out by USDHC, card may still not send out the tuning data of the upper command，then some eMMC cards may stuck, can't response to any command, block the whole tuning procedure. If do not check the CMD CRC for tuning, then do not has this issue. USDHC will wait for the tuning data of each tuning command and check them. If the tuning data pass the check, it also means the CMD line also okay for tuning. So this patch disable the CMD CRC check for tuning, save some time for the whole tuning procedure. Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
2020-06-24mmc: fsl_esdhc_imx: fix the mask for tuning start pointHaibo Chen
According the RM, the bit[6~0] of register ESDHC_TUNING_CTRL is TUNING_START_TAP, bit[7] of this register is to disable the command CRC check for standard tuning. So fix it here. Fixes: fa33d207494c ("mmc: split fsl_esdhc driver for i.MX") Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
2020-06-24cmd: mmc: Cache-align extcsd read targetMarek Vasut
The extcsd read target must be cache aligned in case the controller uses DMA to read the extcsd register, make it so. Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
2020-06-23Merge branch '2020-06-23-misc-minor-fixes'Tom Rini
- Assorted minor fixes
2020-06-23psci: add 'static inline' to invoke_psci_fn() stubMasahiro Yamada
Avoid potential multiple definitions when CONFIG_ARM_PSCI_FW is disabled. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-06-23doc: sifive: Fix spelling of "environment".Vagrant Cascadian
Signed-off-by: Vagrant Cascadian <vagrant@debian.org>
2020-06-23cmd: booti: Fix spelling of "environment".Vagrant Cascadian
Signed-off-by: Vagrant Cascadian <vagrant@debian.org> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-06-23nvme: Invalidate dcache before submitting admin cmdJagan Teki
This patch try to avoids eviction of dirty lines during DMA transfer. The code right now execute the following step: - allocate the buffer - start a dma operation using the non-coherent dma buffer - invalidate cache lines associated with the buffer - read the buffer This can lead to reading back not valid information, because the cache controller could evict dirty cache lines belonging to the buffer *after* the DMA operation has started to fill the DRAM. In order to avoid this, a new invalidation is required *before* starting the DMA operation. The patch just adds an invalidation before submitting the DMA command. Example below shows the nvme disk scan result without the following patch => nvme scan nvme_get_info_from_identify: nn = 544502629, vwc = 100, sn = dev_0T, mn = `�\�, fr = t_part, mdts = 105 So, invalidating the cache before submitting the admin command, fix the cpu read. Cc: André Przywara <andre.przywara@arm.com> Reported-by: Suniel Mahesh <sunil@amarulasolutions.com> Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Suniel Mahesh <sunil@amarulasolutions.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-06-23phy: atheros: Fix the "qca,clk-out-frequency" exampleFabio Estevam
The correct name for the property is "qca,clk-out-frequency", so fix it accordingly. Signed-off-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Michael Walle <michael@walle.cc>
2020-06-23zfs: fix missing include for disk_partition definitionJoel Johnson
Commit 0528979fa7ab ("part: Drop disk_partition_t typedef") changed to a struct. As a result it uncovered an apparent missing include in zfs_common.h for part.h which actually contains the definition. The ZFS handles the struct exclusively as pointers so it was only a warning. warning: ‘struct disk_partition’ declared inside parameter list will not be visible outside of this definition or declaration void zfs_set_blk_dev(struct blk_desc *rbdd, struct disk_partition *info); Signed-off-by: Joel Johnson <mrjoel@lixil.net> Series-CC: Simon Glass <sjg@chromium.org>
2020-06-23Merge tag 'u-boot-imx-20200623' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-imx Fixes for 2020.07 ----------------- Travis: https://travis-ci.org/github/sbabic/u-boot-imx/builds/701059103 - Fixes for atheros and cubox - Toradex: mostly environment - i.MX7: DDR fixes - switch to DM - sabrelite : fix MMC access
2020-06-23configs: Resync with savedefconfigTom Rini
Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com>
2020-06-22Prepare v2020.07-rc5Tom Rini
Signed-off-by: Tom Rini <trini@konsulko.com>
2020-06-23mx6cuboxi: remove unused codeWalter Lozano
After enabling SPL_OF_CONTROL, SPL_DM and SPL_DM_MMC the MMC initialization code is not longer needed. This patch removes the unused code. Signed-off-by: Walter Lozano <walter.lozano@collabora.com>
2020-06-23mx6cuboxi: enable OF_CONTROL and DM in SPLWalter Lozano
In order to take the beneficts of DT and DM in SPL, like reusing the code and avoid redundancy, enable SPL_OF_CONTROL, SPL_DM and SPL_DM_MMC. With this new configuration SPL image is 50 KB, higher than the 38 KB from the previous version, but it still under the 68 KB limit. Signed-off-by: Walter Lozano <walter.lozano@collabora.com>
2020-06-23mx6cuboxi: customize board_boot_order to access eMMCWalter Lozano
In SPL legacy code only one MMC device is created, based on BOOT_CFG register, which can be either SD or eMMC. In this context board_boot_order return always MMC1 when configure to boot from SD/eMMC. After switching to DM both SD and eMMC devices are created based on the information available on DT, but as board_boot_order only returns MMC1 is not possible to boot from eMMC. This patch customizes board_boot_order taking into account BOOT_CFG register to point to correct MMC1 / MMC2 device. Additionally, handle IO mux for the desired boot device. Signed-off-by: Walter Lozano <walter.lozano@collabora.com>
2020-06-23mx6cuboxi: enable MMC and eMMC in DT for SPLWalter Lozano
Signed-off-by: Walter Lozano <walter.lozano@collabora.com>
2020-06-23mx6ull_14x14_evk_plugin: Convert to DM_ETHFabio Estevam
Convert to DM_ETH to avoid board removal from the project. Signed-off-by: Fabio Estevam <festevam@gmail.com>
2020-06-23mx6slevk_spl: Convert to DM_ETHFabio Estevam
Convert to DM_ETH to avoid board removal from the project. Signed-off-by: Fabio Estevam <festevam@gmail.com>
2020-06-23mx6slevk_spinor: Convert to DM_ETHFabio Estevam
Convert to DM_ETH to avoid board removal from the project. Signed-off-by: Fabio Estevam <festevam@gmail.com>
2020-06-23arm: dts: imx: fsl-imx8qm.dtsi: fix gpio aliasesYe Li
Current aliases missed gpio0 node, and this node shoud be aliased to gpio index 0 to align with i.MX8QXP. Otherwise, we will get below message when running "gpio status" command, and see the reason by "dm uclass". => gpio status Device 'gpio@5d090000': seq 0 is in use by 'gpio@5d080000' Device 'gpio@5d0a0000': seq 1 is in use by 'gpio@5d090000' Device 'gpio@5d0b0000': seq 2 is in use by 'gpio@5d0a0000' => dm uclass uclass 36: gpio 0 * gpio@5d080000 @ fbaefb90, seq 0, (req -1) 1 * gpio@5d090000 @ fbaefc70, seq 1, (req 0) 2 * gpio@5d0a0000 @ fbaefd50, seq 2, (req 1) 3 * gpio@5d0b0000 @ fbaefe30, seq 5, (req 2) 4 * gpio@5d0c0000 @ fbaeff10, seq 3, (req 3) 5 * gpio@5d0d0000 @ fbaefff0, seq 4, (req 4) 6 * gpio@5d0e0000 @ fbaf00d0, seq 6, (req 5) 7 * gpio@5d0f0000 @ fbaf01b0, seq 7, (req 6) Signed-off-by: Ye Li <ye.li@nxp.com>
2020-06-23gpio: mxc_gpio: change gpio index for i.MX8Ye Li
Since the i.MX8 GPIO banks are indexed from 0 not 1 on other i.MX platforms, so we have to adjust the index accordingly. Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com>
2020-06-23mx6ul_14x14_evk: Avoid overlap of environment over U-Boot properOtavio Salvador
We need to change the environment offset to avoid corrupting the U-Boot binary when saving it. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Reviewed-by: Fabio Estevam <festevam@gmail.com>
generated by cgit (git 2.34.1) at 2024-12-29 09:33:04 +0000