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2018-01-12ARM: Tegra186: mem parsing fixes from downstreamStephen Warren
Apply a few small fixes for the DTB /memory node parsing from NVIDIA's downstream U-Boot: - Allow arbitrary number of DRAM banks. - Correctly calculate the number of DRAM banks. - Clip PCIe memory in the same way as U-Boot CPU memory use. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2018-01-12ARM: tegra: use LINUX_KERNEL_IMAGE_HEADERStephen Warren
Enable CONFIG_LINUX_KERNEL_IMAGE_HEADER for all 64-bit Tegra boards. cboot (the boot SW that runs before U-Boot) will eventually use this information. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2018-01-12ARMv8: add optional Linux kernel image headerStephen Warren
Allow placing a Linux kernel image header at the start of the U-Boot binary. This is useful since the image header reports the amount of memory (BSS and similar) that U-Boot needs to use, but that isn't part of the binary size. This can be used by the code that loads U-Boot into memory to determine where to load U-Boot, based on other users of memory. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2018-01-12ARM: tegra: use CONFIG_SYS_INIT_SP_BSS_OFFSETStephen Warren
Enable CONFIG_SYS_INIT_SP_BSS_OFFSET for all 64-bit Tegra boards. Place the stack/... 512KiB from the end of the U-Boot binary. This should be plenty to accommodate the current DTBs (max 64 KiB), early malloc region (6KiB), stack usage, and plenty of slack, while still not placing it too far away from the U-Boot binary. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2018-01-12ARMv8: Allow dynamic early stack pointerStephen Warren
U-Boot typically uses a hard-coded value for the stack pointer before relocation. Implement option SYS_INIT_SP_BSS_OFFSET to instead calculate the initial SP at run-time. This is useful to avoid hard-coding addresses into U-Boot, so that can be loaded and executed at arbitrary addresses and thus avoid using arbitrary addresses at runtime. This option's value is the offset added to &_bss_start in order to calculate the stack pointer. This offset should be large enough so that the early malloc region, global data (gd), and early stack usage do not overlap any appended DTB. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2018-01-12ARM: tegra: remove SPL config for non-SPL SoCsStephen Warren
No 64-bit Tegra uses SPL. Remove various unused definitions from config headers. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2018-01-12ARM: tegra: don't use CONFIG_SPL_TEXT_BASE when no SPLStephen Warren
64-bit Tegra don't use SPL, and soon won't define CONFIG_SPL_TEXT_BASE when building. Fix the binman .dts file so that it doesn't use undefined values. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2018-01-13mmc: fsl_esdhc: Fix eMMC 1.8v setting issuePeng Fan
Current USDHC driver will reset VSELECT to 0 (3.3v) during mmc init, then set to 1 for 1.8v eMMC I/O. When booting from eMMC, since ROM has already set VSELECT to 1.8v before running the u-boot. This reset in USDHC driver causes a short 2.2v pulse on CMD pin. Fix this issue by not reset VSELECT to 0 when 1.8v flag is set. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2018-01-13power: Rearrange code to guard power command with CONFIG_SPL_BUILD guardTom Rini
In order to discard this code when unused in SPL we need to guard the command with a check for CONFIG_SPL_BUILD and we rearrange the code slightly to make this cleaner. Cc: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2018-01-12ARM: imx: cm_fx6: env: try to determine dtb to useChristopher Spinrath
Some distributions like Fedora expect U-Boot to select a proper devicetree. Since there are several variants of the cm-fx6 module featuring different SoC variants and the module can be paired with several baseboards, it is not viable to hardcode a filename. Instead, follow the lead of other i.MX6 based devices and try to determine the devicetree to use with the help of the board name and the SoC variant exported by the board code, before calling the distro bootcommand. For now, only for the Utilite Pro a proper devicetree filename is known but further variants of the Utilite Computer or other devices based on the cm-fx6 module may be added in the future. Signed-off-by: Christopher Spinrath <christopher.spinrath@rwth-aachen.de>
2018-01-12ARM: imx: cm_fx6: export board and soc info to envChristopher Spinrath
Like many other i.MX6 based boards, there are multiple variants of the cm-fx6 module featuring different SoC variants. Furthermore, the module can be paired with multiple baseboards. At the same time modern distribution like Fedora require U-Boot to select a proper devicetree which depends on the SoC variant and the baseboard. Thus, export the SoC variant and the actual board to the environment following the conventions of other i.MX6 devices (e.g. the NXP boards) such that the environment can select a devicetree file to load. For now, we only know for sure that the cm-fx6 module and the SB-fx6m baseboard amount to a Utilite Computer variant (depending on the SoC). Further combinations may be added in the future; e.g. CompuLab's evaluation board once someone can verify the identification string stored in its eeprom. Signed-off-by: Christopher Spinrath <christopher.spinrath@rwth-aachen.de> Reviewed-by: Stefano Babic <sbabic@denx.de>
2018-01-12drivers: pci: imx: fix enumeration logic errorKoen Vandeputte
By default, the subordinate is set equally to the secondary bus (1) when the RC boots, and does not alter afterwards. This means that theoretically, the highest bus reachable downstream is bus 1. Force the PCIe RC subordinate to 0xff, otherwise no downstream devices will be detected behind bus 1 if the booting OS does not allow enumerating a higher busnr than the subordinate value of the primary bus. Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
2018-01-12mx6memcal: spl: Disambiguate the error messageFabio Estevam
Currently mmdc_do_dqs_calibration() and mmdc_do_write_level_calibration() show the same error message, which is confusing for debugging. Disambiguate the mmdc_do_dqs_calibration() error message. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2018-01-12mx6memcal: spl: Also take i.MX6ULL into accountFabio Estevam
i.MX6ULL also does not support 64-bit DDR bus, so add it to the check logic. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2018-01-12mx6memcal: Fix the UART ports for mx6sabresd/auto boardsFabio Estevam
mx6sabresd board uses the following pins for console: PAD_CSI0_DAT10__UART1_TX_DATA PAD_CSI0_DAT11__UART1_RX_DATA ,so put it in the same config option as wandboard. mx6sabreauto board uses the following pins for console: PAD_KEY_COL0__UART4_TX_DATA PAD_KEY_ROW0__UART4_RX_DATA So do not mention sabreauto board as part of the UART1_SD3_DAT6_7 option. The config option for sabreauto can be added later when needed. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2018-01-12toradex: imx6: Rework PF0100 fuse programming commands to not be in SPLTom Rini
The code for programming the OTP fuses on the PMIC PF0100 can only be used in full U-Boot, so do not build / link it into SPL. Cc: Max Krummenacher <max.krummenacher@toradex.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Tested-by: Max Krummenacher <max.krummenacher@toradex.com>
2018-01-12imx: ventana: Rework CONFIG_CMD_GSC code to not be included in SPLTom Rini
The command can only be used from full U-Boot, so do not build it into SPL. Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2018-01-12imx: ventana: Rework CONFIG_CMD_EECONFIG code to not be included in SPLTom Rini
The command can only be used from full U-Boot, so do not build it into SPL. Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2018-01-12arm: imx: Rework i.MX specific commands to be excluded from SPLTom Rini
The "clocks" and "bootaux" commands are only usable in full U-Boot, not SPL, so do not link them inside of SPL. Rework a little of the bootaux related code to make use of __weak and declare parts of it static as it's local to the file. Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2018-01-12imx7: spl: Add support for MMC3, SD3 and NAND boot devicesEran Matityahu
Signed-off-by: Eran Matityahu <eran.m@variscite.com>
2018-01-12imx7: spl: Use SPL boot device MMC1 for all of the SOCs MMC/SD boot devicesEran Matityahu
Use only one SPL MMC device, similarly to the iMX6 code Signed-off-by: Eran Matityahu <eran.m@variscite.com>
2018-01-12imx: mx6ull-14x14-evk: enable DM QSPI driverPeng Fan
To support QSPI DM driver - Add spi0 alias for qspi node. Which is used for bus number 0. - Modify the n25q256a@0 compatible property to "spi-flash". - Modify spi4 (gpio_spi) node to spi5 - Define DM SPI/QSPI related config to enable QSPI Signed-off-by: Peng Fan <peng.fan@nxp.com>
2018-01-12spi: fsl_qspi: support i.MX6UL/6ULLL/7DPeng Fan
The QSPI module on i.MX7D is modified from i.MX6SX. The module used on i.MX6UL/6ULL is reused from i.MX7D. They share same tx buffer size. The endianness is not set at qspi driver initialization. So if we don't boot from QSPI, we will get wrong endianness when accessing from AHB address directly. Add the compatible entry for 6ul/7d. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2018-01-12mx6: ddr: Do not access MMDC_P1_BASE_ADDR on i.MX6ULLFabio Estevam
i.MX6ULL also does not have a MMDC_P1_BASE_ADDR, so do not try to access it. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Stefano Babic <ssbabic@denx.de>
2018-01-12pci: imx: request gpio before usePeng Fan
Before use GPIO, we need to request gpio first. Free gpio after use. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Stefano Babic <ssbabic@denx.de>
2018-01-12imx: mx6sxsabresd: enlarge ENV offsetPeng Fan
The u-boot-dtb.imx size is about 519KB, so 8 * 64KB conflicts with u-boot-dtb.imx. Enlarge the offset to 14 * 64KB to fix it. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com>
2018-01-12imx: mx6sxsabresd: config wdog pinmuxPeng Fan
Because kernel set WDOG_B mux before pad with the common pinctrl framwork now and wdog reset will be triggered once set WDOG_B mux with default pad setting, we set pad setting here to workaround this. Since imx_iomux_v3_setup_pad also set mux before pad setting, we set as GPIO mux firstly here to workaround it. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com>
2018-01-12imx: mx6sxsabresd: Enable DM driverPeng Fan
Enable I2C/MMC/GPIO/REGUALTOR/PMIC/USB DM drivers. There are some dependency, such as when DM MMC enabled, USB compile error. Also the i.MX I2C MMC DM driver does not support legacy GPIO interface. So enable them all together. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com>
2018-01-12board: freescale: common: add pfuze dm codePeng Fan
Add pfuze dm code, this code could be enabled with CONFIG_DM_PMIC_PFUZE100. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com>
2018-01-12ARM: imx: Enable dts for i.MX6SX-SDBPeng Fan
Enable DTS and OF_CONTROL for i.MX6SX-SDB. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com>
2018-01-12ARM: imx: Introduce dts for i.MX6SX-SDBPeng Fan
Introduce dts from Kernel commit commit 71ee203389f7cb1c("Merge tag 'scsi-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi") Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com>
2018-01-12misc: mxc_ocotp: check fuse word before programming on i.MX7ULPPeng Fan
On i.MX7ULP, the fuse words (except bank 0 and 1) only supports to write once, because they use ECC mode. Multiple writes may damage the ECC value and cause a wrong fuse value decoded when reading. This patch adds a checking before the fuse word programming, only can write when the word value is 0. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2018-01-12mx6: Support SKS-Kinkel sksimx6 BoardStefano Babic
Board has 1GB RAM and boots from SD Card U-Boot SPL 2018.01-rc3-00005-ga1898b8 (Jan 02 2018 - 13:48:54) BT_FUSE_SEL already fused, will do nothing Trying to boot from MMC1 U-Boot 2018.01-rc3-00005-ga1898b8 (Jan 02 2018 - 13:48:54 +0100) CPU: Freescale i.MX6DL rev1.2 996 MHz (running at 792 MHz) CPU: Commercial temperature grade (0C to 95C) at 40C Reset cause: POR I2C: ready DRAM: 1 GiB MMC: FSL_SDHC: 0 In: serial Out: serial Err: serial Net: FEC [PRIME] Signed-off-by: Stefano Babic <sbabic@denx.de> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2018-01-12travis.yml: Support RISC-VRick Chen
Enable travis-ci support with a link having built. Signed-off-by: Chih-Mao Chen <cmchen@andestech.com> Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com>
2018-01-12riscv: doc: Add relative doc to describe RISC-VRick Chen
Add documents to describe NX25 and AE250. Also update other documents for RISC-V. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com>
2018-01-12riscv: Modify generic codes to support RISC-VRick Chen
Support common commands bdinfo and image format, also modify common generic flow for RISC-V. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2018-01-12riscv: Support standaloneRick Chen
Run hello_world successfully. U-Boot 2018.01-rc2-00033-gb265b91-dirty (Dec 22 2017 - 13:54:21 +0800) DRAM: 1 GiB MMC: mmc@f0e00000: 0 SF: Detected mx25u1635e with page size 256 Bytes, erase size 4 KiB, total 2 MiB In: serial@f0300000 Out: serial@f0300000 Err: serial@f0300000 Net: Warning: mac@e0100000 (eth0) using random MAC address - 0a:47:9b:f8:b4:f2 eth0: mac@e0100000 RISC-V # mmc rescan RISC-V # fatls mmc 0:1 318907 u-boot-ae250-64.bin 1252 hello_world_ae250_32.bin 328787 u-boot-ae250-32.bin 3 file(s), 0 dir(s) RISC-V # fatload mmc 0:1 0x600000 hello_world_ae250_32.bin reading hello_world_ae250_32.bin 1252 bytes read in 23 ms (52.7 KiB/s) RISC-V # go 0x600000 Example expects ABI version 9 Actual U-Boot ABI version 9 Hello World argc = 1 argv[0] = "0x600000" argv[1] = "$B@" Hit any key to exit ... RISC-V # Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com>
2018-01-12riscv: tools: Prelink u-bootRick Chen
Add prelink-riscv to arrange .rela.dyn and .rela.got in compile time. So that u-boot can be directly executed without fixup. Signed-off-by: Chih-Mao Chen <cmchen@andestech.com> Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com>
2018-01-12riscv: defconfig: Add nx25-ae250 defconfig to support RISC-VRick Chen
Add nx25-ae250 default configuration for RISC-V Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com>
2018-01-12riscv: configs: Add nx25-ae250.h to support RISC-VRick Chen
Add nx25-ae250 board configuartion options for RISC-V Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com>
2018-01-12riscv: board: Add nx25-ae250 to support RISC-VRick Chen
Add nx25-ae250 board to do platform initializations. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com>
2018-01-12riscv: Add Kconfig to support RISC-VRick Chen
Add Kconfig and makefile for RISC-V Also modify MAINTAINERS for it. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com> Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>
2018-01-12riscv: nx25: include: Add header files to support RISC-VRick Chen
Add header files for RISC-V. Cache, ptregs, data type and other definitions are included. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com>
2018-01-12riscv: nx25: dts: Add AE250 dts to support RISC-VRick Chen
AE250 is the Soc using NX25 cpu core base on RISC-V arch. Details please see the doc/README.ae250. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com>
2018-01-12riscv: nx25: lib: Add relative lib funcs to support RISC-VRick Chen
Add makefile, interrupts.c and boot.c,... functions to support RISC-V arch. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com> Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>
2018-01-12riscv: cpu: Add nx25 to support RISC-VRick Chen
Add Andes nx25 cpu core (called AndesStar V5) to support RISC-V arch Verifications: 1. startup and relocation ok. 2. boot from rom or ram both ok. 2. timer driver ok. 3. uart driver ok 4. mmc driver ok 5. spi driver ok. 6. 32/64 bit both ok. Detail verification message please see doc/README.ae250. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com> Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>
2018-01-12mmc: remove hc_wp_grp_size from struct mmc if not neededJean-Jacques Hiblot
hc_wp_grp_size is needed only if hardware partitionning is used. On ARM removing it saves about 30 bytes of code space. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-01-12mmc: don't read the size of eMMC enhanced user data area in SPLJean-Jacques Hiblot
This information is only used by the "mmc info" command. On ARM removing this information from SPL saves about 140 of code space. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-01-12mmc: compile out erase and write mmc commands if write operations are not ↵Jean-Jacques Hiblot
enabled Also remove erase_grp_size and write_bl_len from struct mmc as they are not used anymore. On ARM, removing them saves about 100 bytes of code space in SPL. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-01-12mmc: read ssr only if MMC write support is enabledJean-Jacques Hiblot
The content of ssr is useful only for erase operations. on ARM, removing sd_read_ssr() saves around 300 bytes. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
generated by cgit (git 2.34.1) at 2025-01-22 19:11:08 +0000