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2016-10-28i2c: at91_i2c: Change error return -ENODEV to -EINVALWenyou Yang
Change the error return value -ENODEV from to -EINVAL for more reasonable. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2016-10-28i2c: at91_i2c: Remove unnecessary clock callingWenyou Yang
Due to the peripheral clock driver improvement, remove the unnecessary clock calling. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2016-10-28gpio: atmel_pio4: Remove unnecessary clock callingWenyou Yang
Due to the peripheral clock driver improvement, remove the unnecessary clock calling. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Acked-by: Stephen Warren <swarren@nvidia.com>
2016-10-28clk: at91: Improve the clock implementationWenyou Yang
For the peripheral clock, provide the clock ops for the clock provider, such as spi0_clk. The .of_xlate is to get the clk->id, the .enable is to enable the spi0 peripheral clock, the .get_rate is to get the clock frequency. The driver for periph32ck node is responsible for recursively binding its children as clk devices, not provide the clock ops. So do the generated clock and system clock. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Acked-by: Stephen Warren <swarren@nvidia.com>
2016-10-28clk: clk-uclass: Assign clk->dev before call .of_xlateWenyou Yang
In order to make clk->dev available in ops->of_xlate() to get the clock ID from the 'reg' property of the clock node, assign the clk->dev before calling ops->of_xlate(). Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Acked-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-10-28ARM: at91/dt: sama5d2: Fix the warning from dtcWenyou Yang
Fix the warning from dtc like, ---8<---- Warning (unit_address_vs_reg): Node /ahb/apb/pmc@f0014000/periph64ck/sdmmc0_hclk has a reg or ranges property, but no unit name --->8---- Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Acked-by: Stephen Warren <swarren@nvidia.com>
2016-10-28clk: at91: Fix at91-pmc and at91-sckc's class IDWenyou Yang
The at91-pmc and at91-sckc aren't the clock providers, change their class ID from UCLASS_CLK to UCLASS_SIMPLE_BUS, they also don't need to bind the child nodes explicitly, the .post_bind callback of simple_bus uclass will do it for them. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Acked-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-10-28AT91: Correct misspelling of "redundent" in partition namesRobert P. J. Day
Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
2016-10-28arm, at91: add icache supportHeiko Schocher
add at least icache support for at91 based boards. This speeds up NOR flash access on an at91sam9g15 based board from 15.2 seconds reading 8 MiB from a SPI NOR flash to 5.7 seconds. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
2016-10-28ARM: at91: clock: correct PRES offset for at91sam9x5Heiko Schocher
on at91sam9x5 PRES offset is 4 in the PMC master clock register. Signed-off-by: Heiko Schocher <hs@denx.de> Acked-by: Wenyou Yang <wenyou.yang@atmel.com> Acked-by: Andreas Bießmann <andreas@biessmann.org>
2016-10-28arm: at91: mpddrc: add missing MPDDRC_MD definesHeiko Schocher
add missing MPDDRC_MD defines Signed-off-by: Heiko Schocher <hs@denx.de> Acked-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
2016-10-28Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini
Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: common/Kconfig configs/dms-ba16_defconfig
2016-10-28Merge branch 'master' of http://git.denx.de/u-boot-mmcTom Rini
2016-10-28pci: Move CONFIG_PCI_PNP to KconfigBin Meng
Introduce CONFIG_PCI_PNP in Kconfig and move over boards' defconfig to use that. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> [trini: Re-generate configs and include/configs/ changes] Signed-off-by: Tom Rini <trini@konsulko.com>
2016-10-28dm: mmc: socfpga: fix MMC_OPS supportSylvain Lesne
Now that CONFIG_BLK and CONFIG_MMC_OPS are enabled by default with CONFIG_DM_MMC, the DWMMC driver on the socfpga platform fails at runtime. This adds the missing fields in the driver declaration. Signed-off-by: Sylvain Lesne <lesne@alse-fr.com> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-10-28mmc: sdhci: assign to clk_mul when host version is upper than SD3.0Jaehoon Chung
To prevent the wrong value check the SD version. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
2016-10-28mmc: add the device name in debugging message for supplying vmmcJaehoon Chung
If vmmc didn't supply, we didn't know which card didn't supply vmmc. And changed from "put" to "debug". Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2016-10-28dm: mmc: socfpga: fix MMC_OPS supportSylvain Lesne
Now that CONFIG_BLK and CONFIG_MMC_OPS are enabled by default with CONFIG_DM_MMC, the DWMMC driver on the socfpga platform fails at runtime. This adds the missing fields in the driver declaration. Signed-off-by: Sylvain Lesne <lesne@alse-fr.com> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-10-28mmc: refactor two core functionsMasahiro Yamada
Drop unneeded variables and assignments. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-10-28mmc: sdhci: fix the "misaligned operation at range" for cacheJaehoon Chung
This pathc is fixed the below thing. If misaligned the cache range, Just flush to CACHLINE_SIZE. "CACHE: Misaligned operation at range [7ae55b00, 7ae55b08]" Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
2016-10-28mmc: introduce mmc_power_initPeng Fan
In device tree, there is vmmc-supply property for SD/MMC. Introduce mmc_power_init function to handle vmmc-supply. mmc_power_init will first invoke board_mmc_power_init to avoid break boards which already implement board_mmc_power_init. If DM_MMC and DM_REGULATOR is defined, the regulator will be enabled to power up the device. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Jaehoon Chung <jh80.chung@samsung.com>
2016-10-27drivers/pci/Kconfig: Add PCITom Rini
Add 'PCI' as a menu option and migrate all existing users. Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Stephen Warren <swarren@nvidia.com>
2016-10-27arm: socfpga: sockit: Adding handoff for SDRAM ctrlcfg.extratime1Chin Liang See
Adding new handoff for SDRAM ctrcfg.extratime1 which is required for stable LPDDR2 operation. Since the board is using DDR3, the handoff is set to default value 0. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-10-27arm: socfpga: de0-nano-soc: Adding handoff for SDRAM ctrlcfg.extratime1Chin Liang See
Adding new handoff for SDRAM ctrcfg.extratime1 which is required for stable LPDDR2 operation. Since the board is using DDR3, the handoff is set to default value 0. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-10-27arm: socfpga: sr1500: Adding handoff for SDRAM ctrlcfg.extratime1Chin Liang See
Adding new handoff for SDRAM ctrcfg.extratime1 which is required for stable LPDDR2 operation. Since the board is using DDR3, the handoff is set to default value 0. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-10-27arm: socfpga: vining_fpga: Adding handoff for SDRAM ctrlcfg.extratime1Chin Liang See
Adding new handoff for SDRAM ctrcfg.extratime1 which is required for stable LPDDR2 operation. Since the board is using DDR3, the handoff is set to default value 0. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-10-27arm: socfpga: is1: Adding handoff for SDRAM ctrlcfg.extratime1Chin Liang See
Adding new handoff for SDRAM ctrcfg.extratime1 which is required for stable LPDDR2 operation. Since the board is using DDR3, the handoff is set to default value 0. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-10-27arm: socfpga: socrates: Adding handoff for SDRAM ctrlcfg.extratime1Chin Liang See
Adding new handoff for SDRAM ctrcfg.extratime1 which is required for stable LPDDR2 operation. Since the board is using DDR3, the handoff is set to default value 0. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-10-27arm: socfpga: mcvevk: Adding handoff for SDRAM ctrlcfg.extratime1Chin Liang See
Adding new handoff for SDRAM ctrcfg.extratime1 which is required for stable LPDDR2 operation. Since the board is using DDR3, the handoff is set to default value 0. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-10-27arm: socfpga: Adding handoff for SDRAM ctrlcfg.extratime1Chin Liang See
Adding new handoff for SDRAM ctrcfg.extratime1 which is required for stable LPDDR2 operation. Since the board is using DDR3, the handoff is set to default value 0. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-10-27ddr: altera: Configuring SDRAM extra cycles timing parametersChin Liang See
To enable configuration of sdr.ctrlcfg.extratime1 register which enable extra clocks for read to write command timing. This is critical to ensure successful LPDDR2 interface Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-10-27usb: xhci-mvebu: use xhci_deregister() for .remove callbackMasahiro Yamada
No need to use a wrapper that is equivalent to xhci_deregister(). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-10-27usb: ehci-vf: use ehci_deregister() for .remove callbackMasahiro Yamada
This driver was recently converted to Driver Model, so missed the subsystem-wide cleanups by commit 405273427366 ("usb: replace ehci_*_remove() with usb_deregister()"). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-10-26imx6: icorem6: Add default mtd nand partition tableJagan Teki
icorem6qdl> mtdparts device nand0 <nand>, # parts = 6 0: spl 0x00200000 0x00000000 0 1: uboot 0x00200000 0x00200000 0 2: env 0x00100000 0x00400000 0 3: kernel 0x00400000 0x00500000 0 4: dtb 0x00100000 0x00900000 0 5: rootfs 0x1f600000 0x00a00000 0 Cc: Stefano Babic <sbabic@denx.de> Cc: Peng Fan <peng.fan@nxp.com> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2016-10-26imx6: icorem6: Enable MTD device supportJagan Teki
Enable MTD device, partition and command support. Cc: Stefano Babic <sbabic@denx.de> Cc: Peng Fan <peng.fan@nxp.com> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2016-10-26imx6: icorem6: Add NAND supportJagan Teki
Add NAND support for Engicam i.CoreM6 qdl board. Boot Log: -------- U-Boot SPL 2016.09-rc2-30755-gd3dc581-dirty (Sep 28 2016 - 23:00:43) Trying to boot from NAND NAND : 512 MiB U-Boot 2016.09-rc2-30755-gd3dc581-dirty (Sep 28 2016 - 23:00:43 +0530) CPU: Freescale i.MX6SOLO rev1.3 at 792MHz CPU: Industrial temperature grade (-40C to 105C) at 55C Reset cause: WDOG Model: Engicam i.CoreM6 DualLite/Solo Starter Kit DRAM: 256 MiB NAND: 512 MiB MMC: FSL_SDHC: 0 In: serial Out: serial Err: serial Net: FEC [PRIME] Hit any key to stop autoboot: 0 icorem6qdl> Cc: Scott Wood <oss@buserror.net> Cc: Stefano Babic <sbabic@denx.de> Cc: Peng Fan <peng.fan@nxp.com> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2016-10-26mtd: nand: Kconfig: Add NAND_MXS entryJagan Teki
Added kconfig for NAND_MXS driver. Cc: Scott Wood <oss@buserror.net> Cc: Simon Glass <sjg@chromium.org> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Peng Fan <peng.fan@nxp.com> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2016-10-26arm: imx6q: Add devicetree support for Engicam i.CoreM6 Quad/DualJagan Teki
i.CoreM6 Quad/Dual modules are system on module solutions manufactured by Engicam with following characteristics: CPU NXP i.MX6 DQ, 800MHz RAM 1GB, 32, 64 bit, DDR3-800/1066 NAND SLC,512MB Power supply Single 5V MAX LCD RES FULLHD and more info at http://www.engicam.com/en/products/embedded/som/sodimm/i-core-m6s-dl-d-q Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2016-10-26arm: dts: imx6q: Add pinctrl definesJagan Teki
Add imx6q pinctrl defines support from Linux. Here is the last commit: "ARM: dts: imx: pinfunc: add MX6QDL_PAD_GPIO_6__ENET_IRQ" (sha1: d8c765e0d1ddbd5032c2491c82cc9660c2f0e7f2) Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2016-10-26arm: dts: Add devicetree for i.MX6QJagan Teki
Add i.MX6Q dtsi support from Linux. Here is the last commit: "ARM: dts: add gpio-ranges property to iMX GPIO controllers" (sha1: bb728d662bed0fe91b152550e640cb3f6caa972c) Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2016-10-26engicam: icorem6: Add DM_GPIO, DM_MMC supportJagan Teki
Add DM_GPIO, DM_MMC support for u-boot and disable for SPL. Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2016-10-26imx6q: icorem6: Enable pinctrl driverJagan Teki
Enable imx6 pinctrl driver support for i.CoreM6. Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2016-10-26arm: imx6q: Add devicetree support for Engicam i.CoreM6 DualLite/SoloJagan Teki
i.CoreM6 DualLite/Solo modules are system on module solutions manufactured by Engicam with following characteristics: CPU NXP i.MX6 DL, 800MHz RAM 1GB, 32, 64 bit, DDR3-800/1066 NAND SLC,512MB Power supply Single 5V MAX LCD RES FULLHD and more info at http://www.engicam.com/en/products/embedded/som/sodimm/i-core-m6s-dl-d-q Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2016-10-26dt-bindings: clock: imx6qdl: Add clock definesJagan Teki
Add imx6qdl clock header defines support from Linux. "clk: imx: Add clock support for imx6qp" (sha1: ee36027427c769b0b9e5e205fe43aced93d6aa66) Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2016-10-26arm: dts: imx6dl: Add pinctrl definesJagan Teki
Add imx6dl pinctrl defines support from Linux. Here is the last commit: "ARM: dts: imx: pinfunc: add MX6QDL_PAD_GPIO_6__ENET_IRQ" (sha1: d8c765e0d1ddbd5032c2491c82cc9660c2f0e7f2) Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2016-10-26arm: dts: Add devicetree for i.MX6DQLJagan Teki
Add i.MX6DQL dtsi support from Linux. Here is the last commit: "ARM: dts: imx6qdl: Fix SPDIF regression" (sha1: f065e9e4addd75c21bb976bb2558648bf4f61de6) Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2016-10-26arm: dts: Add devicetree for i.MX6DLJagan Teki
Add i.MX6DL dtsi support from Linux. Here is the last commit: "ARM: dts: add gpio-ranges property to iMX GPIO controllers" (sha1: bb728d662bed0fe91b152550e640cb3f6caa972c) Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2016-10-26imx: s/docs\/README.imximage/doc\/README.imximage/gJagan Teki
Fixed typo for doc/README.imximage on respective imximage.cfg files. Cc: Tom Rini <trini@konsulko.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2016-10-26imx6: icorem6: Add ENET supportJagan Teki
Add enet support for engicam icorem6 qdl starter kit. - Add pinmux settings - Add board_eth_init TFTP log: -------- Net: FEC [PRIME] Hit any key to stop autoboot: 0 icorem6qdl> tftpboot {fdt_addr} imx6dl-icore.dtb Using FEC device TFTP from server 192.168.2.96; our IP address is 192.168.2.75 Filename 'imx6dl-icore.dtb'. Load address: 0x0 Loading: ###### 1.3 MiB/s done Bytes transferred = 28976 (7130 hex) CACHE: Misaligned operation at range [00000000, 00007130] icorem6qdl> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-10-26net: Kconfig: Add FEC_MXC entryJagan Teki
Added kconfig for FEC_MXC driver. Cc: Joe Hershberger <joe.hershberger@gmail.com> Cc: Simon Glass <sjg@chromium.org> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Peng Fan <peng.fan@nxp.com> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
generated by cgit (git 2.34.1) at 2025-01-14 07:53:41 +0000