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2014-09-09compulab: eeprom: add support for defining eeprom i2c busNikita Kiryanov
Create CONFIG_SYS_I2C_EEPROM_BUS #define to tell the EEPROM module what I2C bus the EEPROM is located at. Make cl_eeprom_read() switch to that bus when reading EEPROM. Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Dmitry Lifshitz <lifshitz@compulab.co.il> Cc: Tom Rini <trini@ti.com> Cc: Marek Vasut <marex@denx.de> Acked-by: Igor Grinberg <grinberg@compulab.co.il> Acked-by: Dmitry Lifshitz <lifshitz@compulab.co.il> Reviewed-by: Marek Vasut <marex@denx.de> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
2014-09-09mx6: add clock enabling functionsNikita Kiryanov
Add functions to enable/disable clocks for UART, SPI, ENET, and MMC. Cc: Stefano Babic <sbabic@denx.de> Cc: Igor Grinberg <grinberg@compulab.co.il> Acked-by: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
2014-09-09imx: ventana: added cputype env varTim Harvey
There are many similarities between the IMX6QUAD/IMX6DUAL and there are many similarities between the IMX6SOLO/IMX6DUALITE. Add a 'soctype' env variable that tells you which type you have. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2014-09-09imx: ventana: add GW5520 supportTim Harvey
The GW5520 has an IMX6Q SoC with 512MB of DDR3, 256MB of NAND flash as well as: * 2x MiniPCIe sockets * 2x USB host sockets * 2x i210 GigE * HDMI out * digital I/O expansion Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2014-09-09imx: ventana: base SPL MMDC calibration on width and size not boardTim Harvey
The IMX6 MMDC calibration registers depend on propagation delay and capacitive loading between the SoC's MMDC and the DDR3 chips. On the Ventana boards the board layout varies little in trace-lengths such that propagation delays are irrelevant thus we can simply things by using calibration values obtained from various board layouts based on a common SoC and DDR chip configuration. This eliminates board-model from being needed allowing more flexibility. These values were tested on a large sample size of Gateworks Ventana boards ranging in layout, and memory configuration over the entire temperature range supported. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2014-09-09imx: ventana: updated notes regarding NAND boot errataTim Harvey
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2014-09-09net: fec_mxc: Poll FEC_TBD_READY after polling TDARFabio Estevam
When testing the FEC driver on a mx6solox we noticed that the TDAR bit gets always cleared prior then the READY bit is cleared in the last BD, which causes FEC packets reception to always fail. As explained by Ye Li: "The TDAR bit is cleared when the descriptors are all out from TX ring, but on mx6solox we noticed that the READY bit is still not cleared right after TDAR. These are two distinct signals, and in IC simulation, we found that TDAR always gets cleared prior than the READY bit of last BD becomes cleared. In mx6solox, we use a later version of FEC IP. It looks like that this intrinsic behaviour of TDAR bit has changed in this newer FEC version." Fix this by polling the READY bit of BD after the TDAR polling, which covers the mx6solox case and does not harm the other SoCs. No performance drop has been noticed with this patch applied when testing TFTP transfers on several boards of different i.mx SoCs. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de>
2014-09-09net: fec_mxc: Adjust RX DMA alignment for mx6soloxFabio Estevam
mx6solox has a requirement for 64 bytes alignment for RX DMA transfer. Other SoCs work with the standard 32 bytes alignment. Adjust it accordingly by using 64 bytes aligment in the FEC RX DMA buffers, which addresses the needs from mx6solox and also works for the other SoCs. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de>
2014-09-09clang: workaround for generated constantsJeroen Hofstee
KBuild abuses the asm statement to write to a file and clang chokes about these invalid asm statements. Hack it even more by fooling this is actual valid asm code. cc: Masahiro Yamada <yamada.m@jp.panasonic.com> cc: Tom Rini <trini@ti.com> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
2014-09-09eabi_compat: add __aeabi_memcpy __aeabi_memsetJeroen Hofstee
cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
2014-09-09ARM: make gd a function for clangJeroen Hofstee
"clang does not support global register variables; this is unlikely to be implemented soon because it requires additional LLVM backend support" [1] Workaround it by obtaining the value of gd/r9 by an inline asm routine. Note there is no set routine added for ARM at the moment, since most if not all updates of gd from c are actually not needed for ARM. [1] http://clang.llvm.org/docs/UsersManual.html cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
2014-09-09cc-option: also detect unsupported warnings optionsJeroen Hofstee
By default clang will echo a warning if a warning option is unknown. Turning warnings into errors when polling for options also catches such cases and prevents passing arguments to the compiler which cause warnings. cc: Masahiro Yamada <yamada.m@jp.panasonic.com> cc: Tom Rini <trini@ti.com> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
2014-09-09ARM: SPL: do not set gd againJeroen Hofstee
Just before calling board_init_f, crt0.S has already reserved space for the initial gd on the stack. There should be no need to allocate it again. cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
2014-09-09board_r: ARM[64] do not set gd againJeroen Hofstee
For ARM / ARM64 the relocation routines already updated gd to the new value. Don't set it again. This allows compilation with clang as it cannot update gd directly. cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
2014-09-09microblaze: Fix printf size_t format related warnings (again...)Vasili Galka
The basic idea: Define size_t using the __SIZE_TYPE__ compiler-defined type. For detailed explanation see similar patch for the nios2 arch: "nios2: Fix printf size_t format related warnings (again...)" (sha1: 00a2517fcb5159ed016b25130184638b1dbf2f02) Signed-off-by: Vasili Galka <vvv444@gmail.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-09-09Merge branch 'u-boot-sunxi/master' into 'u-boot-arm/master'Albert ARIBAUD
2014-09-09Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'Albert ARIBAUD
2014-09-08ls102xa: dcu: Add platform support for DCU on LS1021ATWR boardWang Huan
This patch adds the TWR_LCD_RGB card/HDMI options and the common configuration for DCU on LS1021ATWR board. Signed-off-by: Alison Wang <alison.wang@freescale.com>
2014-09-08video: dcu: Add Sii9022A HDMI Transmitter supportWang Huan
On LS1021ATWR, Silicon's Sii9022A HDMI Transmitter is used. This patch adds the common setting for this chip. Signed-off-by: Alison Wang <alison.wang@freescale.com>
2014-09-08video: dcu: Add DCU driver supportWang Huan
This patch is to add DCU driver support. DCU also named 2D-ACE(Two Dimensional Animation and Compositing Engine) is a system master that fetches graphics stored in internal or external memory and displays them on a TFT LCD panel. Signed-off-by: Alison Wang <alison.wang@freescale.com>
2014-09-08serial: lpuart: add 32-bit registers lpuart supportJingchang Lu
On vybrid, lpuart's registers are 8-bit. On LS102xA, lpuart's registers are 32-bit. This patch adds the support for 32-bit registers on LS102xA. Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
2014-09-08net: tsec: Remove tx snooping support from LS1Claudiu Manoil
Remove the DMCTRL Tx snooping bits (TDSEN and TBDSEN) as a workaround for LS1. It has been observed that currently the Tx stops functioning after a fair amount of Tx traffic with these settings on. These bits are sticky and once set they cannot be reset from Linux, for instance. Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
2014-09-08arm: ls102xa: Add basic support for LS1021ATWR boardWang Huan
LS102xA is an ARMv7 implementation. This patch is to add basic support for LS1021ATWR board. One DDR controller DUART1 is used as the console For the detail board information, please refer to README. Signed-off-by: Chen Lu <chen.lu@freescale.com> Signed-off-by: Yuan Yao <yao.yuan@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com>
2014-09-08arm: ls102xa: Add basic support for LS1021AQDS boardWang Huan
LS102xA is an ARMv7 implementation. This patch is to add basic support for LS1021AQDS board. One DDR controller DUART1 is used as the console For the detail board information, please refer to README. Signed-off-by: Alison Wang <alison.wang@freescale.com> Signed-off-by: Jason Jin <jason.jin@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Yuan Yao <yao.yuan@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2014-09-08driver/ddr/fsl: Add support of overriding chip select write levelingYork Sun
JEDEC spec allows DRAM vendors to use prime DQ for write leveling. This is not an issue unless some DQ pins are not connected. If a platform uses regular DIMMs but with reduced DDR ECC pins, the prime DQ may end up on those floating pins for the second rank. The workaround is to use a known good chip select for this purpose. Signed-off-by: York Sun <yorksun@freescale.com>
2014-09-08driver/ddr/freescale: Fix DDR3 driver for ARMYork Sun
Reading DDR register should use ddr_in32() for proper endianess. This patch fixes incorrect waiting time for ARM platforms. Signed-off-by: York Sun <yorksun@freescale.com>
2014-09-08driver/ddr/freescale: Add support of accumulate ECCYork Sun
If less than 8 ECC pins are used for DDR data bus width smaller than 64 bits, the 8-bit ECC code will be transmitted/received across several beats, and it will be used to check 64-bits of data once 8-bits of ECC are accumulated. Signed-off-by: York Sun <yorksun@freescale.com>
2014-09-08ls102xa: esdhc: Add esdhc support for LS102xAWang Huan
For LS1, esdhc is big-endian IP. Accessing the registers should be in big-endian mode. So we use esdhc_read32() to read Host controller capabilities register for LS1. For LS1, when using CMD12, cmdtype need to be set to ABORT, otherwise, next read command will hang. Signed-off-by: Alison Wang <alison.wang@freescale.com>
2014-09-08esdhc: Add CONFIG_SYS_FSL_ESDHC_LE and CONFIG_SYS_FSL_ESDHC_BE macrosWang Huan
For LS102xA, the processor is in little-endian mode, while esdhc IP is in big-endian mode. CONFIG_SYS_FSL_ESDHC_LE and CONFIG_SYS_FSL_ESDHC_BE are added. So accessing ESDHC registers can be determined by ESDHC IP's endian mode. Signed-off-by: Alison Wang <alison.wang@freescale.com>
2014-09-08ls102xa: etsec: Add etsec support for LS102xAAlison Wang
This patch is to add etsec support for LS102xA. First, Little-endian descriptor mode should be enabled. So RxBDs and TxBDs are interpreted with little-endian byte ordering. Second, TSEC_SIZE and TSEC_MDIO_OFFSET are different from PowerPC, redefine them for LS1021xA. Signed-off-by: Alison Wang <alison.wang@freescale.com>
2014-09-08net: mdio: Use mb() to be compatible for both ARM and PowerPCAlison Wang
Use mb() instead of sync assembly instruction to be compatible for both ARM and PowerPC. Signed-off-by: Alison Wang <alison.wang@freescale.com>
2014-09-08net: Merge asm/fsl_enet.h into fsl_mdio.hClaudiu Manoil
fsl_enet.h defines the mapping of the usual MII management registers, which are included in the MDIO register block common to Freescale ethernet controllers. So it shouldn't depend on the CPU architecture but it should be actually part of the arch independent fsl_mdio.h. To remove the arch dependency, merge the content of asm/fsl_enet.h into fsl_mdio.h. Some files (like fm_eth.h) were simply including fsl_enet.h only for phy.h. These were updated to include phy.h instead. Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
2014-09-08ls102xa: i2c: Add i2c support for LS102xAWang Huan
The existing i.MX's I2C driver mxc_i2c.c is compatible with the controller of LS102xA. As I2C's registers are 8-bit on LS102xA, I2C_QUIRK_REG is enabled to use 8-bit driver. This patch is to add I2C 1,2,3 support for LS102xA. Signed-off-by: Alison Wang <alison.wang@freescale.com>
2014-09-08arm: ls102xa: Add Freescale LS102xA SoC supportWang Huan
The QorIQ LS1 family is built on Layerscape architecture, the industry's first software-aware, core-agnostic networking architecture to offer unprecedented efficiency and scale. Freescale LS102xA is a set of SoCs combines two ARM Cortex-A7 cores that have been optimized for high reliability and pack the highest level of integration available for sub-3 W embedded communications processors with Layerscape architecture and with a comprehensive enablement model focused on ease of programmability. Signed-off-by: Alison Wang <alison.wang@freescale.com> Signed-off-by: Jason Jin <jason.jin@freescale.com> Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2014-09-05patman: Fix detection of git versionSimon Glass
A missing 'global' declaration means that this feature does not currently work. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-09-05buildman: Separate out display of warnings and errorsSimon Glass
Some boards unfortunately build with warnings and it is useful to be able to easily distinguish the warnings from the errors. Use a simple pattern match to categorise gcc output into warnings and errors, and display each separately. New warnings are shown in magenta (with a w+ prefix) and fixed warnings are shown in yellow with a w- prefix. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-09-05buildman: Add an option to show which boards caused which errorsSimon Glass
Add a -l option to display a list of offending boards against each error/warning line. The information will be shown in brackets as below: 02: wip sandbox: + sandbox arm: + seaboard +(sandbox) arch/sandbox/cpu/cpu.c: In function 'timer_get_us': +(sandbox) arch/sandbox/cpu/cpu.c:40:9: warning: unused variable 'i' [-Wunused-variable] +(seaboard) board/nvidia/seaboard/seaboard.c: In function 'pin_mux_mmc': +(seaboard) board/nvidia/seaboard/seaboard.c:36:9: warning: unused variable 'fred' [-Wunused-variable] +(seaboard) int fred; +(seaboard) ^ Signed-off-by: Simon Glass <sjg@chromium.org>
2014-09-05buildman: Remove the directory prefix from each error lineSimon Glass
The full path is long and also includes buildman private directories. Clean this up, so that only a relative U-Boot path is shown. This will change warnings like these: /home/sjg/c/src/third_party/u-boot/buildman5/.bm-work/00/arch/sandbox/cpu/cpu.c: In function 'timer_get_us': /home/sjg/c/src/third_party/u-boot/buildman5/.bm-work/00/arch/sandbox/cpu/cpu.c:40:9: warning: unused variable 'i' [-Wunused-variable] /home/sjg/c/src/third_party/u-boot/files/arch/sandbox/cpu/cpu.c: In function 'timer_get_us': /home/sjg/c/src/third_party/u-boot/files/arch/sandbox/cpu/cpu.c:40:9: warning: unused variable 'i' [-Wunused-variable] to: arch/sandbox/cpu/cpu.c: In function 'timer_get_us': arch/sandbox/cpu/cpu.c:40:9: warning: unused variable 'i' [-Wunused-variable] Signed-off-by: Simon Glass <sjg@chromium.org>
2014-09-05buildman: Implement an option to exclude boards from the buildSimon Glass
Some boards are known to be broken and it is convenient to be able to exclude them from the build. Add an --exclude option to specific boards to exclude. This uses the same matching rules as the normal 'include' arguments, and is a comma- separated list of regular expressions. Suggested-by: York Sun <yorksun@freescale.com> Signed-off-by: Simon Glass <sjg@chromium.org>
2014-09-05buildman: Allow make-flags variables to include '-' and '_'Simon Glass
These characters are commonly used in variables, so permit them. Also document the permitted characters. Reported-by: Tom Rini <trini@ti.com> Signed-off-by: Simon Glass <sjg@chromium.org>
2014-09-05buildman: Set the return code to indicate build resultSimon Glass
When buildman finds errors/warnings when building, set the return code to indicate this. Suggested-by: York Sun <yorksun@freescale.com> Signed-off-by: Simon Glass <sjg@chromium.org>
2014-09-05patman: Avoid changing the order of tagsSimon Glass
patman collects tags that it sees in the commit and places them nicely sorted at the end of the patch. However, this is not really necessary and in fact is apparently not desirable. Suggested-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-09-05patman: Use --no-pager' to stop git from forking a pagerSimon Glass
In a headless environment the pager can apparently hang. We don't want a pager anyway so let's request that none be used. Reported-by: Tom Rini <trini@ti.com> Signed-off-by: Simon Glass <sjg@chromium.org>
2014-09-05patman: Remove the -a optionSimon Glass
It seems that this is no longer needed, since checkpatch.pl will catch whitespace problems in patches. Also the option is not widely used, so it seems safe to just remove it. Suggested-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Signed-off-by: Simon Glass <sjg@chromium.org>
2014-09-05patman: Correct unit tests to run correctlySimon Glass
It seems that doctest behaves differently now, and some of the unit tests do not run. Adjust the tests to work correctly. ./tools/patman/patman --test <unittest.result.TestResult run=10 errors=0 failures=0> Signed-off-by: Simon Glass <sjg@chromium.org>
2014-09-05patman: Fix indentation in terminal.pySimon Glass
This code came from a different project with 2-character indentation. Fix it for U-Boot. Signed-off-by: Simon Glass <sjg@chromium.org>
2014-09-05CONFIGS: peach-pit: Enable display for peach_pit boardAjay Kumar
Enable drivers for FIMD, DP and parade bridge chip. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-09-05ARM: exynos: peach_pit: Add DT nodes for fimd and parade bridge chipAjay Kumar
This patch adds DT properties for fimd and the parade bridge chip present on peach_pit. The panel supports 1366x768 resolution. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-09-05exynos5420: add callbacks needed for exynos_fb driverAjay Kumar
Add initialization code for peach_pit panel, parade bridge chip, and backlight. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-09-05ARM: exynos: Add missing declaration for gpio_direction_inputAjay Kumar
This patch adds missing declaration for gpio_direction_input function, thereby helps in resolving compilation warnings. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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