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2019-05-08rockchip: rk3399: add tpl supportKever Yang
Rockchip platform suppose to use TPL(run in SRAM) as dram init and SPL(run in DDR SDRAM) as pre-loader, so that the SPL would not be limited by SRAM size. This patch add rk3399-board-tpl.c and its common configs. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08rockchip: add u-boot-tpl-v8.ldsKever Yang
We don't have both sram and sdram in TPL, so update from: arch/arm/cpu/armv8/u-boot-spl.lds Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-05-08rockchip: px5: add timer0 dts node as tick timerKever Yang
Let's use rockchip timer before stimer patches can be merged. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08rockchip: rk3368: remove uart iomux init in SPLKever Yang
The iomux should have been set in board_debug_uart_init(), do not set in board_init_f(), remove it. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08rockchip: dmc: rk3368: update rank number for evb-px5Kever Yang
evb-px5 has only 1 CS, update for it. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Andy Yan <andy.yan@rock-chips.com>
2019-05-08rockchip: boot0: update CONFIG_ROCKCHIP_SPL_RESERVE_IRAM for SPL onlyKever Yang
The CONFIG_ROCKCHIP_SPL_RESERVE_IRAM is for SPL only, add condition to limit it not affect TPL. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08rockchip: px5: update defconfig for TPL/SPLKever Yang
Add options to support TPL. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08rockchip: px5: update SPL size for spl/tplKever Yang
Use larger space for load bl31 in SPL Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Andy Yan <andy.yan@rock-chips.com>
2019-05-08rockchip: px5 update dts for spl/tplKever Yang
TPL need dmc to init ddr sdram, and emmc, boot-order. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Andy Yan <andy.yan@rock-chips.com>
2019-05-08rockchip: rk3368: support UART2/4 in board_debug_uart_init()Kever Yang
evb-rk3368 is using UART2 and PX5 evb is using UART4 Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Andy Yan <andy.yan@rock-chips.com>
2019-05-08rockchip: evb-rk322x: update defconfig with tpl and optee supportKever Yang
Enable all the options for TPL/SPL and OPTEE. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08rockchip: evb-rk3229: add README file for OP-TEE supportKever Yang
Detail of step by step to bring up the board with OP-TEE support. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08rockchip: evb-rk3229: remove unnecessary definesKever Yang
Prefer to use default setting like other SoCs. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08rockchip: rk322x: dts: enable uart2 for SPL/TPLKever Yang
When we use DM_SERIAL for serial driver, we need enable the dts node for the debug console. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08sysreset: enable driver support in SPL/TPLKever Yang
SPL/TPL also need use sysreset for some feature like panic callback. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08rockchip: rk322x: add tpl supportKever Yang
Move original spl to tpl, and add spl to load next stage firmware, adapt all the address and option for them. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08rockchip: clk: rk322x: fix assert clock valueKever Yang
BUS_PCLK_HZ and BUS_HCLK_HZ are from BUS_ACLK_HZ, not from GPLL_HZ. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08rockchip: rk322x: add CLK_EMMC_SAMPLE clock supportKever Yang
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08arm: add a separate stack for TPLKever Yang
TPL stack may different from SPL and sys stack, add support for separate one when the board defines it. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08arm: add option for TPL support in arm 32bitKever Yang
Some options like TPL_SYS_THUMB_BUILD, TPL_USE_ARCH_MEMCPY and TPL_USE_ARCH_MEMCPY are needed for TPL build in 32bit arm. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08Revert "rockchip: rk322x: ram: enable DRAM init in SPL instead of TPL"Kever Yang
This reverts commit f338cca1d2bce906b049722d2fdbf527a4963b61. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08arm: remove ARCH_ROCKCHIP macro in common codeKever Yang
This is fix to: e2a12f590d rockchip: use 'arch-rockchip' as header file path The V2 of origin patch set has fix this, but we merge V1 by mistake, so lets correct it. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08rockchip: add common header boot0.h and gpio.h for socKever Yang
boot0.h and gpio.h will be used by system and include by 'asm/arch/', each of them need of a copy from 'asm/arch-rockchip'. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2019-05-08x86: samus: Add a target to boot through TPLSimon Glass
Add a version of samus which supports booting from TPL to SPL and then to U-Boot. This allows TPL to select from an A or B SPL to support verified boot with field upgrade. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: samus: Update device tree for verified bootSimon Glass
Add nvdata drivers for the TPM and RTC as used on samus. These are needed for Chromium OS verified boot on samus. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: samus: Update device tree for SPLSimon Glass
Add tags to allow required nodes to be present in SPL / TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: Add a simple TPL implementationSimon Glass
Add the required CPU code so that TPL builds correctly. Also update the SPL code to deal with being booted from TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: Add a way to jump from TPL to SPLSimon Glass
When TPL finishes it needs to jump to SPL with the stack set up correctly. Add a function to handle this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: samus: Increase the pre-reloc memory againSimon Glass
This is again too small, so increase it slightly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: broadwell: Update PCH to work in TPLSimon Glass
The early init should only happen once. Update the probe method to deal with TPL, SPL and U-Boot proper. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: Enable the RTC on all boardsSimon Glass
With the move to Kconfig this option should be set in Kconfig, not in the config header file. Move it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: Fix device-tree indentationSimon Glass
With the use of a phandle we can outdent the device tree nodes a little. Fix this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: Update device tree for Chromium OS verified bootSimon Glass
The standard image generated by U-Boot on x86 is u-boot.rom. Add a separate image called image.bin for verified boot. This supports verification in TPL of which SPL/U-Boot to start, then jumping to the correct one, with SPL setting up the SDRAM and U-Boot proper providing the user interface if needed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: Update device tree for TPLSimon Glass
Add TPL binaries to the device x86 binman desciption. When enabled, TPL will start first, doing the 16-bit init, then jump to SPL and finally U-Boot proper. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: Add documentation on the samus flashmapSimon Glass
There are quite a few variables which control where things appear in the final ROM image. Add a flashmap in the documentation to make this easier to figure out. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed "x86: Update the memory map a little" in] [bmeng: fixed typo of 'documentation' in the commit title] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: Support PCI VGA ROM when TPL is usedSimon Glass
When TPL is in use, U-Boot proper should support initing the VGA ROM even though the 32-bit init portion is in SPL. Update the condition to handle this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: Don't generate a bootstage report in SPLSimon Glass
This report is normally generated by U-Boot proper. Correct the condition here so that it respects the Kconfig options for bootstage. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: Don't set up MTRRs in SPLSimon Glass
The MTRRs are normally set up in U-Boot proper, so avoid setting them up in SPL as well. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: Support TPL in Intel common codeSimon Glass
Update the Makefie rules to ensure that the correct files are built when TPL is being used. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: sysreset: Implement the get_last() methodSimon Glass
Add a default implementation of this method which always indicates that the last reset was a power-on reset. This is the most likely type of reset and without a PCH-specific driver we cannot determine any other type. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: sysreset: Implement power-off if availableSimon Glass
On modern x86 devices we can power the system off using the power- management features of the PCH. Add an implementation for this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: sysreset: Separate out the EFI codeSimon Glass
The EFI implementation of reset sits inside the driver and is called directly from outside the driver, breaking the normal driver-model conventions. Worse, it passed NULL as the device pointer, hoping that the called function won't use it, which breaks as soon as code is added to use it. Separate out the implementation to improve the situation enough to allow a future patch to add new sysreset features. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: broadwell: Implement PCH_REQ_PMBASE_INFOSimon Glass
Implement this ioctl() to support power off. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: ivybridge: Implement PCH_REQ_PMBASE_INFOSimon Glass
Implement this ioctl() to support power off. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: pch: Add an ioctl to read power-management infoSimon Glass
Add a new ioctl() request to read information about the power-management system. This can be used to power off the device. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: mrccache: Add more debuggingSimon Glass
When the MRC cache fails to save it is useful to have some debugging info to indicate what when wrong. Add some more debug() calls. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: Support saving MRC data from SPLSimon Glass
When SPL is used to set up the memory controller we want to save the MRC data in SPL to avoid needing to pass it up to U-Boot proper to save. Add a function to handle that. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: Add common Intel code for SPLSimon Glass
Add an implementation of arch_cpu_init_f() so that the x86 SPL code builds and identifies the CPU. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: broadwell: Select refcode and CPU code for SPLSimon Glass
Allow broadwell to build for SPL and include the reference code. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: broadwell: Allow booting from SPLSimon Glass
At present broadwell only supports booting straight into U-Boot proper. Add a separate init file to boot from SPL into U-Boot proper, and select it when SPL is in use. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
generated by cgit (git 2.34.1) at 2024-12-24 05:13:30 +0000