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2020-05-29usb: dwc3: amend UTMI/UTMIW phy interface setupFrank Wang
Let move 8/16-bit UTMI+ interface initialization into DWC3 core init that is convenient for both DM_USB and u-boot traditional process. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-29usb: dwc3: Enable AutoRetry feature in the controllerJagan Teki
By default when core sees any transaction error (CRC or overflow) it replies with terminating retry ACK (Retry=1 and Nump == 0). Enabling this Auto Retry feature in controller will make the core send a non-terminanting ACK upon such transaction errors. That is, ACK TP with Retry=1 and Nump != 0. Doing so will give controller a chance to recover from transient error conditions. Reference from below Linux commit, commit <b138e23d3dff> ("usb: dwc3: core: Enable AutoRetry feature in the controller") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-29usb: dwc3: Add disable u2mac linestate check quirkJagan Teki
This patch adds a quirk to disable USB 2.0 MAC linestate check during HS transmit. Refer the dwc3 databook, we can use it for some special platforms if the linestate not reflect the expected line state(J) during transmission. When use this quirk, the controller implements a fixed 40-bit TxEndDelay after the packet is given on UTMI and ignores the linestate during the transmit of a token (during token-to-token and token-to-data IPGAP). On some rockchip platforms (e.g. rk3399), it requires to disable the u2mac linestate check to decrease the SSPLIT token to SETUP token inter-packet delay from 566ns to 466ns, and fix the issue that FS/LS devices not recognized if inserted through USB 3.0 HUB. Reference from below Linux commit, commit <65db7a0c9816> ("usb: dwc3: add disable u2mac linestate check quirk") Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-29usb: dwc3: add dis_u2_freeclk_exists_quirkFrank Wang
Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit, which specifies whether the USB2.0 PHY provides a free-running PHY clock, which is active when the clock control input is active. Refer to commit 27f83eeb6b42("usb: dwc3: add dis_u2_freeclk_exists_quirk") in Linux Rockchip Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2020-05-29usb: dwc3: add dis_enblslpm_quirkFrank Wang
Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls whether the PHY receives the suspend signal from the controller. Refer to commit ec791d149bca("usb: dwc3: Add dis_enblslpm_quirk") in Linux Kernel. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2020-05-29phy: rockchip: Add Rockchip USB TypeC PHY driverJagan Teki
Add USB TYPEC PHY driver for rockchip platform. Referenced from Linux TypeC PHY driver, currently supporting usb3-port and dp-port need to add it in the future. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-29phy: rockchip: Add Rockchip USB2PHY driverJagan Teki
Add Rockchip USB2PHY driver with initial support. This will help to use it for EHCI controller in host mode, and USB 3.0 controller in otg mode. More functionality like charge, vbus detection will add it in future changes. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-29arm: mach-rockchip: bind sub-nodes for rk3399_sysconFrank Wang
There are some sub-nodes under the grf DT, so add bind callback function in rk3399 syscon driver to scan them recursively. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> # roc-rk3399-pc Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-29clk: rk3399: Enable/Disable TCPHY clocksJagan Teki
Enable/Disable TCPHY clock for rk3399 platform. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-29clk: rk3399: Set empty for TCPHY assigned-clocksJagan Teki
Due to v5.7-rc1 sync the SD controller nodes in rk3399.dtsi have SCLK_UPHY0_TCPDCORE, SCLK_UPHY1_TCPDCORE assigned-clocks which are usually required for Linux and don't require to handle them in U-Boot. assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>; assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>; So, mark them as empty in clock otherwise device probe on those typec phy driver would fail. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-29clk: rk3399: Enable/Disable the USB2PHY clkJagan Teki
Enable/Disable the USB2PHY clk for rk3399. CLK is clear in enable and set in disable functionality. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-29doc: rockchip: Remove list of supported boardsWalter Lozano
As documentation is being moved to doc/boards/rockchip create a warning message and remove the redundant list of supported boards. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-29doc: board: rockchip: Add missing supported boardsWalter Lozano
Update the list of supported boards with the information available on doc/README.rockchip. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-29doc: board: rockchip: Improve supported board list formatWalter Lozano
As an additional step to move documentation to doc/boards/rockchip improve format of the supported board list to make it more readable. Additionally, add the configuration files used to build them based on doc/README.rockchip. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-29rockchip: enable USB OHCI host for RockPro64Marcin Juszkiewicz
U-Boot has video output enabled so time to get keyboard working. => usb reset;usb tree resetting USB... Bus usb@fe380000: USB EHCI 1.00 Bus usb@fe3a0000: USB OHCI 1.0 Bus usb@fe3c0000: USB EHCI 1.00 Bus usb@fe3e0000: USB OHCI 1.0 Bus dwc3: usb maximum-speed not found Register 2000140 NbrPorts 2 Starting the controller USB XHCI 1.10 scanning bus usb@fe380000 for devices... 1 USB Device(s) found scanning bus usb@fe3a0000 for devices... 1 USB Device(s) found scanning bus usb@fe3c0000 for devices... 1 USB Device(s) found scanning bus usb@fe3e0000 for devices... 3 USB Device(s) found scanning bus dwc3 for devices... cannot reset port 1!? 2 USB Device(s) found scanning usb for storage devices... 2 Storage Device(s) found USB device tree: 1 Hub (480 Mb/s, 0mA) u-boot EHCI Host Controller 1 Hub (12 Mb/s, 0mA) U-Boot Root Hub 1 Hub (480 Mb/s, 0mA) u-boot EHCI Host Controller 1 Hub (12 Mb/s, 0mA) | U-Boot Root Hub | +-2 Hub (12 Mb/s, 100mA) | ALCOR Generic USB Hub | +-3 Mass Storage (12 Mb/s, 200mA) Kingston DT 101 G2 001478544887BB3157380157 1 Hub (5 Gb/s, 0mA) | U-Boot XHCI Host Controller | +-2 Mass Storage (5 Gb/s, 76mA) ADATA ADATA USB Flash Drive 1520405012240002 Signed-off-by: Marcin Juszkiewicz <marcin@juszkiewicz.com.pl> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-29rk3399: Enable NVMe distro bootcmdMark Kettenis
Include NVME in the list of boot targets if CONFIG_NVME is enabled. Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-29pci: Make Rockchip PCIe voltage regulators optionalMark Kettenis
The vpcie*-supply properties are optional and these are absent on boards like the ROCKPro64 and Firefly RK3399 where the voltage is supplied by always-on regulators that are already enabled upon boot. Make these regulators optional and properly check their presence before attempting to enable them. Makes PCIe work on un U-Boot on the boards mentioned above. Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Marcin Juszkiewicz <marcin@juszkiewicz.com.pl>
2020-05-29doc: rockchip: Document eMMC program stepsJagan Teki
Document eMMC partition creation and program steps for rockchip platforms. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-29nanopc-t4: Enable USB GadgetJagan Teki
Enable DWC3 core, gadget for nanopc-t4 board. This would help to use fastboot by default. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-29arm64: dts: rk3399-nanopi4: Add u-boot,spl-boot-orderJagan Teki
Add u-boot,spl-boot-order as sdhci and sdmmc for booting from eMMC and SD card. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-29clk: rk3399: Fix eMMC get_clk reg offsetJagan Teki
Actual eMMC get_clk register is clksel_con22 instead of clksel_con21. Fix it. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-29rockchip: Fix spl mmc boot device ofpathJagan Teki
Linux v5.7-rc1 dts(i) sync has changed the sdmmc node from dwmmc@fe320000 to mmc@fe320000 and this ofpath is being used in rockchip spl bootdevice code. So, update the ofpath with a new node name and prefix "same-as-spl" to missing u-boot,spl-boot-order. Bug log: U-Boot SPL 2020.07-rc2-00256-g9c5fef5774 (May 24 2020 - 20:20:43 +0530) Trying to boot from MMC2 mmc_load_image_raw_sector: mmc block read error Trying to boot from MMC1 mmc_load_image_raw_sector: mmc block read error SPL: failed to boot from all boot devices Fixes: 167efc2c7a46 ("arm64: dts: rk3399: Sync v5.7-rc1 from Linux" Signed-off-by: Suniel Mahesh <sunil@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-29arm: dts: meson-gxl: fix USB gadget by adding missing nodes for U-BootNeil Armstrong
The khadas-vim, khadas-vim2, libretech-ac & libretech-*-pc boards were missing DT tweak to enable USB gadget. Add them to their -u-boot.dtsi files and include the right gxl-u-boot.dtsi. Fixes: a19e8a0f03 ("arm: dts: meson-gxl: Add USB Gadget nodes for U-Boot") Reported-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-05-29configs: khadas-vim3: enable HDMI outputNeil Armstrong
Enable options to permit HDMI output on Khadas VIM3 & VIM3L boards. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-05-29arm: dts: khadas-vim3: include meson-g12-common-u-boot.dtsi to enable HDMI ↵Neil Armstrong
output Include the common g12 u-boot tweaks to permit enabling video output tweaks on Khadas VIM3 boards. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-05-28ARM: dts: stm32: Disable SDR104 mode on AV96Marek Vasut
Disable SDR104 mode until we know it is really stable. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-05-28ARM: dts: stm32: Repair I2C2 operation on AV96Marek Vasut
The I2C2 uses different pinmux on AV96, use correct pinmux and also add comments about the I2C being present on the "low-speed" expansion connector X6. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-05-28ARM: dts: stm32: Add alternate pinmux for I2C2 pinsMarek Vasut
Add another mux option for I2C2 pins, this is used on AV96 board. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-05-28ARM: stm32: Hog GPIO PF7 high on DHCOR to unlock SPI NOR nWPMarek Vasut
The SPI NOR nWP line is connected to GPIO PF7 on the SoM, pull the GPIO line high by default to clear SPI NOR WP. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-05-28ARM: stm32: Re-enable KS8851 on DHCOMMarek Vasut
Since the KS8851 driver is now in, enable the Kconfig entry on DHCOM to make the second ethernet available. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-05-28misc: i2c_eeprom: implement different probe test eeprom offsetEugen Hristev
Because of this commit : 5ae84860b0 ("misc: i2c_eeprom: verify that the chip is functional at probe()") at probe time, each eeprom is tested for read at offset 0. The Atmel AT24MAC402 eeprom has different mapping. One i2c slave address is used for the lower 0x80 bytes and another i2c slave address is used for the upper 0x80 bytes. Because of this basically the i2c master sees 2 different slaves. We need the upper bytes because we read the unique MAC address from this EEPROM area. However this implies that our slave address will return error on reads from address 0x0 to 0x80. To solve this, implemented an offset field inside platform data that is by default 0 (as it is used now), but can be changed in the compatible table. The probe function will now read at this offset and use it, instead of blindly checking offset 0. This will fix the regression noticed on these EEPROMs since the commit abovementioned that introduces the probe failed issue. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2020-05-28i2c: observe scl_count in i2c_deblock_gpio_loop()Heinrich Schuchardt
When compiling with -Wtype-limits we see this error: drivers/i2c/i2c-uclass.c: In function ‘i2c_deblock_gpio_loop’: drivers/i2c/i2c-uclass.c:517:21: error: comparison of unsigned expression >= 0 is always true [-Werror=type-limits] 517 | while (scl_count-- >= 0) { | Don't loop forever. Fixes: 1f746a2c82b1 ("i2c: Make deblock delay and SCL clock configurable") Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-05-28i2c: designware_i2c: Check if the device is poweredRaul E Rangel
If the device doesn't return a version that means the device is non-functional. The dw_i2c_regs had invalid offsets for the version field. I got the correct value from the DesignWare databook. It also matches what the Picasso PPR says. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Tested on chromebook_coral: Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-28i2c: designware_i2c: Tidy up use of NULL privSimon Glass
At present we still have pre-driver-model code in this driver and it makes things a bit confusing. In particular calc_bus_speed() is called with priv as NULL if not using driver model. This results in spk_cnt and comp_param1 being read from an invalid address if not using driver model. For comp_param1 this may not cause problems if reading from addresses close to 0 happens to be allowed, as high speed is only supported by DM code. But spk_cnt is subsequently used to calculate the bus periods and so this may cause problems (e.g. on spear600 board which has not been migrated yet). Add a new parameter regs parameter to calc_bus_speed() and add more comments to this function and to _dw_i2c_set_bus_speed(), which calls it. Signed-off-by: Simon Glass <sjg@chromium.org> Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-05-28mtd: spinand: toshiba: Support for new Kioxia Serial NANDYoshio Furuyama
Add support for new Kioxia products. The new Kioxia products support program load x4 command, and have HOLD_D bit which is equivalent to QE bit. Signed-off-by: Yoshio Furuyama <ytc-mb-yfuruyama7@kioxia.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/aa69e455beedc5ce0d7141359b9364ed8aec9e65.1584949601.git.ytc-mb-yfuruyama7@kioxia.com Signed-off-by: Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-05-28mtd: spinand: toshiba: Rename function name to change suffix and prefix (8Gbit)Yoshio Furuyama
The suffix was changed from "G" to "J" to classify between 1st generation and 2nd generation serial NAND devices (which now belong to the Kioxia brand). As reference that's 1st generation device of 1Gbit product is "TC58CVG0S3HRAIG" 2nd generation device of 1Gbit product is "TC58CVG0S3HRAIJ". The 8Gbit type "TH58CxG3S0HRAIJ" is new to Kioxia's serial NAND lineup and the prefix was changed from "TC58" to "TH58". Thus the functions were renamed from tc58cxgxsx_*() to tx58cxgxsxraix_*(). Signed-off-by: Yoshio Furuyama <ytc-mb-yfuruyama7@kioxia.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/linux-mtd/0dedd9869569a17625822dba87878254d253ba0e.1584949601.git.ytc-mb-yfuruyama7@kioxia.com Signed-off-by: Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-05-27Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvellTom Rini
- Fix SPI boot on ds414 (Ezra) - Fix PHY mode definition on armada-3720-uDPU (Jakov) - Convert CRS305-1G-4S to generic version (Luka)
2020-05-27Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86Tom Rini
- Use device tree for FSP-M and FSP-S configuration on Intel Apollo Lake - Add SMBIOS cbmem entry parsing for coreboot - Various clean-ups to CBFS implementation
2020-05-27cbfs: Don't require the CBFS size with cbfs_init_mem()Simon Glass
The size is not actually used since it is present in the header. Drop this parameter. Also tidy up error handling while we are here. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-05-27cbfs: Allow reading a file from a CBFS given its base addrSimon Glass
Currently we support reading a file from CBFS given the address of the end of the ROM. Sometimes we only know the start of the CBFS. Add a function to find a file given that. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-05-27cbfs: Change file_cbfs_find_uncached() to return an errorSimon Glass
This function currently returns a node pointer so there is no way to know the error code. Also it uses data in BSS which seems unnecessary since the caller might prefer to use a local variable. Update the function and split its body out into a separate function so we can use it later. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-05-27cbfs: Return the error code from file_cbfs_init()Simon Glass
We may as well return the error code and use it directly in the command code. CBFS still uses its own error enum which we may be able to remove, but leave it for now. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-05-27cbfs: Record the start address in cbfs_privSimon Glass
The start address of the CBFS is used when scanning for files. It makes sense to put this in our cbfs_priv struct and calculate it when we read the header. Update the code accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-05-27cbfs: Use void * for the position pointersSimon Glass
It doesn't make sense to use u8 * as the pointer type for accessing the CBFS since we do not access it as bytes, but via structures. Change it to void *, which allows us to avoid a cast. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-05-27cbfs: Unify the two header loadersSimon Glass
These two functions have mostly the same code. Pull this out into a common function. Also make this function zero the private data so that callers don't have to do it. Finally, update cbfs_load_header_ptr() to take the base of the ROM as its parameter, which makes more sense than passing the address of the header within the ROM. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-05-27cbfs: Adjust cbfs_load_header_ptr() to use cbfs_privSimon Glass
This function is strange at the moment in that it takes a header pointer but then accesses the cbfs_s global. Currently clients have their own priv pointer, so update the function to take that as a parameter instead. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-05-27cbfs: Adjust file_cbfs_load_header() to use cbfs_privSimon Glass
This function is strange at the moment in that it takes a header pointer but then accesses the cbfs_s global. Currently clients have their own priv pointer, so update the function to take that as a parameter instead. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-05-27cbfs: Adjust return value of file_cbfs_next_file()Simon Glass
At present this uses a true return to indicate it found a file. Adjust it to use 0 for this, so it is consistent with other functions. Update its callers accordingly and add a check for malloc() failure in file_cbfs_fill_cache(). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-05-27cbfs: Use bool type for whether initialisedSimon Glass
At present this uses an int type. U-Boot now supports bool so use this instead. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-05-27cbfs: Use ulong consistentlySimon Glass
U-Boot uses ulong for addresses but there are a few places in this driver that don't use it. Convert this driver over to follow this convention fully. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
generated by cgit (git 2.34.1) at 2025-01-07 16:15:10 +0000