summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2019-12-27rockchip: add description for TPL_ROCKCHIP_COMMON_BOARDThomas Hebb
SPL_ROCKCHIP_COMMON_BOARD, an almost identical option, has a title but this one doesn't for some reason. Add a description to make the menu easier to read. Signed-off-by: Thomas Hebb <tommyhebb@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-12-27rockchip: px30-firefly add standalone dtsKever Yang
Firefly Core-PX30-JD4 use UART2M1 while PX30 evb using UART2M0, the U-Boot proper will use the dts setting to do the IOMUX init, and a separate dts is needed for px30-firefly. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-12-27rockchip: firefly-px30: Fix the MACRO for CONFIG_DEBUG_UART2_CHANNELKever Yang
The Macro has update without update the defconfig, update the defconfig to make Mcaro correct. Fixes: ec4fafdf1f ("rockchip: px30: Rename CONFIG_DEBUG_UART2_CHANNEL to...") Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-12-27rockchip: make_fit_atf: explicitly use python3Jack Mitchell
On a distribution with no python2 installed and no python->python3 symlink the script will fail to execute. Specify python3 explicitly as it's already a requirement to build u-boot. Signed-off-by: Jack Mitchell <ml@embed.me.uk> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-12-26Merge branch '2019-12-26-ti-imports'Tom Rini
- Update maintainer on omapl138_lcdk - Match TRM sequence & settings in the TI pipe3 PHY
2019-12-26board: davinci: Update OMAPL138_LCDK maintainerLokesh Vutla
As per the email discussion[0], add myself as a maintainer to OMAPL138_LCDK and drop Peter's entry. [0] http://u-boot.10912.n7.nabble.com/OMAP-L138-LCDK-giving-up-maintainership-td394211.html Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-12-26phy: ti-pipe3: Fix SATA & USB PHY power up sequenceRoger Quadros
As per "Table 26-7. SATA PHY Subsystem Low-Level Programming Sequence" in TRM [1] we need to turn on SATA_PHY_TX before SATA_PHY_RX. [1] DRA75x, DRA74x TRM - http://www.ti.com/lit/ug/sprui30f/sprui30f.pdf Signed-off-by: Roger Quadros <rogerq@ti.com>
2019-12-26phy: ti-pipe3: improve DPLL stability for SATA & USBRoger Quadros
For increased DPLL stability use the settings recommended in the TRM [1] for PHY_RX registers for SATA and USB. For SATA we need to use spread spectrum settings even though we don't have spread spectrum enabled. The suggested non-spread spectrum settings don't work. [1] DRA75x, DRA74x TRM - http://www.ti.com/lit/ug/sprui30f/sprui30f.pdf Signed-off-by: Roger Quadros <rogerq@ti.com>
2019-12-26phy: ti-pipe3: Introduce mode property in driver dataRoger Quadros
Introduce a mode property in the driver data so that we don't have to keep using "of_device_is_compatible()" throughtout the driver. No functional change. Signed-off-by: Roger Quadros <rogerq@ti.com>
2019-12-26phy: ti-pipe3: Use TRM recommended settings for SATA DPLLRoger Quadros
The AM572x Technical Reference Manual, SPRUHZ6H, Revised November 2016 [1], shows recommended settings for the SATA DPLL in Table 26-8. DPLL CLKDCOLDO Recommended Settings. Use those settings in the driver. The TRM does not show a value for 20MHz SYS_CLK so we use something close to the 26MHz setting. [1] - http://www.ti.com/lit/ug/spruhz6h/spruhz6h.pdf Signed-off-by: Roger Quadros <rogerq@ti.com>
2019-12-26rockchip: rk3288-evb: update config to support OPTEEKever Yang
Upstream kernel and rockchip kernel has default enable PSCI which needs OPTEE in trust word, enable OPTEE support for evb by default and SPL_FIT option to pack OPTEE with U-Boot proper. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-12-26rockchip: rk3288-evb: update CONFIG_NR_DRAM_BANKS to 2Kever Yang
The OPTEE will use the ram start at 0x8400000 which make the DRAM be two banks. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-12-26rockchip: rk3288-evb: update SPL_STACK/MALLOC_LEN config with rk3399Kever Yang
Update the SPL_STACK_R_MALLOC_SIMPLE_LEN which also including space for STACK and the size may not enough when loding FIT image in SPL. If the size is not enough, you can see log like this when loding FIT: U-Boot TPL 2020.01-rc3-00082-g4b19b89ca4-dirty (Dec 05 2019 - 11:52:53) Trying to boot from BOOTROM Returning to boot ROM... U-Boot SPL 2020.01-rc3-00082-g4b19b89ca4-dirty (Dec 05 2019 - 11:52:53 +0800) Trying to boot from MMC2 And if enable the DEBUG for everyting in SPL, the log will hang at dwmmc sending CMD16 for 'uboot' loadables binary because this step need a large stack cost(about 0x2d00). External data: dst=8400000, offset=72638, size=b3580 Image OS is Trusted Execution Environment board_fit_config_name_match: rk3288-evb Selecting config 'rk3288-evb'loadables: 'uboot' blk_find_device: if_type=6, devnum=1: dwmmc@ff0c0000.blk, 6, 0 blk_find_device: if_type=6, devnum=1: dwmmc@ff0f0000.blk, 6, 1 Sending CMD16 Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-12-26rockchip: fit_spl_optee: get text and optee base from buildKever Yang
Instead of hardcode the base address, we can get them from the build output, eg. get the SYS_TEXT_BASE from .config and get optee base from DRAM_BASE. We can use this script for SoCs with DRAM base not from 0x60000000(rk3229 and many other 32bit Rockchip SoCs), eg. rk3288 DRAM base is 0. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-12-22Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini
- dwc3 and cdns3 bug fixes
2019-12-22Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-netTom Rini
- Fix phy_connect() call in two drivers - fw_setenv bugfix
2019-12-21usb: dwc3: Fix UTMI/UTMIW phy interface initializationJagan Teki
DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-12-21MAINTAINERS: assign usb.c and and usb_kbd.cHeinrich Schuchardt
Marek is already maintaining USB. Assign files common/usb.c and common/usb_kbd.c to him. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-12-21usb: cdns3: ep0: Fix build warnings related to cache opsVignesh Raghavendra
Since, commit 62f9b6544728 ("common: Move older CPU functions to their own header") cache ops functions are declared in a separate header. Include the same to avoid build warnings. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2019-12-20fw_setenv: avoid writing environment when nothing has changedRasmus Villemoes
In the case where one deletes an already-non-existing variable, or sets a variable to the value it already has, there is no point in writing the environment back, thus reducing wear on the underlying storage device. In the case of redundant environments, if the two environments differ (e.g. because one is corrupt), make sure that any call of fw_setenv causes the two to become synchronized, even if the fw_setenv call does not change anything in the good copy. Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-20drivers: net: bcm-sf2: pass -1 to phy_connect()Alex Marginean
Passing 0 to PHY connect used to trigger a MDIO scan due to a bug fixed in the meantime. It's unclear if bcm-sf2 wants to connect to PHY @ addr 0 or is scanning the bus, passing -1 here should keep it functional either way. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Cc: Jiandong Zheng <jdzheng@broadcom.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-20net: dwc_eth_qos: Pass -1 to phy_connect() to scan for all PHYsMarek Vasut
PHY address 0 is a valid PHY address, to scan for all PHYs, pass -1 to phy_connect(). Passing 0 used to work before be accident, but does no longer. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Ramon Fried <rfried.dev@gmail.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-18sunxi: remove __packed from struct sunxi_prcm_regHeinrich Schuchardt
struct sunxi_prcm_reg is naturally packed. There is no need to define it as packed. Defining it as packed leads to compilation errors with GCC 9.2.1: CC arch/arm/lib/reloc_arm_efi.o arch/arm/cpu/armv7/sunxi/psci.c: In function ‘sunxi_cpu_set_power’: :qarch/arm/cpu/armv7/sunxi/psci.c:163:21: error: taking address of packed member of ‘struct sunxi_prcm_reg’ may result in an unaligned pointer value [-Werror=address-of-packed-member] 163 | sunxi_power_switch(&prcm->cpu_pwr_clamp[cpu], &prcm->cpu_pwroff, | ^~~~~~~~~~~~~~~~~~~~~~~~~ Remove __packed attribute from struct sunxi_prcm_reg. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-12-18sun8i: h3: Support H3 variant of Orange Pi Zero Plus 2Diego Rondini
Orangepi Zero Plus 2 is an open-source single-board computer, available in two Allwinner SOC variants, H3 and H5. We add support for H3 variant here, as the H5 is already supported. H3 Orangepi Zero Plus 2 has: - Quad-core Cortex-A7 - 512MB DDR3 - microSD slot and 8GB eMMC - Debug TTL UART - HDMI - Wifi + BT - OTG + power supply Sync dts from linux v5.2 commit: "ARM: dts: sunxi: h3/h5: Remove stale pinctrl-names entry" (sha1: 75f9a058838be9880afd75c4cb14e1bf4fe34a0b) Commit: "ARM: dts: sun8i: h3: Refactor the pinctrl node names" (sha1: a4dc791974e568a15f7f37131729b1a6912f4811) has been avoided as it breaks U-Boot build. Signed-off-by: Diego Rondini <diego.rondini@kynetics.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-12-18sunxi: psci: avoid error address-of-packed-memberHeinrich Schuchardt
Compiling with GCC 9.2.1 leads to build errors: arch/arm/cpu/armv7/sunxi/psci.c: In function ‘sunxi_cpu_set_power’: arch/arm/cpu/armv7/sunxi/psci.c:144:21: error: taking address of packed member of ‘struct sunxi_cpucfg_reg’ may result in an unaligned pointer value [-Werror=address-of-packed-member] 144 | sunxi_power_switch(&cpucfg->cpu1_pwr_clamp, &cpucfg->cpu1_pwroff, | ^~~~~~~~~~~~~~~~~~~~~~~ arch/arm/cpu/armv7/sunxi/psci.c:144:46: error: taking address of packed member of ‘struct sunxi_cpucfg_reg’ may result in an unaligned pointer value [-Werror=address-of-packed-member] 144 | sunxi_power_switch(&cpucfg->cpu1_pwr_clamp, &cpucfg->cpu1_pwroff, | ^~~~~~~~~~~~~~~~~~~~ Use memcpy() and void* pointers to resolve the problem caused by packing the struct sunxi_cpucfg_reg. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
2019-12-18mtd: spi-nor: ids: Add GigaDevice gd25q128Peter Robinson
Add gd25q128 128Mbit chip to spi-nor id table. Tested on Pinebook Pro Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Acked-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> # roc-rk3399-pc Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-12-18Merge tag 'u-boot-stm32-20191218' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-stm - Fix stm32mp1 crash (bootstage) and warning (cls)
2019-12-18stm32mp1: configs: Resync with savedefconfigPatrick Delaunay
Rsync all defconfig files using moveconfig.py Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Acked-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-12-18stm32mp1: remove the imply BOOTSTAGEPatrick Delaunay
This patch is only a temporarily workaround for crash introduced by commit ac9cd4805c8b ("bootstage: Correct relocation algorithm"). The crash occurs because the bootstage struct is not correctly aligned when BOOTSTAGE feature is activated. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Acked-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-12-18stm32mp1: imply CMD_CLSPatrick Delaunay
Activate by default the command CLS (clear screen); this command used in pxe or sysboot command (DISTRO support) when the "menu background" keyword is present. This patch avoid the warning "Unknown command 'cls'" with extlinux.conf: # Generic Distro Configuration file generated by OpenEmbedded menu title Select the boot mode MENU BACKGROUND /splash.bmp TIMEOUT 20 DEFAULT stm32mp157c-ev1-emmc LABEL stm32mp157c-ev1-emmc KERNEL /uImage FDT /stm32mp157c-ev1.dtb APPEND root=/dev/mmcblk1p4 rootwait rw console=ttySTM0,115200 ... Retrieving file: /mmc0_stm32mp157c-ev1_extlinux/extlinux.conf 614 bytes read in 36 ms (16.6 KiB/s) Retrieving file: /splash.bmp 46180 bytes read in 40 ms (1.1 MiB/s) Unknown command 'cls' - try 'help' Select the boot mode 1: stm32mp157c-ev1-sdcard ... Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Acked-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-12-16Prepare v2020.01-rc5Tom Rini
Signed-off-by: Tom Rini <trini@konsulko.com>
2019-12-13Merge branch '2019-12-13-master-imports'Tom Rini
- Assorted minor fixes
2019-12-13arm: ti: dra7: move BOOTP_DNS2 and PHY_TI in defconfigGrygorii Strashko
Move BOOTP_DNS2 and PHY_TI from dra7xx_evm.h to dra7xx_evm_defconfig. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-12-13common: remove duplicate typedef for ucharHeinrich Schuchardt
With commit 37db55b7e9db ("linux/types.h: fix typo unchar") we have a duplicate typedef for uchar. As linux/types.h is included in common.h we don't need another typedef for uchar there. Fixes: 37db55b7e9db ("linux/types.h: fix typo unchar") Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
2019-12-13doc: fitImage: example of a signature nodeHeinrich Schuchardt
Describe that a signature node can be added to a binary device tree using the mkimage tool. Provide an example device tree node. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-12-13mailmap: Update mail address for Boris BrezillonHeinrich Schuchardt
Boris' email address has changed. Copy two entries from the Linux .mailmap file. Boris confirmed the new email address: https://lists.denx.de/pipermail/u-boot/2019-December/393774.html Cc: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-12-13doc: really get rid of Documentation/ directoryRasmus Villemoes
Commit 656d8da9d2 (doc: Remove duplicated documentation directory) got rid of most of Documentation/. But there's still an obviously useless .gitignore left behind. Also, there's a copy of the linux kernel's net/ethernet.txt binding imported from v5.0, while the existing one in doc/ is from 4.0-rc1. So replace the latter by the former, and making Documentation/ finally empty. Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-12-13sysreset_mpc83xx: fix mcp83xx -> mpc83xx typoRasmus Villemoes
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2019-12-13dts: am335x-brsmarc1/xre1: insert phy_id againHannes Schmelzer
commit 3b3e8a37d36e ("arm: dts: am335x: sync cpsw/mdio/phy with latest linux - drop phy_id") did sync with recent linux kernel and replaced therefore the 'phy_id' property with a phy-handle pointing to the mdio. This is OK for linux, but introduces trouble with the already running vxWorks on this target. So this commit here re-inerts the phy_id property beside the phy-handle property to be compatible with both. Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
2019-12-11Merge tag 'rpi-next-2020.01.2' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-raspberrypi - fix DRAM bank detection for unified binary - fix 32bit RPi4 config
2019-12-11Merge tag 'fix-for-2020.01' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-i2c i2c bugfixes for 2020.01 - i2c: i2c_cdns: fix write timeout on fifo boundary fixes timout issue when writting number of bytes is multiple of the FIFO depth.
2019-12-11Merge tag 'u-boot-atmel-fixes-2020.01-a' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-atmel - First set of u-boot-atmel fixes for 2020.01 cycle: This set includes a small fix for gpio bank names, one for removing unused headers (also touches some other boards), and a fix for the QSPI env read on one of the boards.
2019-12-11ARM: defconfig: Fix 32bit config for RPi4Matthias Brugger
The rpi_4_32b_defconfig states that only one DRAM bank is present. This leads to a wrong configuration of the available DRAM. Fix this by setting the DRAM bank config accordingly. Fixes: 193279d784 ("RPI: Add defconfigs for rpi4 (32/64)") Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2019-12-11rpi: Enable DRAM bank initialization on arm64Matthias Brugger
Up to now we only update the DRAM banks when we are define CONFIG_BCM2711. But our one binary approach uses a config that supports BCM2837 and BCM2711. As a result we only see one gibibyte of RAM on Raspberry Pi 4, even if it has more RAM. Fix this by calling dram_init_banksize. Fixes: 5694090670 ("ARM: defconfig: add unified config for RPi3 and RPi4") Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2019-12-11rpi: fix dram bank initializationMatthias Brugger
To update the dram bank information from device-tree we use fdtdec_decode_ram_size() which expectes the the size-cells and address-cells to be defined in the memory node. For normal system RAM these values are defined in the root node. When the values differ from the default values defined in the spec, we can end up with wrong RAM bank information. Switch to the "standard" way to update the RAM bank information to avoid this. Fixes: 9de5b89e4c ("rpi4: enable dram bank initialization") Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2019-12-11i2c: i2c_cdns: fix write timeout on fifo boundaryMichael Auchter
This fixes an issue that would cause I2C writes to timeout when the number of bytes is a multiple of the FIFO depth (i.e. 16 bytes). Within the transfer loop, after writing the data register with a new byte to transfer, if the transfer size equals the FIFO depth, the loop pauses until the INTERRUPT_COMP bit asserts to indicate data has been sent. This same check is performed after the loop as well to ensure data has been transferred prior to returning. In the case where the amount of data to be written is a multiple of the FIFO depth, the transfer loop would wait for the INTERRUPT_COMP bit to assert after writing the final byte, and then wait for this bit to assert once more. However, since the transfer has finished at this point, no new data has been written to the data register, and hence INTERRUPT_COMP will never assert. Fix this by only waiting for INTERRUPT_COMP in the transfer loop if there's still data to be written. Signed-off-by: Michael Auchter <michael.auchter@ni.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-12-10Merge tag 'fixes-for-2020.01' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-video - fix crash and board reset when drawing RLE8 bitmaps bigger than the framebuffer resolution - reduce dead code in video and console uclass routines (tested on mx53cx9020, sama5d2_xplained, stm32mp157c-ev1, stm32f746-disco, stm32f769-disco and wandboard)
2019-12-10configs: sama5d27_som1_ek: Add default config to read ENV from QSPISwapna Gurumani
In the initial SPI flash setup, the default bus mode being used was 3, which is incorrect, causing a CRC error when the ENV was being read from QSPI. Setting the default bus mode to 0 which is the correct mode. Signed-off-by: Swapna Gurumani <swapna.gurumani@microchip.com>
2019-12-09Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-riscvTom Rini
- Increase stack size to avoid a stack overflow during distro boot. - Add hifive-unleashed-a00.dts for SIFIVE FU540. - Add OF_SEPARATE support for SIFIVE FU540. - Add SPL support for Andes AX25 AE350. - Improve U-Boot SPL / OpenSBI smp boot flow for RISC-V.
2019-12-10spl: opensbi: wait for ack from secondary harts before entering OpenSBILukas Auer
At the start, OpenSBI relocates itself to its link address. If the link address ranges of U-Boot SPL and OpenSBI overlap, the relocation can lead to code corruption if a hart is still running U-Boot SPL during relocation. To avoid this problem, the main hart is specified as the preferred boot hart to perform the relocation. This fixes the code corruption problems based on the assumption that since the main hart schedules the secondary harts to enter OpenSBI, it will be the last to enter OpenSBI. However it was reported that this assumption is not always correct. To make sure the assumption always holds true, wait for all secondary harts to acknowledge the call-function request before entering OpenSBI on the main hart. Reported-by: Rick Chen <rick@andestech.com> Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Rick Chen <rick@andestech.com> Tested-by: Rick Chen <rick@andestech.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>
generated by cgit (git 2.34.1) at 2024-12-28 05:12:40 +0000