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2015-01-13x86: ivybridge: Request MTRRs for DRAM regionsSimon Glass
We should use MTRRs to speed up execution. Add a list of MTRR requests which will dealt with when we relocate and run from RAM. We set RAM as cacheable (with write-back) and registers as non-cacheable. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-13x86: board_f: Adjust x86 boot order for performanceSimon Glass
For bare platforms we turn off ROM-caching before calling board_init_f_r() It is then very slow to copy U-Boot from ROM to RAM. So adjust the order so that the copying happens before we turn off ROM-caching. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-13x86: ivybridge: Set up an MTRR for the video frame bufferSimon Glass
Set the frame buffer to write-combining. This makes it faster, although for scrolling write-through is even faster for U-Boot. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-13x86: Add support for MTRRsSimon Glass
Memory Type Range Registers are used to tell the CPU whether memory is cacheable and if so the cache write mode to use. Clean up the existing header file to follow style, and remove the unneeded code. These can speed up booting so should be supported. Add these to global_data so they can be requested while booting. We will apply the changes during relocation (in a later commit). Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-13x86: ivybridge: Drop support for ROM cachingSimon Glass
This is set up along with CAR (Cache-as-RAM) anyway. When we relocate we don't really need ROM caching (we read the VGA BIOS from ROM but that is about it) Drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-13x86: pci: Display vesa modes in hexSimon Glass
The hex value is more commonly understood, so use that instead of decimal. Add a 0x prefix to avoid confusion. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-01-13x86: Tidy up VESA mode numbersSimon Glass
There are some bits which should be ignored when displaying the mode number. Make sure that they are not included in the mode that is displayed. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-13x86: Use cache, don't clear the display in video BIOSSimon Glass
There is no need to run with the cache disabled, and there is no point in clearing the display frame buffer since U-Boot does it later. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-13x86: ivybridge: Only run the Video BIOS when video is enabledSimon Glass
This takes about about 700ms on link when running natively and 900ms when running using the emulator. It is a waste of time if video is not enabled, so don't bother running the video BIOS in that case. We could add a command to run the video BIOS later when needed, but this is not considered at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-01-13x86: video: Add debug option to time the BIOS copySimon Glass
This can be very slow - typically 80ms even on a fast machine since it uses the SPI flash to read the data. Add an option to display the time taken. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-01-13x86: pci: Don't return a vesa mode when there is not videoSimon Glass
If the video has not been set up, we should not return a success code. This can be detected by seeing if any of the variables are non-zero. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-13x86: video: Add a debug() to display the frame buffer addressSimon Glass
Provide a way to display this address when booting. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-13x86: Correct ifdtool microcode calculationSimon Glass
This currently assumes that U-Boot resides at the start of ROM. Update it to remove this assumption. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2015-01-13x86: Drop RAMTOP KconfigSimon Glass
We don't need this in U-Boot since we calculate it based on available memory. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-01-13x86: Correct XIP_ROM_SIZESimon Glass
This should default to the size of the ROM for faster execution before relocation. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-13x86: crownbay: Add pci devices in the dts fileBin Meng
The Topcliff PCH has 4 UART devices integrated (Device 10, Funciton 1/2/3/4). Add the corresponding device nodes in the crownbay.dts per Open Firmware PCI bus bindings. Also a comment block is added for the 'stdout-path' property in the chosen node, mentioning that by default the legacy superio serial port (io addr 0x3f8) is still used on Crown Bay as the console port. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-01-13x86: Use ePAPR defined properties for x86-uartBin Meng
Use ePAPR defined properties for x86-uart: clock-frequency and current-speed. Assign the value of clock-frequency in device tree to plat->clock of x86-uart instead of using hardcoded number. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-01-13serial: ns16550: Support ns16550 compatible pci uart devicesBin Meng
There are many pci uart devices which are ns16550 compatible. We can describe them in the board dts file and use it as the U-Boot serial console as specified in the chosen node 'stdout-path' property. Those pci uart devices can have their register be memory-mapped, or i/o-mapped. The driver will try to use the memory-mapped register if the reg property in the node has an entry to describe the memory-mapped register, otherwise i/o-mapped register will be used. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-01-13fdt: Add several apis to decode pci device nodeBin Meng
This commit adds several APIs to decode PCI device node according to the Open Firmware PCI bus bindings, including: - fdtdec_get_pci_addr() for encoded pci address - fdtdec_get_pci_vendev() for vendor id and device id - fdtdec_get_pci_bdf() for pci device bdf triplet - fdtdec_get_pci_bar32() for pci device register bar Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> (Include <pci.h> in fdtdec.h and adjust tegra to fix build error)
2015-01-13PM9G45 adding generic board supportGeorgi Botev
Signed-off-by: Georgi Botev <botev@ronetix.at>
2015-01-13PM9261 adding generic board supportGeorgi Botev
Signed-off-by: Georgi Botev <botev@ronetix.at>
2015-01-13PM9263 adding generic board supportGeorgi Botev
Signed-off-by: Georgi Botev <botev@ronetix.at>
2015-01-13ppc4xx: switch VOM405 to generic boardMatthias Fuchs
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
2015-01-13ppc4xx: switch PMC405DE to generic boardMatthias Fuchs
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
2015-01-13ppc4xx: switch PLU405 to generic boardMatthias Fuchs
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
2015-01-13ppc4xx: switch CPCI2DP to generic boardMatthias Fuchs
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
2015-01-13ppc4xx: cleanup CPCI4052 boardMatthias Fuchs
- remove some obsolete code - switch to generic board Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
2015-01-13ppc4xx: remove some CPCI405 variantsMatthias Fuchs
only keep CPCI4052 Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
2015-01-13ppc4xx: remove G2000 boardMatthias Fuchs
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
2015-01-13ppc4xx: remove WUH405 boardMatthias Fuchs
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
2015-01-13ppc4xx: remove VOH405 boardMatthias Fuchs
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
2015-01-13ppc4xx: remove PMC405 boardMatthias Fuchs
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
2015-01-13ppc4xx: remove PCI405 boardMatthias Fuchs
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
2015-01-13ppc4xx: remove OCRTC boardMatthias Fuchs
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
2015-01-13ppc4xx: remove HUB405 boardMatthias Fuchs
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
2015-01-13ppc4xx: remove HH405 boardMatthias Fuchs
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
2015-01-13ppc4xx: remove DU440 boardMatthias Fuchs
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
2015-01-13ppc4xx: remove DU405 boardMatthias Fuchs
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
2015-01-13ppc4xx: remove DP405 boardMatthias Fuchs
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
2015-01-13ppc4xx: remove CPCIISER4 boardMatthias Fuchs
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
2015-01-13ppc4xx: remove CMS700 boardMatthias Fuchs
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
2015-01-13ppc4xx: remove ASH405 boardMatthias Fuchs
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
2015-01-13ppc4xx: remove AR405 boardMatthias Fuchs
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
2015-01-13ppx4xx: remove APC405 boardMatthias Fuchs
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
2015-01-13m68k: remove TASREG boardMatthias Fuchs
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu> Acked-by: Stefan Roese <sr@denx.de>
2015-01-12x86: Simplify the fsp hob access functionsBin Meng
Remove the troublesome union hob_pointers so that some annoying casts are no longer needed in those hob access routines. This also improves the readability. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-01-12pci: Make pci apis usable before relocationBin Meng
Introduce a gd->hose to save the pci hose in the early phase so that apis in drivers/pci/pci.c can be used before relocation. Architecture codes need assign a valid gd->hose in the early phase. Some variables are declared as static so change them to be either stack variable or global data member so that they can be used before relocation, except the 'indent' used by CONFIG_PCI_SCAN_SHOW which just affects some print format. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-01-12x86: Support pci bus scan in the early phaseBin Meng
On x86, some peripherals on pci buses need to be accessed in the early phase (eg: pci uart) with a valid pci memory/io address, thus scan the pci bus and do the corresponding resource allocation. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-01-12x86: Add missing DECLARE_GLOBAL_DATA_PTR for pci.cBin Meng
arch/x86/cpu/pci.c has access to the U-Boot global data thus DECLARE_GLOBAL_DATA_PTR is needed. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-01-12x86: Clean up the board dts filesBin Meng
This commits cleans up the board dts files. - Correct the serial port register size to 8 - Remove the misleading status = "disabled" statement in the serial.dtsi - Move the inclusion of skeleton.dtsi from serial.dtsi to board dts files - Let the board dts file define stdout-path in the chosen node - Remove device nodes in board dts files thar are duplicated to skeleton.dtsi Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
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