summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2016-11-15ARM64: zynqmp: DT: Remove unused DDR PM domainFilip Drazic
DDR power states are handled by the PM firmware, so this domain is redundant. Also, since there is no device using this PM domain, it will be powered off during boot, which is wrong. Signed-off-by: Filip Drazic <filip.drazic@aggios.com> Acked-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-11-15ARM64: zynqmp: Remove note about level shifter on zcu102Michal Simek
i2c device is just level shifter. Remove reference from dts. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-11-15ARM64: zynqmp: Add dcc port to dtsiMichal Simek
Add dcc to dtsi for supporting system without serial port. DCC is enabled by default on ZynqMP. Adding dcc to zcu100 and zcu102 which were tested. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-11-15ARM64: zynqmp: Add gpio-keys for zcu102Michal Simek
There is gpio push button on MIO22. Add it to DTS to have full board description. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-11-15ARM64: zynqmp: Enable gpio-led as heartbeat on zcu102Michal Simek
Show user that Linux is alive on the board. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-11-15ARM64: zynqmp: Enable can1 for ep108Naga Sureshkumar Relli
This patch enables can1 for ep108. Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com> Reviewed-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-11-15ARM64: zynqmp: Added clocks to DT for ep108VNSL Durga
Added clks for ep108 platform. Signed-off-by: VNSL Durga <vnsldurg@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-11-15ARM64: zynqmp: Add clocks for LPDDMAKedareswara rao Appana
Zynqmp DMA driver expects two clocks (main clock and apb clock) LPDDMA clock cofiguration is missing for the same in the zynqmp-clk.dtsi file. This patch updates for the same. Reported-by: Sai Pavan Boddu <saipava@xilinx.com> Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-11-15ARM64: zynqmp: Remove DTC 1.4.2 warningsMichal Simek
DTC 1.4.2 reports these warnings: Warning (unit_address_vs_reg): Node /amba_apu has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /amba has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /amba/usb@fe200000 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /amba/usb@fe300000 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /amba/dma@fd4c0000/dma-video0channel@fd4c0000 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /amba/dma@fd4c0000/dma-video1channel@fd4c0000 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /amba/dma@fd4c0000/dma-video2channel@fd4c0000 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /amba/dma@fd4c0000/dma-graphicschannel@fd4c0000 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /amba/dma@fd4c0000/dma-audio0channel@fd4c0000 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /amba/dma@fd4c0000/dma-audio1channel@fd4c0000 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /memory has a reg or ranges property, but no unit name This patch is fixing them. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-11-15ARM: zynq: Remove DTC 1.4.2 warningsMichal Simek
DTC 1.4.2 reports these warnings: Warning (unit_address_vs_reg): Node /memory has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /pmu has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /fixedregulator@0 has a unit name, but no reg property This patch is fixing them. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-11-15ARM64: zynqmp: Correct the sdhci minimum frequency for ep108Siva Durga Prasad Paladugu
Correct the sdhci minimum frequency for ep platform. It should be right shift instead of left shift operand. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-11-15ARM64: zynqmp: Ignore warnings from autogenerated filesMichal Simek
Autogenerated files contain casting issues and missing function declaration and even usleep implementation. Suppress them for now till these files are fixed. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-11-15ARM64: zynqmp: Fix secondary bootmode enablingMichal Simek
Do not setup use_alt bit which copy alternative boot mode to boot mode. The reason is that this bit is cleared after POR but not after any software reset which will cause that after SW reset bootrom will look for different boot image. This patch setups alternative boot mode selection (purely SW handling) and extends code to read this alternative boot mode first and use it if it is setup. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-11-15ARM64: zynqmp: Add support for SD1 with level shifters bootmodeSiva Durga Prasad Paladugu
Add support for SD1 with level shifters bootmode. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-11-15ARM64: zynqmp: Record board name as serial number for DFU/FASTBOOTMichal Simek
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-11-15ARM64: zynqmp: Adjust to new SMC interface to get silicon versionSoren Brinkmann
The new FW interface returns the IDCODE and version register, leaving extracting bitfields to the caller. Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-11-15ARM: zynq: Add support for Zynq 7000S 7007s/7012s/7014s devicesMichal Simek
Zynq 7000S (Single A9 core) devices is using different ID code. This patch adds this new codes and assign them. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-11-15net: zynq_gem: Correct SGMII enable bit settingSiva Durga Prasad Paladugu
Correct the SGMII enable bit position to 27 instead of 31. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-11-15net: zynq_gem: Modify the nwcfg bit definitionsSiva Durga Prasad Paladugu
Modify the nwcfg bit definitions to have 32-bit by removing the extra nibble. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-11-15nand: arasan_nfc: Clear ecc on bit while sending read commandSiva Durga Prasad Paladugu
Clear ecc ON bit while sending read command as all types of read command(like reading spare) doesnt need ECC to be enabled. It has been anyway taken care in other places whereever required using arasan_nand_enable_ecc(). Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-11-15zynq: nand: Runtime detection of nand buswidth through slcrMichal Simek
This patch adds support to check the buswidth on nand flash at runtime based on nand MIO configurations done by FSBL. User needs to correctly configure the MIO's based on the buswidth supported by the nand flash which is present on the board. Added nand8 and nand16 @periph names on slcr driver. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-11-15zynq: nand: Enable Nand flash controller driver a zynq boardSiva Durga Prasad Paladugu
Enable zynq Nand flash controller driver for a zynq ZC770 XM011(dc2) board. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-11-15mtd: nand: zynq_nand: Add nand driver support for zynqSiva Durga Prasad Paladugu
Add nand flash controller driver support for zynq SoC. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-11-15ARM: zynq: Add support for the topic-miami system-on-modules and carrier boardsMike Looijmans
The topic-miami SoMs contain a Zynq xc7z015 or xc7z030 SoC, 1GB DDR3L RAM, 32MB QSPI NOR flash and 256MB NAND flash. The topic-miamiplus SoMs contain a Zynq xc7z035, xc7z045 or xc7z100 SoC, 2x 1GB DDR3L RAM, 64MB dual-parallel QSPI flash, clock sources and a fan controller. The "Florida" carrier boards add SD, USB, ethernet and other interfaces. Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-11-15ARM: zynq: Make SYS_VENDOR configurableMike Looijmans
Add a string description for SYS_VENDOR to allow configuring boards from other vendors than just "xilinx". Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-11-15tools: mkimage: Check if file is regular fileMichal Simek
Current Makefile.spl passes -R parameter which is not empty and pointing to ./ folder. "./tools/mkimage -T zynqmpimage -R ./"" -d spl/u-boot-spl.bin spl/boot.bin" That's why mkimage is trying to parse ./ file and generate register init which is wrong. Check that passed filename is regular file. If not do not work with it. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-11-15tools: mkimage: Add support for initialization table for Zynq and ZynqMPMike Looijmans
The Zynq/ZynqMP boot.bin file contains a region for register initialization data. Filling in proper values in this table can reduce boot time (e.g. about 50ms faster on QSPI boot) and also reduce the size of the SPL binary. The table is a simple text file with register+data on each line. Other lines are simply skipped. The file can be passed to mkimage using the "-R" parameter. It is recommended to add reg init file to board folder. For example: CONFIG_BOOT_INIT_FILE="board/xilinx/zynqmp/xilinx_zynqmp_zcu102/reg.int Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-11-14Prepare v2016.11Tom Rini
Signed-off-by: Tom Rini <trini@konsulko.com>
2016-11-14MAINTAINERS: mark sunxi status as OrphanHans de Goede
Ian has not had any time for sunxi for some time now and I'm in the same situation now, so I'm stepping down as sunxi custodian and marking the sunxi support as Orphan. Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: Chen-Yu Tsai <wens@csie.org> Cc: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
2016-11-13video: bmp: Fix compilation errors with CONFIG_BMP_xxBPP enabledStefan Roese
Compiling the 'bmp' command with DM and having one of the following macros enabled: CONFIG_BMP_16BPP, CONFIG_BMP_24BPP ONFIG_BMP_32BPP generates this error: drivers/video/video_bmp.c: In function ‘video_bmp_display’: drivers/video/video_bmp.c:315:22: error: ‘lcd_line_length’ undeclared (first use in this function) fb -= width * 2 + lcd_line_length; ^ This patch moves to using the correct variable instead and enables the 'bmp' command for DM again. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Anatolij Gustschin <agust@denx.de>
2016-11-13net: write enetaddr down to hardware on env_callbackMarek Vasut
If mac-address is changed using "setenv ethaddr ...." command the new mac-adress also must be written into the responsible ethernet driver. This fixes the legacy ethernet handling. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Hannes Schmelzer <oe5hpm@oevsv.at> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Hannes Schmelzer <oe5hpm@oevsv.at>
2016-11-13spi: ti_qspi: Fix baudrate divider calculationVignesh R
Fix the divider calculation logic to choose a value so that the resulting baudrate is either equal to or closest possible baudrate less than the requested value. While at that, cleanup ti_spi_set_speed(). Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2016-11-13ARM: dts: dra7xx: Update spi-max-frequency for qspi slave nodeVignesh R
Update the spi-max-frequency property of m25p80 flash slave to match that of TI QSPI controller node, so that QSPI operations happen at maximum supported frequency of 76.8MHz. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
2016-11-13ARM: k2g: Update PLL Multiplier and divider valuesLokesh Vutla
Only a certain set of PLLM/D values are recommended to configure the DDR at the required speeds for a given clock input frequency. Updating these values as specified in Data Sheet[1] Table 5-18 [1] http://www.ti.com/lit/ds/symlink/66ak2g02.pdf Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-11-13ARM: keystone2: PLL: Enable glitch free initialization sequenceLokesh Vutla
Update the PLL initialization sequence to avoid glitches while programming. User guide for the same is available at[1]. [1] http://www.ti.com/lit/ug/sprugv2h/sprugv2h.pdf Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-11-13arm: Set TTB XN bit in case DCACHE_OFF for LPAE modeKeerthy
While we setup the mmu initially we mark set_section_dcache with DCACHE_OFF flag. In case of non-LPAE mode the DCACHE_OFF macro is rightly defined with TTB_SECT_XN_MASK set so as to mark all the 4GB XN. In case of LPAE mode XN(Execute-never) bit is not set with DCACHE_OFF. Hence XN bit is not set by default for DCACHE_OFF which keeps all the regions execute okay and this leads to random speculative fetches in random memory regions which was eventually caught by kernel omap-l3-noc driver. Fix this to mark the regions as XN by default. Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-11-13arm: print the cache config option in hex instead of decimalKeerthy
Printing the option value in hex makes it more comprehensible. Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-11-13mx6ull_14x14_evk: Add README fileDiego Dorta
Add a README file to help users getting started with the board. Signed-off-by: Diego Dorta <diego.dorta@nxp.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2016-11-13davinci: omapl138_lcdk: keep booting even when MAC address is invalidFabien Parent
If the MAC address specified on the EEPROM is invalid (multicast or zero address), then u-boot fails to boot. Having a bad MAC address in the EEPROM should not prevent the system from booting. This commit changes the error path to just print an error messages in case of bad MAC address. Signed-off-by: Fabien Parent <fparent@baylibre.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-11-13board: am335x/mux: Do not hang when encountering a bad EEPROMAlex G
In most cases, the SPL and u-boot.img will be on the same boot media. Since the SPL was loaded by the boot rom, the pinmux will already have been configured for this media. This, the board will still be able to boot successfully, or at least reach the u-boot console, where more recovery options are available. I've encountered this on a beaglebone black with a corrupted EEPROM. Removing this check allowed the board to boot successfully. I've also seen this on EVM-based boards with an unprogrammed EEPROM. On those boards, for some reason there were no UART messages. This made it look as if the SOC was dead. Remove the hang(), as it is not a fatal error. Also reformat the error message to be clearer as to the cause. The original message made it appear as if the wrong binary was being loaded. Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2016-11-13igep00x0: add Hynix timingsLadislav Michl
Tested on IGEPv2 with Micron MT29F4G16ABBDA3W and Hynix H27S4G6F2DKA-BM Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Reviewed-by: Javier Martinez Canillas <javier@samsung.com> Tested-by: Javier Martinez Canillas <javier@samsung.com>
2016-11-13igep00x0: consolidate defconfigsLadislav Michl
Defconfigs should remain the same except CONFIG_SYS_EXTRA_OPTIONS. Drop NAND specific defconfig as flash type is runtime detected. Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Reviewed-by: Javier Martinez Canillas <javier@samsung.com>
2016-11-13igep00x0: disable CONFIG_DISPLAY_BOARDINFOLadislav Michl
As a single U-Boot binary can now run on various board modifications, drop CONFIG_DISPLAY_BOARDINFO as it prints flash memory information too early to give us chance to easily detect it. Also saves few bytes as a bonus. Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Reviewed-by: Javier Martinez Canillas <javier@samsung.com> Tested-by: Javier Martinez Canillas <javier@samsung.com>
2016-11-13tools: fix mksunxiboot build for tools-all targetAndre Przywara
Commit fed329aebe3a ("tools: add mksunxiboot to tools-all target") added mksunxiboot to the tools-all target, but used the CONFIG_SUNXI symbol to enable its build. Now commit aec9a0f19f64 ("sunxi: Rename CONFIG_SUNXI to CONFIG_ARCH_SUNXI"), merged before that, renamed that symbol, so that the first patch basically gets ineffective. Adjust the symbol name in tools/Makefile to make it build again. Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2016-11-08Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini
2016-11-07ARM: tegra186: call secure monitor for all cache-wide opsStephen Warren
An SMC call is required for all cache-wide operations on Tegra186. This patch implements the two missing hooks now that U-Boot supports them, and fixes the mapping of "hook name" to SMC call code. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-11-07armv8: add hooks for all cache-wide operationsStephen Warren
SoC-specific logic may be required for all forms of cache-wide operations; invalidate and flush of both dcache and icache (note that only 3 of the 4 possible combinations make sense, since the icache never contains dirty lines). This patch adds an optional hook for all implemented cache-wide operations, and renames the one existing hook to better represent exactly which operation it is implementing. A dummy no-op implementation of each hook is provided. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-11-07ARM: tegra: translate __asm_flush_l3_cache to assemblyStephen Warren
When performing a cache disable function, code must not access DRAM. That is because when the cache is disabled, it will be bypassed and all loads and stores will be serviced by RAM. This prevents accessing any dirty data in the cache. In turn, this means the stack cannot be used, since that is in RAM. To guarantee that code doesn't use RAM (and in particular the stack) __asm_flush_l3_cache() must be manually implemented in assembly, rather than implemented in C since the compiler won't know not to touch RAM. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-11-07ARM: tegra: ensure nvtboot_boot_x0 alignmentStephen Warren
nvtboot_boot_x0 is a 64-bit variable and hence must be 64-bit aligned. So far this has happened by accident! Fix the code so this is guaranteed. This fixes the following build error: ... relocation truncated to fit: R_AARCH64_LDST64_ABS_LO12_NC against symbol `nvtboot_boot_x0' ... Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-11-07Merge branch 'master' of git://git.denx.de/u-boot-netTom Rini
generated by cgit (git 2.34.1) at 2024-12-28 21:11:43 +0000