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2019-07-19ram: rk3399: debug: Add sdram_print_strideJagan Teki
Add code to print the channel stride, this would help to print the stride of associated channel. Here is sample print on LPDDR4, 50MHz. 256B stride Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19ram: rockchip: debug: Get the cs capacityJagan Teki
Add code to get the channel capacity, this would help to print the capacity of specific channel. Here is sample print on LPDDR4, 50MHz channel 0 BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19ram: rockchip: debug: Add sdram_print_ddr_infoJagan Teki
Add sdram ddr info print support, this would help to observe the sdram base parameters. Here is sample print on LPDDR4, 50MHz channel 0 BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19ram: rockchip: Add debug sdram driverJagan Teki
Add sdram driver to handle debug across rockchip SoCs. This would help to improve code debugging feature for sdram drivers in rockchip family, whoever wants to debug the driver should call these core debug code on their respective platform sdram drivers. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19debug_uart: Add printdecJagan Teki
Add printdec, this would help to print an output a decimalism value. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19ram: rockchip: Add initial KconfigJagan Teki
Right now sdram drivers in rockchip SoC are built based on the SoC configs which may not be an adequate solutions while adding common or debug driver. So, add meaningful Kconfig options start with rk3399. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19ram: rk3399: Add pctl start supportJagan Teki
Add support for pctl start for both channel 0, 1 control and phy registers. This would also handle pwrup_srefresh_exit init based on the channel number. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19ram: rk3399: Move pwrup_srefresh_exit to dram_infoJagan Teki
Add pwrup_srefresh_exit to be part of dram_info so-that the it can help to support pwrup_srefresh_exit in individual channels while starting pctl in future. No functionality change. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19ram: rk3399: Add phy pctrl reset supportJagan Teki
Add support for phy pctrl reset support for both channel 0, 1. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19ram: rk3399: Use rank mask in wdql data trainingJagan Teki
Add rank_mask based on the rank number, this would keep the wdql data training loop based on the desired rank mask value instead of looping for all values. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19ram: rk3399: Use rank mask in ca data trainingJagan Teki
Add rank_mask based on the rank number, this would keep the ca data training loop based on the desired rank mask value instead of looping for all values. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19ram: rk3399: Clear PI_175 interrupts in data trainingJagan Teki
Clear the PI_175 interrupts before processing actual data training in all relevant calls. This would help to clear interrupt from previous training. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19ram: rk3399: Handle data training return typesJagan Teki
data trainings calls like ca, wl, rg, rl, wdql have proper return types with -EIO and the return type missed to handle in data_training function. This patch, add proper return type checks along with useful debug statement on each data training calls. Incidentally this would help to prevent the sdram initialization hang for single channel dram and when the code is trying to initialize second channel with proper return type of relevant data training call might failed. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19clk: rockchip: rk3399: Fix check patch warnings and checksJagan Teki
- CHECK: spaces preferred around that '*' - CHECK: spaces preferred around that '/' - CHECK: space preferred before that '|' - WARNING: macros should not use a trailing semicolon - CHECK: Unnecessary parentheses around 'fbdiv <= min_fbdiv' - CHECK: Unnecessary parentheses around 'parent->id == SCLK_MAC' - CHECK: Unnecessary parentheses around 'parent->dev == clk->dev' - WARNING: line over 80 characters - CHECK: Prefer kernel type 'u8' over 'uint8_t' - Add proper macro definitions arrangements Note: there are still line over 80 characters and other warnings but fixing those making code look unreadable, so I kept it as it is. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19arm: include: rockchip: Add DDR4 enumJagan Teki
Add DDR4 enum number in common header. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19arm: include: rockchip: Move dramtypes to common headerJagan Teki
dramtype enum numbers as common across all dram controllers in rockchip, so move the eneum values in common header. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19ram: rk3399: Move common sdram structures in common headerJagan Teki
Move common sdram structures like sdram_cap_info, sdram_base_params into sdram_common header, this would help to reuse the same from another controllers like px30. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19ram: rk3399: s/rk3399_base_params/sdram_base_paramsJagan Teki
Most of the ddr parameters are common in rk3399_base_params structure and which would reuse it in another controller like px30 in future. So, rename the structure from rk3399_base_params into sdram_base_params. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19ram: rockchip: rk3399: Add cap_info structureJagan Teki
Group common ddr attributes like - rank - col - bk - bw - dbw - row_3_4 - cs0_row - cs1_row - ddrconfig into a common cap_info structure for more code readability and extend if possible based on the new features. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19ram: rk3399: Order tsel variablesJagan Teki
Order tsel* variable declarations and assignment in proper and meaningful way. No functionality change. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19ram: rk3399: s/ca_tsel_wr_select_p/tsel_wr_select_ca_pJagan Teki
Rename ca_tsel_wr_select_p to tsel_wr_select_ca_p based on the bsp code. No functionality change. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19ram: rk3399: s/ca_tsel_wr_select_n/tsel_wr_select_ca_nJagan Teki
Rename ca_tsel_wr_select_n to tsel_wr_select_ca_n based on the bsp code. No functionality change. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19ram: rk3399: s/tsel_wr_select_p/tsel_wr_select_dq_pJagan Teki
Rename tsel_wr_select_p to tsel_wr_select_dq_p based on the bsp code. No functionality change. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19ram: rk3399: s/tsel_wr_select_n/tsel_wr_select_dq_nJagan Teki
Rename tsel_wr_select_n to tsel_wr_select_dq_n based on the bsp code. No functionality change. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19ram: rk3399: Handle pctl_cfg return typeJagan Teki
Add proper return type handling of pctl_cfg with meaningful print statement. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19ram: rk3399: s/sdram_params/paramsJagan Teki
Rename variable name of struct rk3399_sdram_params from sdram_params with params for more code readability. No functionality change. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19ram: rk3399: Some trivial code fixesJagan Teki
- Add proper spaces in data training, rk3399_dmc_init, pctl_cfg - Order include files - Move macro after include files Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19ram: rk3399: Fix code warningsJagan Teki
Fix checkpatch warninigs on sdram_rk3399.c like - Avoid CamelCase - Unnecessary parentheses - Alignment should match open parenthesis - multiple blank lines - misspelled - spaces preferred around that '>>' Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19rockchip: rock960-rk3399: fix mail format in MAINTAINER fileKever Yang
The mail format should have '<>', or else the patman won't recognize it correctley. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-19rockchip: dts: rk3399: Add 'same-as-spl' for Rock PI 4Andy Yan
Let the board continue boot from the storage device where it bootup. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
2019-07-19rockchip: dts: rk3399: Add spl-boot-order for Rock PI 4Andy Yan
RK3399 use sdhci for eMMC and DW MMC for SD Card, and spl will only try to boot from SDMMC if we don't specify other boot device for spl-boot-order. So add sdhci and sdmmc for spl-boot-order here. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-19configs: rockchip: rock960: enable USB3 supportPeter Robinson
Enable USB3 support via the dwc3 XHCI driver. Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2019-07-19configs: rockchip: rock960: Add support for USB ethernet adaptersPeter Robinson
As the Rock960 doesn't have an onboard wired ethernet interface it's useful to have some common USB wired ethernet devices added to enable testing. Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2019-07-19configs: rockchip: rock960: enable DMA for SDHCI controllerPeter Robinson
Enable the SDMA controller so the eMMC connected to the SDHCI controller (sdhci@fe330000) can make use of it. Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2019-07-19configs: rockchip: rock960: enable pmic and regulator commandsPeter Robinson
We have both PMIC and Regulator functionality so it's useful to be able to see output and debug with the commands enabled. Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2019-07-19configs: rockchip: rock960: drop options for non-existent HWPeter Robinson
The Rock960 doesn't contain SPI flash so drop related config options. Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2019-07-19arm64: rockchip: rock960: sync dts files from Linux 5.2-rc6Peter Robinson
Sync the dts files for the Rock960 boards from Linux to get the latest changes and fixes for the devices. Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2019-07-19rockchip: xhci: Remove RK3399 supportMark Kettenis
Remove RK3399 compatible strings as this driver is no longer used on that SoC. Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-19usb: xhci-dwc3: Add USB2 PHY configurationMark Kettenis
Configure USB2 PHY register based on "phy_type" property and handle all the quirks that are relevant for Rockchip RK3399 SoCs. Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-19usb: dwc3-of-simple: Add support for RK3399Mark Kettenis
Add compatible string for RK3399 and enable it by default on Rockchip platforms with USB3 support. Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-19rockchip: clk: rk3399: handle clk_enable requests for USB3Mark Kettenis
The "simple" OF glue layer for the Designware USB3 core enables all refernced clocks. These need to be need to be implemented otherwise the driver fails to probe. A dummy implementation that simply returns success is sufficient since the RK3399 comes out of reset with all clock gates open. Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2019-07-18Merge branch '2019-07-17-master-imports'Tom Rini
- Various FS/disk related fixes with security implications. - Proper fix for the pci_ep test. - Assorted bugfixes - Some MediaTek updates. - 'env erase' support.
2019-07-18Revert "test: Disable pci_ep test for now"Tom Rini
We now have a proper fix for this test, stop disabling it in CI. This reverts commit ae8d23a668755d804748a1cf848426b28338b3d5. Signed-off-by: Tom Rini <trini@konsulko.com>
2019-07-18pci_ep: fix wrong addressing to barnoRamon Fried
barno was mistakely readed from the target structure, resulting in undefined behavious depending on the previous memory content. fix that. Fixes: bb413337826e ("pci_ep: add pci endpoint sandbox driver") Signed-off-by: Ramon Fried <rfried.dev@gmail.com> [trini: Drop unused bar_idx] Signed-off-by: Tom Rini <trini@konsulko.com>
2019-07-18board: Arcturus: ucp1020: Removing obsoleted stuffOleksandr Zhadan
Removed one of the defconfig(obsoleted) file and unused CONFIG_MMC_SPI definition to avoid confusion about if this board using non-DM stuff or not. uCP1020 is completely DM free board, tested and runs well. Signed-off-by: Oleksandr Zhadan <oleks@arcturusnetworks.com> Signed-off-by: Michael Durrant <mdurrant@arcturusnetworks.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-07-18blk: Invalidate block cache when switching hwpartWeijie Gao
Some storage devices have multiple hw partitions and both address from zero, for example eMMC. However currently block cache invalidation only applies to block write/erase. This can cause a problem that data of current hw partition is cached before switching to another hw partition. And the following read operation of the latter hw partition will get wrong data when reading from the addresses that have been cached previously. To solve this problem, invalidate block cache after a successful select_hwpart operation. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-07-18arm: dts: MediaTek: remove tick-timer from mt7629.dtsiWeijie Gao
This patch removes tick-timer as all mt7629 boards should use arch timer. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-07-18configs: mt7629_rfb: use arm arch timer instead of mtk timerWeijie Gao
This patch changes mt7629_rfb to use ARM's generic arch timer instead of MediaTek's soc timer. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-07-18arm: dts: MediaTek: fix clock order for timer0 node of mt7629.dtsiWeijie Gao
The timer0 node has its two clocks written in reversed order. The timer0 is used as the tick timer which causes a problem that the time a delay function used is 4 times longer. This patch reverses these two clocks to solve this issue. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2019-07-18chromium: Update docs to clone vboot_reference directlySimon Glass
We don't need a full checkout of Chrome OS to build U-Boot with Chromium OS verified boot. Update the instructions accordingly and fix a typo which joins the output directory and defconfig. Signed-off-by: Simon Glass <sjg@chromium.org>
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