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2017-07-28configs: Remove CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS in all boardsBin Meng
Now that EHCD does not use CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS, remove it in all boards' config files. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de>
2017-07-28usb: ehci: Get rid of CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTSBin Meng
EHC reports supported maximum number of ports in the HCSPARAMS register, so it's unnecessary to use a hardcoded config option CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de>
2017-07-28configs: Remove CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS in all boardsBin Meng
Now that xHCD does not use CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS, remove it in all boards' config files. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de>
2017-07-28usb: xhci: Get rid of CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTSBin Meng
xHC reports supported maximum number of ports in the HCSPARAMS1 register, so it's unnecessary to use a hardcoded config option CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de>
2017-07-28usb: xhci: Change MAX_HC_PORTS to 255Bin Meng
HCSPARAMS1:MaxPorts field specifies the maximum port number value, and its valid values are in the range of 1 to 255. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de>
2017-07-28usb: hub: Add 3.0 hub port status mask of 2.0 hubBin Meng
USB 3.0 hub port status has different bit position regarding to port power, port speed, etc. But others are the same as 2.0 hubs. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de>
2017-07-28usb: hub: Change USB hub descriptor to match USB 3.0 hubsBin Meng
USB 3.0 hubs have a slightly different hub descriptor than USB 2.0 hubs, with a fixed (rather than variable length) size. Change the host controller drivers that access those last two fields (DeviceRemovable and PortPowerCtrlMask) to use the union. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de>
2017-07-28usb: hub: Revise wLength for 'get port status' requestBin Meng
For accuracy, we should use 'sizeof(struct usb_port_status)' as the wLength for 'get port status' request, although it happens to be equal to 'sizeof(struct usb_hub_status)'. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de>
2017-07-28usb: hub: Send correct wValue to get hub descriptor of a USB 3.0 hubBin Meng
Testing a USB 3.0 hub by connecting it to the xHCI port on Intel MinnowMax, when issuing 'get hub descriptor' to the hub, xHCI reports a transfer event TRB with a completion code 6 which means 'Stall Error'. In fact super speed USB hub descriptor type is 0x2a, not 0x29. Sending correct SETUP packet to the hub makes it not stall anymore. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de>
2017-07-28usb: hub: Update handling connect status/change in usb_scan_port()Bin Meng
It was observed that on Intel MinnowMax board, when xHCI is enabled in the BayTrail SoC, with a USB 3.0 device connected to the bottom USB 3.0 port (mapped to xHCI root port #7), its PORTSC register is always 0x201203 (CCS = 1, CSC = 0). The root cause of such behavior is unknown yet. Connect status change bit is set on the same port with a USB 2.0 device (mapped to xHCI port #1, which is a different port on the root hub). With current logic in usb_scan_port(), the enumeration process will abort if it does not detect a connect status change on a hub port. However since a device connection status is correctly reported, the enumeration process can still continue. With this change, USB device connected to the bottom blue port on MinnowMax board can be enumerated under either SS or HS mode. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Dinh Nguyen <dinguyen@kernel.org>
2017-07-28usb: xhci: Add input slot context in xhci_set_configuration()Bin Meng
A valid input slot context for a 'configure endpoint' command requires the 'Context Entries' field to be initialized to the index of the last valid endpoint context that is defined by the target configuration. We set up the 'Context Entries' field, but we forget to include the input slot context in the input control context 'Add Context flags' bitmap. So xHC will simply ignore input slot context and continue using its own which contains old information of the device. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de>
2017-07-28usb: xhci: Initialize scratchpad buffer array and scratchpad buffersBin Meng
The scratchpad buffer array is used to define the locations of statically allocated memory pages that are available for the private use of the xHC. The xHCI spec explicitly mentions that system software shall allocate the scratchpad buffers before placing the xHC in to Run mode (Run/Stop (R/S) = ‘1’), however U-Boot is missing this part. This causes xHC on Intel platform does not respond the very first 'enable slot' command that is given to xHC and the 'enable slot' command completion event TRB is never generated and xHC seems to hang forever. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de>
2017-07-28usb: xhci: Correct command TRB 4th dword initializationBin Meng
In xhci_queue_command(), when the command is not 'reset endpoint', 'stop endpoint' or 'set TR dequeue pointer', endpoint ID should not be encoded in the TRB. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de>
2017-07-28usb: xhci: Remove incorrect comments for struct xhci_container_ctxBin Meng
There is no member called 'dma' in struct xhci_container_ctx. Remove the comments that mentions it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Stefan Roese <sr@denx.de>
2017-07-28usb: host: ohci-generic: add generic PHY supportPatrice Chotard
Extend ohci-generic driver with generic PHY framework Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28usb: host: ohci-generic: add RESET supportPatrice Chotard
use array to save deasserted resets reference in order to assert them in case of error during probe() or during driver removal. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28usb: host: ohci-generic: add CLOCK supportPatrice Chotard
use array to save enabled clocks reference in order to disabled them in case of error during probe() or during driver removal. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28usb: host: ehci-generic: add generic PHY supportPatrice Chotard
Extend ehci-generic driver with generic PHY framework Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28usb: host: ehci-generic: add error path and .remove callbackPatrice Chotard
Use an array to save enabled clocks reference and deasserted resets in order to respectively disabled and asserted them in case of error during probe() or during driver removal. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28usb: host: ehci-generic: replace printf() by error()Patrice Chotard
this allows to get file, line and function location of the current error message. Signed-off-by: patrice chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28dm: core: add ofnode_count_phandle_with_args()Patrice Chotard
This function is usefull to get phandle number contained in a property list. For example, this allows to allocate the right amount of memory to keep clock's reference contained into the "clocks" property. To implement it, either of_count_phandle_with_args() or fdtdec_parse_phandle_with_args() are used respectively for live tree and flat tree. By passing index = -1, these 2 functions returns the number of phandle contained into the property list. Add also the dev_count_phandle_with_args() based on ofnode_count_phandle_with_args() Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28clk: add clk_release_all()Patrice Chotard
Add clk_release_all() method which Disable/Free an array of clocks that has been previously requested by clk_request/get_by_*() Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28reset: add reset_release_all()Patrice Chotard
Add reset_release_all() method which Assert/Free an array of resets signal that has been previously successfully requested by reset_get_by_*() Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28reset: add reset_request()Patrice Chotard
This is needed in error path to assert previously deasserted reset by using a saved reset_ctl reference. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28usb: host: xhci-dwc3: Add generic PHY supportPatrice Chotard
Add support of generic PHY framework support Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28drivers: phy: add generic_phy_valid() methodPatrice Chotard
This allow to check if a PHY has been correctly initialised and avoid to get access to phy struct. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2017-07-28drivers: phy: Set phy->dev to NULL when generic_phy_get_by_index() failsPatrice Chotard
phy->dev need to be set to NULL in case of generic_phy_get_by_index() fails. Then phy->dev can be used to check if the phy is valid Reported-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28usb: host: xhci-dwc3: Add dual role mode support from DTPatrice Chotard
DWC3 dual role mode is selected using DT "dr_mode" property. If not found, DWC3 controller is configured in HOST mode by default Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-28usb: host: xhci-dwc3: Convert driver to DMPatrice Chotard
Add Driver Model support with use of generic DT compatible string "snps,dwc3" Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-28usb: add static to local symbolsMasahiro Yamada
Sparse reports "... was not declared. Should it be static?" Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-07-27rockchip: puma-rk3399: remove duplicate code (merge artifact)Kever Yang
A few lines (defines and declarations) had been duplicated when the puma-rk3399 board was initially merged. This removes the duplicates and changes the style to use local constants instead of pasted literals. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> [fixed up commit-message & converted to use 'const u32':] Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27rockchip: add u-boot specific dts for rk3036 sdkAndy Yan
Add this dts to enable debug uart releated devices before relocation. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27rockchip: use puts instead of printf when back to bootromAndy Yan
printf will increase the code size more than 1kb, but platform like rk3036 has no enough space for it. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27rockchip: enable SPL_LIBGENERIC for rk3036 based boardsAndy Yan
function board_init_f_init_reserve will call memset, which is implemented in lib, and enabled by CONFIG_SPL_LIBGENERIC_SUPPORT in spl stage. To reduce the code size, also enable SPL_TINY_MEMSET. As rk3036 will return to bootrom immediately after dram initialization, there is no need to run DM, so disable SPL_DM_SERIAL. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27rockchip: disable SPL_ARCH_MEMCPY/MEMSET for rk3036Andy Yan
RK3036 has no enough sapce use ARCH_MEMCPY/MEMSET in spl stage Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27rockchip: set malloc pool size to 0 before relocation in spl state on rk3036 ↵Andy Yan
based board RK3036 only has 4kb sram, the spl code will use 3.4 ~ 3.5 kb, the last 0.5kb are used for SP and GD, so there is no space for malloc. Also, the spl will directly return to bootrom after dram initialized, they never need the space for malloc. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27sandbox: use CONFIG_VAL(SYS_MALLOC_F_LEN) to distinguish malloc pool size ↵Andy Yan
before relocation SPL and normal u-boot stage use different malloc pool size configuration before relocation, so use CONFIG_VAL(SYS_MALLOC_F_LEN) to fit different boot stage. Signed-off-by: Andy Yan <andyshrk@gmail.com> Changes in v3: - use CONFIG_VAL(), which suggested by Simon Changes in v2: None arch/sandbox/cpu/start.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27microblaze: spl: configure SYS_MALLOC_F_LEN independently for SPL and full ↵Andy Yan
U-Boot Some platforms have very limited SRAM to run SPL code, so there may not be the same amount space for a malloc pool before relocation in the SPL stage as the normal U-Boot stage. Make SPL and (the full) U-Boot stage use independent SYS_MALLOC_F_LEN, so the size of pre-relocation malloc pool can be configured memory space independently. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> [fixed up commit-message:] Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27powerpc: spl: configure SYS_MALLOC_F_LEN independently for SPL and full U-BootAndy Yan
Some platforms have very limited SRAM to run SPL code, so there may not be the same amount space for a malloc pool before relocation in the SPL stage as the normal U-Boot stage. Make SPL and (the full) U-Boot stage use independent SYS_MALLOC_F_LEN, so the size of pre-relocation malloc pool can be configured memory space independently. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> [fixed up commit-message:] Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27mips: spl: configure SYS_MALLOC_F_LEN independently for SPL and full U-BootAndy Yan
Some platforms have very limited SRAM to run SPL code, so there may not be the same amount space for a malloc pool before relocation in the SPL stage as the normal U-Boot stage. Make SPL and (the full) U-Boot stage use independent SYS_MALLOC_F_LEN, so the size of pre-relocation malloc pool can be configured memory space independently. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Acked-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> [fixed up commit-message:] Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27spl: make SPL and normal u-boot stage use independent SYS_MALLOC_F_LENAndy Yan
Some platforms have very limited SRAM to run SPL code, so there may not be the same amount space for a malloc pool before relocation in the SPL stage as the normal U-Boot stage. Make SPL and (the full) U-Boot stage use independent SYS_MALLOC_F_LEN, so the size of pre-relocation malloc pool can be configured memory space independently. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> [fixed up commit-message:] Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27rockchip: firefly: Add "usb start" to auto-start USB deviceLeo Wen
Add "preboot=usb start" to ROCKCHIP_DEVICE_SETTINGS,you don't need to input "usb start" in command line of u-boot console,it can auto-start the USB device,after that usb keyboard can work. Signed-off-by: Leo Wen <leo.wen@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27rockchip: firefly: Set the environment variable 'usbkbd' to the stdinLeo Wen
Add the 'usbkbd' environment variable to the 'stdin', the contents of the keyboard input can be auto-displayed on the serial terminal,so you don't need to manually set the environment variable 'stdin'. Signed-off-by: Leo Wen <leo.wen@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27rockchip: firefly: Add some macros to enable the usb keyboardLeo Wen
Add four macros of CONFIG_USB_KEYBOARD,CONFIG_DM_KEYBOARD,etc in the firefly-rk3288_defconfig,can support usb keyboard device when these four macros are enabled. Signed-off-by: Leo Wen <leo.wen@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27rockchip: rk3399: enable SPL_SERIAL_SUPPORT and SPL_DRIVERS_MISC_SUPPORT via ↵Philipp Tomsich
Kconfig SPL_SERIAL_SUPPORT and SPL_DRIVERS_MISC_SUPPORT were previously enabled through rk3399_common.h. This change implies these options through Kconfig. These need to always be active for the RK3399, as follows: - SPL_SERIAL_SUPPORT is needed to pass the SPL build - SPL_DRIVERS_MISC_SUPPORT is needed to pass the SPL build Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27rockchip: rk3288: Add support for drive-strength in PINCTRLRomain Perier
Currently, drive-strenght to 12ma are described and supposed to be used on RK3288. However, the pinctrl driver for this SoC only handles muxing and pull up/pull down via PU/PD control registers. So complex IPs like GMAC are working in normal ethernet 100mbps, but not at 1gbps typically. This commit adds support for handling drive-strength of 12ma, when it's defined in the DT. Signed-off-by: Romain Perier <romain.perier@collabora.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27rockchip: use UUID for root partitionsKever Yang
We use to use /dev/mmcbl0p7 as root partition, and pass it to kernel by cmdline, but the mmc number in kernel in not fixed, we need to change the bootargs to adapt it from time to time. We can use the UUID to fix it, the ID is from: https://www.freedesktop.org/wiki/Specifications/DiscoverablePartitionsSpec/ ARM 32bit: 69dad710-2ce4-4e3c-b16c-21a1d49abed3 ARM 64bit: b921b045-1df0-41c3-af44-4c6f280d3fae Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27rockchip: dts: rk3399-puma: put EFI partition entries at 2MBPhilipp Tomsich
When creating a EFI/GUID partition map for the RK3399-Q7 through U-Boot, the partition entries should be places at a 1MB offset from the start of the device to give us space for the environment (at 16KB on SD/MMC devices), the SPL stage (at 32KB on SD/MMC devices) and the image payload (at 256KB on SD/MMC devices). This change sets this up through the u-boot,efi-partition-entries-offset /config property in the RK3399-Q7 DTSI. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27rockchip: dts: rk3399-puma: put environment (in MMC/SD configurations) ↵Philipp Tomsich
before SPL As our SPL stage can grow quite large (80KB+ are not unusual) on the RK3399-Q7, the default setting for the environment location (in include/configs/rockchip-common.h) can overlap our SPL. This change finally makes use of the 'u-boot,mmc-env-offset' DTS property to override the environment location and put it at 16KB into the device, which is right before the SPL (located at 32KB). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-07-27rockchip: clk: rk3399: remove unused fields from priv-structuresPhilipp Tomsich
This removes the unused 'rate' field from both rk3399_pmuclk_priv and rk3399_clk_priv. I didn't bother to check where this came from (i.e. what the historical context of these was), but only verified that these are indeed unused across all code-paths. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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