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2017-03-29arm64: mvebu: dts: Add DTS file for MACCHIATOBin boardRabeeh Khoury
Added A8040 dts file for community board MACCHIATIBin. The patch includes the following features: AP - Serial console (connected to onboard FTDI usb to serial) CP0 - PCIe x4, SATA, I2C and 10G KR (connected to Marvell 3310 10G copper / SFP+ phy) CP1 - Boot SPI, USB3 host, 2xSATA, 10G KR (connected to Marvell 3310 10G copper / SFP+ phy), SGMII connected to onboard 1512 1Gbps copper phy, and additional SGMII connected to SFP (default 1Gbps can be configured to 2.5Gbps). Network interface naming - egiga0 - CP0 KR egiga1 - CP1 KR egiga2 - CP1 RJ45 1Gbps connector (recommended for TFTP boot) egiga3 - CP1 SFP default 1Gbps and can be modified to 2.5Gbps Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com> Cc: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2017-03-29mvebu: pcie: Add support for GPIO reset for PCIe deviceKonstantin Porotchkin
Add support for "marvell,reset-gpio" property to mvebu DW PCIe driver. This option is valid when CONFIG_DM_GPIO=y Change-Id: Ic17c500449050c2fbb700731f1a9ca8b83298986 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com> Cc: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2017-03-29arm64: mvebu: dts: Add i2c1 pin definitions to CPMKonstantin Porotchkin
Add i2c-1 pin mappings to CP0(master) DTSI file Change-Id: I0c6e6de8a557393f518f7df8e6daa6dfce1788b0 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2017-03-29arm64: mvebu: gpio: Add GPIO nodes to A8K family devicesKonstantin Porotchkin
Add GPIO nodes to AP-806 and CP-110-master DTSI files. Change-Id: I05958698d460cb721b7d8683d34f74a5ea32532c Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2017-03-29dtoc: make ScanTree recurse into subnodesPhilipp Tomsich
Previously, dtoc could only process the top-level nodes which led to device nodes in hierarchical trees to be ignored. E.g. the mmc0 node in the following example would be ignored, as only the soc node was processed: / { soc { mmc0 { /* ... */ }; }; }; This introduces a recursive helper method ScanNode, which is used by ScanTree to recursively parse the entire tree hierarchy. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-03-29drivers: ti_qspi: use syscon to get the address ctrl_mod_mmap registerJean-Jacques Hiblot
We used to get the address of the optionnal ctrl_mod_mmap register as the third memory range of the "reg" property. the linux driver moved to use a syscon instead. In order to keep the DTS as close as possible to that of linux, we move to using a syscon as well. If SYSCON is not supported, the driver reverts to the old way of getting the address from the 3rd memory range Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2017-03-29regmap: use fdt address translationJean-Jacques Hiblot
In the DTS, the addresses are defined relative to the parent bus. We need to translate them to get the address as seen by the CPU core. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2017-03-29dm: core: Fix Handling of global_data moving in SPLLokesh Vutla
commit 2f11cd9121658 ("dm: core: Handle global_data moving in SPL") handles relocation of GD in SPL if spl_init() is called before board_init_r(). So, uclass_root.next need not be initialized always and accessing uclass_root.next->prev gives an abort. Update the uclass_root only if it is available. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2017-03-29mmc: xenon_sdhci: Add missing host->max_clk to Xenon SDHCI driverStefan Roese
The Xenon SDHCI driver just missed the integration of this patch: git ID 6d0e34bf mmc: sdhci: Distinguish between base clock and maximum peripheral frequency With this patch applied, the SDHCI subsystem complains now with this warning while probing: sdhci_setup_cfg: Hardware doesn't specify base clock frequency This patch fixes this issue, by providing the missing host->max_clk variable to the SDHCI subsystem. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Hu Ziji <huziji@marvell.com> Cc: Victor Gu <xigu@marvell.com> Cc: Konstantin Porotchkin <kostap@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Cc: Jaehoon Chung <jh80.chung@samsung.com>
2017-03-29mmc: drop unnecessary send_status requestXu Ziyuan
It's redundant to send cmd13 after cmd9 whose response is not R1b. The card devices will not be busy w/ cmd9. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
2017-03-29mmc: sdhci: only flush cache for data commandKevin Liu
No need to flush cache for command without data. Signed-off-by: Kevin Liu <kevinliu@asrmicro.com>
2017-03-29mmc: tangier: Add Intel Tangier eMMC/SDHCI driverFelipe Balbi
This patch adds Intel Tangier eMMC/SDHCI driver. Intel Tangier SoC contains a hybrid of PCI and non-PCI devices. SDHCI controller is one of the devices which are *not* on a PCI and, hence, cannot be enumerated by standard PCI means. This driver, allows for SDHCI controller on Tangier SoC to work in U-Boot. Signed-off-by: Vincent Tinelli <vincent.tinelli@intel.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-03-29mmc: pci: Add CONFIG_MMC_PCIFelipe Balbi
We don't want pci_mmc to compile every time x86 compiles, only when there's a platform that needs it. For that reason, we're adding a new CONFIG_MMC_PCI which platforms can choose to enable. Suggested-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2017-03-28pcie-layerscape: Fixup iommu-map property of pci nodeBharat Bhushan
This patch fixup iommu-map property on pci node to have a valid mapping of requester-id to stream-id. The requester-id to stream-id mapping is based on PCI-LUT table initialization. Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28pcie-layerscape: Initialize pci-lut for NXP chasis-2 socsBharat Bhushan
Layerscape Chasis-2 also uses same PCIe controller as Chasis-3 and have similar PCI-Lut. Signed-off-by: Bharat Bhushan <bharat.bhushan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28armv8: fsl-lsch2: Use Chassis-2 streamid definition for ls1012aBharat Bhushan
LS1012A is Chassis-2 type SOC and shares same streamid definition. This patch adds using streamids for ls1012a Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28armv8: fsl-lsch2: Use Chassis-2 streamid definition for ls1046aBharat Bhushan
LS1046A is Chassis-2 type SOC and shares same streamid definition, this patch adds using streamids for LS1046A. Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28arvm8: pcie-layerscape: Define stream-ids for Layerscape Chassis-2Bharat Bhushan
Layerscape Chassis-2 have PCIe device, some platform devices and DPAA1 devices which will use stream-ids for iommu level isolation as they are behind SMMU. This patch defines the stream-ids for Chassis-2 devices. DPAA1 is reserved for future use. Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28armv8: fsl-lsch3: Rewrite comment for stream IDsBharat Bhushan
LS2080a, LS1088a and LS2088a SOCs are based on Chassis-3 and shared same stream-id partitioning. This patch rewords the definition to support all these SOCs. Also have changes in description about iommu-map property updates in PCI node. Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28armv8: fsl-lsch3: rename ls2080a_stream_id.h to stream_id_lsch3.hBharat Bhushan
The stream ID allocation for Chasis 3.0 devices can be shared among LS1088, LS2088 and LS2080. Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28fsl-layerscape/ls104xardb: enable PPA support for eMMC/SD and NAND bootHou Zhiqiang
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28armv8: Kconfig: fsl-ppa: support load PPA from eMMC/SD and NAND FlashHou Zhiqiang
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28fsl: PPA: add support PPA image loading from NAND and SDHou Zhiqiang
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28mtd: nand: remove nand size print from nand_init functionHou Zhiqiang
Add nand_size() function to move the nand size print into initr_nand(). Remove nand size print from nand_init() to allow other function to call nand_init() without printing nand size. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28mtd: nand: add initialization flagHou Zhiqiang
Add initialization flag to avoid initializing NAND Flash multiple times, otherwise it will calculate a wrong total size. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28armv8/fsl-layerscape: fdt: Skip checking USB clock on LS1012AYingxi Yu
USB requires 100MHz clock. On LS1012A, a dedicated 100MHz is provided instead of SYSCLK (125MHz). Skipping checking SYSCLK for FDT fixup. Signed-off-by: Yingxi Yu <yingxi.yu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28armv8: ls1043a/ls1046aqds: fix the offsets of MTD partitions on NOR flashWenbin Song
Fix the offsets of MTD partitions on Nor flash on ls1043ardb, ls1043aqds and ls1046aqds boards. Delete the rcw, uboot env and fman partitions. Add user partitions for general usage. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28board: freescale: ls2080a/ls2088a: Enable PPASantan Kumar
Enable PPA on LS2080A, LS2088A boards: -LS2080ARDB, LS2080AQDS -LS2088ARDB, LS2088AQDS Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28pci: layerscape: Fixup device tree node for ls2088aHou Zhiqiang
LS2088A and its variants have different PCIe node than LS2080A. The compatible string is updated accordingly. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28pci: layerscape: add LS2088A series SoC pcie supportHou Zhiqiang
The LS2088A series SoCs has different physical memory map address and CCSR registers address against LS2080A series SoCs. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28tools: plbimage support generate rcw fileyuan linyu
some system will not generate pbl format u-boot, but require rcw. Signed-off-by: yuan linyu <Linyu.Yuan@alcatel-sbell.com.cn> Reviewed-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28armv8: fsl-lsch3: Conditionally apply workaround for erratum a0009203Ashish kumar
This i2c errata only applies to LS2080A and its variants, namely LS2080A, LS2085A and LS2088A. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28armv8: dts: fsl-ls1012a: Change number of CS in SPI nodeSuresh Gupta
LS1012A has only one chip select for QSPI flash. Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28spi: fsl_qspi: Add support for single chip selectSuresh Gupta
SOC’s like LS1012A has only one chip select signal for QSPI flash. Avoid scanning other flash. Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28armv8:fsl-layerscape: Avoid RCWSR28 register hard-codingPrabhakar Kushwaha
SerDes information is not necessary to be present in RCWSR29 register. It may vary from SoC to SoC. So Avoid RCWSR28 register hard-coding. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28arm: fsl-layerscape: Move QSGMII wriop_init to SoC filePrabhakar Kushwaha
MAC number used per QSGMII is not fixed. It may wary from SoC to SoC. So move QSGMII wriop_init_dpmac() to SoC file. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28armv8/fsl-layerscape: Update erratum A009635 implementationPriyanka Jain
Erratum A009635 is valid only for LS2080A SoC and its personality. Add SoC svr check. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28pci: layerscape: enable PCIe config readyHou Zhiqiang
In EP mode, to enable accesses from the Root Complex, the CONFIG_READY bit must be set, otherwise any config attempts from the Root Complex will be returned with config retry status (CRS). Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28fsl: Secure Boot: Enable IE (Key extention) FeatureUdit Agarwal
For validating images from uboot (Such as Kernel Image), either keys from SoC fuses can be used or keys from a verified table of public keys can be used. The latter feature is called IE Key Extension Feature. For Layerscape Chasis 3 based platforms, IE table is validated by Bootrom and address of this table is written in scratch registers 13 and 14 via PBI commands. Following are the steps describing usage of this feature: 1) Verify IE Table in ISBC phase using keys stored in fuses. 2) Install IE table. (To be used across verification of multiple images stored in a static global structure.) 3) Use keys from IE table, to verify further images. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Saksham Jain <saksham.jain@nxp.com> Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28armv8: ls2080ardb, ls2080aqds: Add mcmemsize in default env settingSantan Kumar
Initialize mcmemsize to 0x40000000 Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28fsl-layerscape/ppa: cleanup ppa.hHou Zhiqiang
Moved the ifdef into ppa.h and removed the duplicated macros. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28armv8: LS2080A: Move sec_init to board_initUdit Agarwal
Moves sec_init to board_init rather than in misc_init function beacuse PPA will be initialised in board_init function and for PPA validation sec_init has to be done prior to PPA init. Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28armv8: lsch3: SECURE_BOOT: Define CONFIG_SYS_LS_PPA_ESBC_ADDR for LS2080AUdit Agarwal
Add header address for PPA to be validated during ESBC phase for LS2080A platform based on Layescape Chasis 3. Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28i2c: Set default I2C bus numberLukasz Majewski
This patch allows using i2c commands (e.g. "i2c probe", "i2c md", etc) without the need to first select the bus number with e.g. "i2c dev 0". This is the "i2c" command behavior similar to the one from pre DM, where by default bus 0 was immediately accessible. Signed-off-by: Lukasz Majewski <lukma@denx.de>
2017-03-28i2c: ti: Update method to calculate psc, sscl and ssch I2C parametersLukasz Majewski
This patch updates the way in which psc, sscl and ssch I2C parameters are calculated to be in sync with v4.9 Linux kernel SHA1: 69973b830859bc6529a7a0468ba0d80ee5117826 in the ./drivers/i2c/busses/i2c-omap.c The previous method was causing several issues: - The internal I2C frequency (after prescaler) was far above recommended one (7 - 12 MHz [*]) - the current approach brings better noise suppression (as stated in Linux commit: SHA1: 84bf2c868f3ca996e5bb) - The values calculated (psc, sscl and ssch) were far from optimal, which caused on the test platform (AM57xx) the I2C0 SCL signal low time (Fast Mode) of ~1.0us (the standard requires > 1.3 us). [*] for AM57xx TRM SPRUHZ6G, Table 24,7 "HS I2C Register Values for Maximum I2C Bit Rates in I2C F/S, I2C HS Modes" Signed-off-by: Lukasz Majewski <lukma@denx.de>
2017-03-28i2c: ti: Update SCLH and SCLL to be in sync with v4.9 Linux kernelLukasz Majewski
v4.9 Linux release: SHA1: 69973b830859bc6529a7a0468ba0d80ee5117826 in the ./drivers/i2c/busses/i2c-omap.c recommends to use SCLH=5 and SCLL=7 values. This patch sets them to default. Signed-off-by: Lukasz Majewski <lukma@denx.de>
2017-03-28i2c: lpc32xx: Force consistent bus numberingLiam Beguin
Normally, this would probably be done by adding devicetree aliases to the main dtsi file for the lpc32xx and using bus->req_seq instead. Since we want to have consistent i2c numbering, we cannot force the bus->req_seq because. If for instance we have 3 buses numbered from 0 to 2 with i2c0 enabled, i2c1 disabled and i2c2 enabled; i2c2 can be selected using 'i2c dev 1' and 'i2c dev 2' commands because a bus can be probed using req_seq or seq interchangeably. Signed-off-by: Liam Beguin <lbeguin@tycoint.com> Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
2017-03-28i2c: lpc32xx: Move definitions to header fileLiam Beguin
Since the lpc32xx i2c driver does not yet support the devicetree bindings, this structure is also needed by the board file as the hardware description is done there. Signed-off-by: Liam Beguin <lbeguin@tycoint.com> Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
2017-03-28i2c: lpc32xx: Remove note for DM conversationSylvain Lemieux
Removed note in the LPC32xx I2C driver for DM conversation. Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
2017-03-28i2c: lpc32xx: Add DM for lpc32xx I2CLiam Beguin
Adding DM specific wrapper functions and definitions. Signed-off-by: Liam Beguin <lbeguin@tycoint.com> Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
generated by cgit (git 2.34.1) at 2025-01-20 15:56:19 +0000