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2016-02-21pinctrl: imx: Introduce pinctrl driver for i.MX6Peng Fan
Introduce pinctrl for i.MX6 1. pinctrl-imx.c is for common usage. It's used by i.MX6/7. 2. Add PINCTRL_IMX PINCTRL_IMX6 Kconfig entry. 3. To the pinctrl_ops implementation, only set_state is implemented. To i.MX6/7, the pinctrl dts entry is as following: &iomuxc { pinctrl-names = "default"; pinctrl_csi1: csi1grp { fsl,pins = < MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088 MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088 MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088 >; }; [.....] }; there is no property named function or groups. So pinctrl_generic_set_state can not be used here. 5. This driver is a simple implementation for i.mx iomux controller, only parse the fsl,pins property and write value to registers. 6. With DEBUG enabled, we can see log when "i2c bus 0": " set_state_simple op missing imx_pinctrl_set_state: i2c1grp mux_reg 0x14c, conf_reg 0x3bc, input_reg 0x5d8, mux_mode 0x0, input_val 0x1, config_val 0x4000007f write mux: offset 0x14c val 0x10 select_input: offset 0x5d8 val 0x1 write config: offset 0x3bc val 0x7f mux_reg 0x148, conf_reg 0x3b8, input_reg 0x5d4, mux_mode 0x0, input_val 0x1, config_val 0x4000007f write mux: offset 0x148 val 0x10 select_input: offset 0x5d4 val 0x1 write config: offset 0x3b8 val 0x7f " this means imx6 pinctrl driver works as expected. Signed-off-by: Peng Fan <van.freenix@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-02-21imx: Refactoring CAAM Job Ring structure and Secure Memory for imx7Ulises Cardenas
Refactored data structure for CAAM's job ring and Secure Memory to support i.MX7. The new memory map use macros to resolve SM's offset by version. This will solve the versioning issue caused by the new version of secure memory of i.MX7 Signed-off-by: Ulises Cardenas <raul.casas@nxp.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
2016-02-21mx7dsabresd: Make 'ums' command functionalFabio Estevam
When running the 'ums' command we get: => ums 0 mmc 0 UMS: disk start sector: 0x0, count: 0xe18000 g_dnl_register: failed!, error: -22 ERROR: g_dnl_register failed at common/cmd_usb_mass_storage.c:107/do_usb_mass_storage() Fix this by initializing USB OTG1 port as USB device mode instead of host. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2016-02-21mx7dsabresd: Use Adrian's NXP email addressFabio Estevam
Use the new NXP email address for the board maintainer. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2016-02-21mx6ul_14x14_evk: Select CONFIG_FSL_QSPIFabio Estevam
Select CONFIG_FSL_QSPI so that the SPI can be probed: => sf probe SF: Detected N25Q256 with page size 256 Bytes, erase size 64 KiB, total 32 MiB Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2016-02-21mxsboot: remove unused includeAndreas Bießmann
Commit 276d3ebb883024d753cd9c69ab2fd243ffa1262e removed htole32() but missed to remove the corresponding header. This is annoying, since BSD systems do not have endian.h. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Michael Heimpold <mhei@heimpold.de>
2016-02-21x86: doc: Update to include Intel Bayley Bay board instructionsBin Meng
Update existing documentation to mention Intel Bayley Bay board instructions, an additional Bay Trail based board to MinnowMax. This also adds a minor change to QEMU section to indicate clearly the instructions are for bare mode. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-02-21x86: Add Intel Cougar Canyon 2 boardBin Meng
This adds basic support to Intel Cougar Canyon 2 board, a board based on Chief River platform with an Ivy Bridge processor and a Panther Point chipset. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2016-02-21x86: ivybridge: bd82x6x: Support FSP enabled configurationBin Meng
Wrap initialization codes with #ifndef CONFIG_HAVE_FSP #endif, and enable the build for both FSP and non-FSP configurations. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-02-21x86: fsp: Make sure HOB list is not overwritten by U-BootBin Meng
Intel IvyBridge FSP seems to be buggy that it does not report memory used by FSP itself as reserved in the resource descriptor HOB. The FSP specification does not describe how resource descriptor HOBs are generated by the FSP to describe what memory regions. It looks newer FSPs like Queensbay and BayTrail do not have such issue. This causes U-Boot relocation overwrites the important boot service data which is used by FSP, and the subsequent call to fsp_notify() will fail. To resolve this, we find out the lowest memory base address allocated by FSP for the boot service data when walking through the HOB list in fsp_get_usable_lowmem_top(). Check whether the memory top address is below the FSP HOB list, and if not, use the lowest memory base address allocated by FSP as the memory top address. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested on link (ivybridge non-FSP) Tested-by: Simon Glass <sjg@chromium.org>
2016-02-21superio: Add SMSC SIO1007 driverBin Meng
The SMSC SIO1007 superio chipset integrates two ns16550 compatible serial ports for legacy applications, 16 GPIO pins and some other functionalities like power management. This adds a simple driver to enable serial port and handle GPIO. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-02-21x86: ivybridge: Add FSP supportBin Meng
IvyBridge FSP package is built with a base address at 0xfff80000, and does not use UPD data region. This adds basic FSP support. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested on link (ivybridge non-FSP) Tested-by: Simon Glass <sjg@chromium.org>
2016-02-21x86: fix memalign() parameter orderStephen Warren
Purely by code inspection, it looks like the parameter order to memalign() is swapped; its parameters are (align, size). 4096 is a likely desired alignment, and a variable named size sounds like a size:-) Fixes: 45b5a37836d5 ("x86: Add multi-processor init") Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2016-02-20Merge branch 'master' of git://git.denx.de/u-boot-atmelTom Rini
2016-02-20vinco: add Maintainers fileAndreas Bießmann
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
2016-02-20arc: cache - utilize IO coherency (AKA IOC) engineAlexey Brodkin
With release of ARC HS38 v2.1 new IO coherency engine could be built-in ARC core. This hardware module ensures coherency between DMA-ed data from peripherals and L2 cache. With L2 and IOC enabled there's no overhead for L2 cache manual maintenance which results in significantly improved IO bandwidth. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2016-02-20arc: cache - accommodate different L1 cache line lengthsAlexey Brodkin
ARC core could be configured with different L1 and L2 (AKA SLC) cache line lengths. At least these values are possible and were really used: 32, 64 or 128 bytes. Current implementation requires cache line to be selected upon U-Boot configuration and then it will only work on matching hardware. Indeed this is quite efficient because cache line length gets hardcoded during code compilation. But OTOH it makes binary less portable. With this commit we allow U-Boot to determine real L1 cache line length early in runtime and use this value later on. This extends portability of U-Boot binary a lot. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2016-02-19spl: if MMCSD_MODE_RAW fails, try MMCSD_MODE_FSGuillaume GARDET
Since commit fd61d39970b9901217efc7536d9f3a61b4e1752a: spl: mmc: add break statements in spl_mmc_load_image() RAW and FS boot modes are now exclusive again. So, if MMCSD_MODE_RAW fails, the board hangs. This patch allows to try MMCSD_MODE_FS then. It has been tested on a beaglebone black to boot on an EXT partition. Signed-off-by: Guillaume GARDET <guillaume.gardet@free.fr> Cc: Tom Rini <trini@konsulko.com> Cc: Nikita Kiryanov <nikita@compulab.co.il> Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Paul Kocialkowski <contact@paulk.fr> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Simon Glass <sjg@chromium.org> Cc: Matwey V. Kornilov <matwey.kornilov@gmail.com> Acked-by: Nikita Kiryanov <nikita@compulab.co.il>
2016-02-19Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini
2016-02-19ARM: Add Support for the VInCo platformGregory CLEMENT
The Versatile Industrial Communication platform is a community oriented board from Landis + Gyr. It comes with: - an RS-485 port - 2 Ethernet ports - a wireless M-BUS - a 4G modem - a 4MB SPI flash - a 4GB eMMC Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> [rebase on current TOT] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2016-02-18ARM: at91: sama5d2: configure the L2 cache memorySamuel Mescoff
The SAMA5D2 has a second internal SRAM that can be reassigned as a L2 cache memory. Make sure it is configured as a L2 cache memory when booting from a SPL image. Based on the commit b5ea95ef2b5b from the at91bootstrap repository. Signed-off-by: Samuel Mescoff <samuel.mescoff@mobile-devices.fr> Reviewed-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
2016-02-18arm: at91: Add support for DENX MA5D4 SoM and EVKMarek Vasut
Add support for DENX MA5D4 SoM and MA5D4EVK board, based on the Atmel SAMA5D4 SoC. The SoM contains the SoC, eMMC, SPI NOR, SPI CAN controllers and DRAM, the baseboard contains UART connectors, ethernet port, microSD slot, LCD header, 2x CAN connector and a lot of expansion headers. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Andreas Bießmann <andreas.devel@googlemail.com> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
2016-02-18siemens,at91: enable features for smartwebMatthias Michel
New features for smartweb: * switch to hush command parser * change autoboot stop to <ESC><ESC> * allow to write ethaddr Signed-off-by: Matthias Michel <matthias.michel@siemens.com> Reviewed-by: Samuel Egli <samuel.egli@siemens.com> Cc: Roger Meier <r.meier@siemens.com> Cc: Heiko Schocher <hs@denx.de> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
2016-02-18board: atmel: clean up the PMC_PLLICPR init codeWenyou Yang
Due to introducing the PMC_PLLICPR init function, use this function to clean up the code. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Tested-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
2016-02-18ARM: at91: clean up the PMC_PLLICPR init codeWenyou Yang
Due to introducing the PMC_PLLICPR init function, use this function to clean up the code. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Tested-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
2016-02-18ARM: at91: clock: add PMC_PLLICPR init functionWenyou Yang
To avoid the duplicated code, add the PMC_PLLICPR init function. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Tested-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
2016-02-18board: atmel: siemens: clean up PLLB codeWenyou Yang
Due to introducing the new PLLB clock handle functions, use these functions to clean up the PLLB enable code. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> Tested-by: Heiko Schocher <hs@denx.de>
2016-02-18drivers: usb: ohci-at91: clean up the PLLB codeWenyou Yang
Due to introducing the new PLLB clock handle functions, use these functions to clean up the PLLB enable/disable code. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> Tested-by: Heiko Schocher <hs@denx.de>
2016-02-18ARM: at91: clock: add PLLB enable/disable functionsWenyou Yang
To avoid the duplicated code, add the PLLB handle functions. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> Tested-by: Heiko Schocher <hs@denx.de> [add enable/disable functions to arm920t] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2016-02-18board: atmel: siemens: clean up UTMI PLL codeWenyou Yang
Due to introducing the new UTMI PLL clock handle functions, use the functions to reduce the duplicated code. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Tested-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
2016-02-18drivers: usb: atmel: clean up the UTMI PLL codeWenyou Yang
Due to introducing the new UTMI PLL clock handle functions, use these function to reduce the duplicated code. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Tested-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
2016-02-18ARM: at91: armv7: clean up UTMI PLL handle codeWenyou Yang
Due to introducing the UTMI PLL enable function, use this function to reduce the duplicated code. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Tested-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
2016-02-18ARM: at91: clock: add UTMI PLL enable/disable functionWenyou Yang
To avoid the duplicated code, add the UTMI PLL handle functions, and add PMC_USB init function too. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Tested-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
2016-02-18drivers: at91: clean up peripheral clock codeWenyou Yang
Due to introducing the new peripheral clock handle functions, use these functions to reduce the duplicated code. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Tested-by: Heiko Schocher <hs@denx.de> [fixup for missing clk.h in at91_emac.c] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2016-02-18board: atmel: clean up peripheral clock codeWenyou Yang
Due to introducing the new peripheral clock handle functions, use these functions to reduce duplicated code. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Tested-by: Heiko Schocher <hs@denx.de> [Rebased on current master, fixup for at91rm9200ek] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2016-02-18ARM: cpu: at91: clean up peripheral clock codeWenyou Yang
Due to introducing the new peripheral clock handle functions, use these functions to clean up the duplicated code. Meanwhile, remove unneeded header file include, at91_pmc.h. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Tested-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> [fixup for arm920t code] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2016-02-18ARM: at91: clock: add a new file to handle clockWenyou Yang
To reduce the duplicated code, add a new file to accommodate the peripheral's and system's clock handle code, shared with the SoCs with different ARM core. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Tested-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
2016-02-18ARM: at91: asm/at91_pmc.h: fix trival register offsetWenyou Yang
Remove unnecessary #ifdef CPU_HAS_PCR. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Tested-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
2016-02-18net: phy: marvell: Fix problem with phy_reset() clearing BMCRStefan Roese
With commit a058052c [net: phy: do not read configuration register on reset], phy_reset() will clear the BMCR register. Resulting in bit 12 being cleared (A/N enable). This leads to autonegotiation link problems, at least on the Marvell Armada ClearFog board. I suspect that other boards using this driver will be affected as well. At the of m88e1111s_config(), phy_reset() is called. This is not needed for the PHY to load the changed configuration, as phy_reset() is called a few lines before already. So lets call genphy_restart_aneg() here instead to start the AN correctly. Tested on clearfog. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Stefan Agner <stefan@agner.ch> Cc: Hao Zhang <hzhang@ti.com> Cc: Michal Simek <monstr@monstr.eu> Cc: Andy Fleming <afleming@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-02-18net: phy: marvell: Call phy_reset() where possibleStefan Roese
Instead of coding the soft PHY reset function multiple times in marvell.c, lets call the common phy_reset() function from phy.c. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Stefan Agner <stefan@agner.ch> Cc: Hao Zhang <hzhang@ti.com> Cc: Michal Simek <monstr@monstr.eu> Cc: Andy Fleming <afleming@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-02-18ARM: tegra: enable USB device mode port on DalmoreStephen Warren
This allows U-Boot to expose UMS and DFU protocols on this port in device mode, or to act as a USB host on the port, using an "OTG" (micro-B to female A host) cable. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-02-18ARM: tegra: don't set CONFIG_USB_MAX_CONTROLLER_COUNTStephen Warren
This option is no longer used now that DM_USB is enabled. Fixes: 534f9d3feffd ("dm: tegra: usb: Move USB to driver model") Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-02-17video: tegra: Correct a Kconfig warning with VIDCONSOLE_AS_LCDSimon Glass
This new feature causes a Kconfig warning on boards without a display enabled. Fix this. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de> Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-02-16tegra: video: Clean up the old LCD/PWM driver codeSimon Glass
Remove the old PWM code. Remove calls to CONFIG_LCD functions now that we are using driver model for video. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-02-16tegra: video: Move LCD driver to use the DM PWM driverSimon Glass
Use the driver-model PWM driver in preference to the old code. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-02-16tegra: Convert CONFIG_PWM_TEGRA to KconfigSimon Glass
Move this option to Kconfig and clean up the header files. Adjust the only user (the LCD driver) to work with the new driver. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-02-16tegra: video: Move all fdt-decoding into a single functionSimon Glass
Join the two functions which decode the device tree and put them in the ofdata_to_platdata() method. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-02-16tegra: video: Move LCD enums into the driverSimon Glass
There is no need to have these in a separate file as they are not referenced from anywhere else. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-02-16tegra: video: Remove the static variablesSimon Glass
We can move the static variables into the driver-private data. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-02-16tegra: video: Convert tegra20 LCD driver to driver modelSimon Glass
Move this driver over to use driver model. This involves rearranging the code somewhat. The effect is that everything is run from the probe() method. Boards which use this are fixed up, but only seaboard is tested. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
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