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2012-09-01arm: omap: Fix switching back to nandecc sw.Jeroen Hofstee
Orjan Friberg wrote at [1]: "For the beagleboard, ecc.size is not explicitly set when doing 'nandecc sw'. If it's not set for the NAND_ECC_SOFT case in nand_scan_tail, it's set to 256 bytes. When doing 'nandecc hw', ecc.size is set to 512 bytes. Hence, when changing back to 'nandecc sw' ecc.size remains at 512 bytes and suddenly the format has changed." No patch has been submitted and the issue was still present. This patch adds the mentioned solution. Tested on a tam3517 board. [1] http://lists.denx.de/pipermail/u-boot/2012-February/119002.html cc: Orjan Friberg <of@flatfrog.com> Acked-by: Igor Grinberg <grinberg@compulab.co.il> Acked-by: Nikita Kiryanov <nikita@compulab.co.il> Signed-off-by: Jeroen Hofstee <jhofstee@victronenergy.com>
2012-09-01davinci: enbw_cmc: change switch init behaviourHeiko Schocher
change the behaviour of switch initialization: - rename "pwl" to "lan" in hwconfig parameter "lan" = port 1 with phy addr 2 "lmn" = port 2 with phy addr 3 - if we have a valid switch config file in flash, do not evaluate the settings in the hwconfig "lan" or "lmn" subcommand. - if we have no valid switch config file in flash, start the switch with default values, if we have a "lan" or a "lmn" hwconfig subcommand. If no "lan" or "lmn" is found in hwconfig, do nothing with the switch. Signed-off-by: Heiko Schocher <hs@denx.de>
2012-09-01am33xx evm: Update secure_emif_sdram_config during ddr initSatyanarayana, Sandhya
This patch updates secure_emif_sdram_config with the same value written to sdram_config during ddr3 initialization. During suspend/resume, this value is copied into sdram_config. With this, a write to sdram_config at the end of resume sequence which triggers an init sequence can be avoided. Without this register write in place, the DDR_RESET line goes low for a few cycles during resume which is a violation of the JEDEC spec. Signed-off-by: Satyanarayana, Sandhya <sandhya.satyanarayana@ti.com>
2012-09-01da8xx/hawkboard: Add support for ohci host controllerSughosh Ganu
Also enable the ohci port on hawkboard. These additions result in an increased u-boot size -- adjust the same accordingly in the board's config. Move the usb header for da8xx platforms under arch-davinci. Signed-off-by: Sughosh Ganu <urwithsughosh@gmail.com>
2012-09-01armv7: Make lowlevel_init.S's lowlevel_init do ABI compatible stackTom Rini
Make sure that when we setup the stack before calling s_init() we have the stack have 8-byte alignment for ABI compliance. Tested-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01omap4/5/am33xx: Make lowlevel_init available to all armv7 platformsTom Rini
Make the lowlevel_init function that these platforms have which just sets up the stack and calls a C function available to all armv7 platforms. As part of this we change some of the macros that are used to be more clear. Previously (except for am335x evm) we had been setting CONFIG_SYS_INIT_SP_ADDR to a series of new defines that are equivalent to simply referencing NON_SECURE_SRAM_END. On am335x evm we should have been doing this initially and do now. Cc: Sricharan R <r.sricharan@ti.com> Tested-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01am335x evm: Enable support for spi0Tom Rini
Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01am33xx: Add support, update omap3 McSPI driverTom Rini
Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01am335x evm: Enable MMC1 pinmuxTom Rini
MMC1 is available in profile 2 on the GP EVM and is exposed on the expansion header on beaglebone. Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01am33xx: Correct MMC1, remove MMC2 supportTom Rini
- Correct the MMC1 base offset - Remove MMC2 (that area is reserved and not MMC2). - Add the real BOOT_DEVICE_MMC2 value Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01am335x evm: Initial support for AM335x GP EVM ProfilesTom Rini
The AM335x GP EVM can have one of 8 different profiles selected. Each profile has a different set of peripherals and requires different pinmux configurations that conflict with other profiles. i2c1 is an example of a conflicted mux currently. Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01sc_sps_1: Adjust board config to use 'mxs' SoC codeOtavio Salvador
Fix build failure due the move of mx28 code to 'mxs' SoC. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Acked-by: Stefano Babic <sbabic@denx.de>
2012-09-01rtc: imxdi: Initial supportBenoît Thébaudeau
Add support for Freescale's i.MX DryIce RTC, present on i.MX25. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
2012-09-01MX28: Add SchulerControl SC_SPS_1 platformMarek Vasut
This i.MX28 platform supports the following: * 2x FEC ethernet * USB on USBH0 * I2C EEPROM * SPI NVRAM * LEDs Signed-off-by: Marek Vasut <marex@denx.de>
2012-09-01i.MX28: bug fixes in PMU configuration codeStathis Voukelatos
Signed-off-by: Stathis Voukelatos <stathis.voukelatos@linn.co.uk> Cc: Stefano Babic <sbabic@denx.de> Cc: Marek Vasut <marek.vasut@gmail.com>
2012-09-01MX28: Move the u-boot.bd info CPUDIR/SOCDIRMarek Vasut
This gets us rid of duplication of the same file. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
2012-09-01vision2: do not overwrite the consoleFabio Estevam
On this board, the console is always set to the serial line. Do not allow to overwrite it when video is enabled. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-09-01mx51evk: do not overwrite the consoleFabio Estevam
On this board, the console is always set to the serial line. Do not allow to overwrite it when video is enabled. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-09-01MX5: mx53loco: do not overwrite the consoleStefano Babic
On this board, the console is always set to the serial line. Do not allow to overwrite it when video is enabled. Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Fabio Estevam <fabio.estevam@freescale.com> Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-09-01MX28: Fix MXS MMC DMA issuesMarek Vasut
The DMA didn't work properly because the DMA descriptor wasn't properly cleaned after it was used once. Also, the DMA_ENABLE bit was enabled/disabled too late. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <festevam@freescale.com> Cc: Andy Fleming <afleming@freescale.com>
2012-09-01MX28: Transfer small blocks via PIO in MXS MMCMarek Vasut
Large blocks (> 512b) shall be transfered via DMA to make things a bit faster. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <festevam@freescale.com> Cc: Andy Fleming <afleming@freescale.com>
2012-09-01MX28: Split out the PIO and DMA transfer functionsMarek Vasut
Move DMA and PIO data transfer parts into separate functions. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <festevam@freescale.com> Cc: Andy Fleming <afleming@freescale.com>
2012-09-01MX28: Fix up the MMC driver DMA modeMarek Vasut
The DMA mode didn't properly configure the DMA_ENABLE bit in CTRL1. Also, it was using SSP0 DMA channel for all SSP devices. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <festevam@freescale.com> Cc: Andy Fleming <afleming@freescale.com>
2012-09-01mxs: rename mx28.c to mxs.c as it is common to i.MX233 and i.MX28 SoCsOtavio Salvador
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
2012-09-01mxs: Clarify why we poweroff in case of brownout in 5v conflictOtavio Salvador
If VDDIO has a brownout, then the VDD5V_GT_VDDIO becomes unreliable but this wasn't clear on code so a comment has been added to clarify it. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
2012-09-01mxs: Reowork SPL to use 'mxs' prefix for methodsOtavio Salvador
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
2012-09-01mxs: prefix register structs with 'mxs' prefixOtavio Salvador
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
2012-09-01mxs: prefix register acessor macros with 'mxs' prefixOtavio Salvador
As the register accessing mode is the same for all i.MXS SoCs we ought to use 'mxs' prefix intead of 'mx28'. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
2012-09-01mxs: reorganize source directory for easy sharing of code in i.MXS SoCsOtavio Salvador
Most code can be shared between i.MX23 and i.MX28 as both are from i.MXS family; this source directory structure makes easy to share code among them. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Acked-by: Stefano Babic <sbabic@denx.de>
2012-09-01mx28evk: Turn on cachesFabio Estevam
Turn on data and instruction caches. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2012-09-01MX28: use a clear name for DDR2 initializationOtavio Salvador
The mx28 prefix has been added to the initialization data and function so it is clear by which SoC it is used as i.MX233 will have a specific one. While on that, we also change it to static. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Acked-by: Marek Vasut <marex@denx.de>
2012-09-01Add support for Bluegiga APX4 Development KitVeli-Pekka Peltola
This adds support for Bluegiga APX4 Development Kit. It is built around Freescale i.MX28. Currently supported features are: ethernet, I2C, MMC, RTC and USB. APX4 has only one ethernet port. Signed-off-by: Veli-Pekka Peltola <veli-pekka.peltola@bluegiga.com> Signed-off-by: Lauri Hintsala <lauri.hintsala@bluegiga.com> Cc: Stefano Babic <sbabic@denx.de>
2012-09-01MX28: extend print_cpuinfo() to use chip informationOtavio Salvador
The information now is gathered from HW_DIGCTL_CHIPID register and includes the chip modem and revision on the output. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
2012-09-01MX28: SPI: Add DMA transfer supportMarek Vasut
The DMA transfers happen only if the transfered data are larger than 512 bytes. Otherwise PIO is used. This is a small speed optimization. The DMA transfer doesn't work if unaligned transfer is requested due to the limitation of the DMA controller. This has to be fixed by introducing generic bounce buffer. Therefore the DMA feature is now disabled by default. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de>
2012-09-01MX28: SPI: Pull out the PIO transfer functionMarek Vasut
Pull out all the PIO transfer logic into separate function, so DMA can be added. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de>
2012-09-01MX28: SPI: Refactor spi_xfer a bitMarek Vasut
This makes it easier to adapt for addition of DMA support. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de> Cc: Wolfgang Denk <wd@denx.de>
2012-09-01imx: Use a clear identification of an unidentified CPU typeOtavio Salvador
In case an unidentified CPU type is detected it now returns i.MX??, in a const char. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com>
2012-09-01at91: Add support for taskit AT91SAM9G20 boards.Markus Hubig
This adds support for the AT91SAM9G20 boards by taskit GmbH. Both boards, Stamp9G20 and PortuxG20, are integrated in one file. PortuxG20 is basically a SBC built around the Stamp9G20. Signed-off-by: Markus Hubig <mhubig@imko.de> Cc: Andreas Bießmann <andreas.devel@googlemail.com> Signed-off-by: Andreas Bießmann <andreas.deve@googlemail.com>
2012-09-01Enable the EMAC clock in at91_macb_hw_init().Markus Hubig
Signed-off-by: Markus Hubig <mhubig@imko.de> Cc: Andreas Bießmann <andreas.devel@googlemail.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2012-09-01MAINTAINERS: fix Andreas Bießmann AVR32 entryAndreas Bießmann
The grasshopper board is a avr32 based device and belongs therefore to the avr32 section. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2012-09-01MAINTAINERS: fix entry of Ilko IlievAndreas Bießmann
These boards have ARM cores, move to the ARM section. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2012-09-01arm : Atmel : add at91sam9x5ek board supportBo Shen
Add at91sam9x5ek board support, this board support the following SoCs AT91SAM9G15, AT91SAM9G25, AT91SAM9G35, AT91SAM9X25, AT91SAM9X35 Using at91sam9x5ek_nandflash to configure for the board Now only supports NAND with software ECC boot up Signed-off-by: Bo Shen <voice.shen@atmel.com> [move MAINTAINERS entry to right place] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2012-09-01doc/git-mailrc: update at91 and avr32Andreas Bießmann
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2012-09-01am335x_evm: enable SMSC PHY driverIlya Yanok
Beaglebone uses SMSC PHY which works incorrectly with generic PHY driver so enable SMSC PHY driver to fix networking problems on Beaglebone. Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
2012-09-01OMAP3: fix DRAM size for IGEP-based boards.Enric Balletbò i Serra
The total RAM size of the IGEP-based boards is 512MiB not 1GiB, the LPDDR memory consist on two dies of 256MiB. Signed-off-by: Enric Balletbo i Serra <eballetbo@gmail.com> Tested-by: Javier Martinez Canillas <javier@dowhile0.org>
2012-09-01DaVinci DA8xx: fix set_cpu_clk_info()Laurence Withers
For the DA8xx family of SoCs, the set_cpu_clk_info() function was not initialising the DSP frequency, leading to 'bdinfo' command output such as: [...snip...] ARM frequency = 300 MHz DSP frequency = -536870913 MHz DDR frequency = 300 MHz This commit provides a separate implementation of set_cpu_clk_info() for the DA8xx SoCs that initialises the DSP frequency to zero (since currently the DSP is not enabled by U-Boot on any DA8xx platform). The separate implementation is justified because there is no common code between DA8xx and the other SoC families. It is now much easier to understand the flow of the two separate functions. Signed-off-by: Laurence Withers <lwithers@guralp.com> Cc: Tom Rini <trini@ti.com> Cc: Hadli, Manjunath <manjunath.hadli@ti.com> Cc: Heiko Schocher <hs@denx.de>
2012-09-01DaVinci DA8xx: replace magic number for DDR speedLaurence Withers
Replace a magic number for the DDR2/mDDR PHY clock ID with a proper definition. In addition, don't request this clock ID on DA830 hardware, which does not have a DDR2/mDDR PHY (or associated PLL controller). Signed-off-by: Laurence Withers <lwithers@guralp.com> Cc: Tom Rini <trini@ti.com> Cc: Prabhakar Lad <prabhakar.csengg@gmail.com>
2012-09-01DaVinci DA850: UART2 clock ID comes from ASYNC3Laurence Withers
On the DA830, UART2's clock is derived from PLL controller 0 output 2. On the DA850, it is in the ASYNC3 group, and may be switched between PLL controller 0 or 1. Fix the definition of the ID to match. Signed-off-by: Laurence Withers <lwithers@guralp.com> Cc: Tom Rini <trini@ti.com> Cc: Prabhakar Lad <prabhakar.csengg@gmail.com>
2012-09-01DaVinci DA8xx: tidy up clock ID definitionLaurence Withers
Tidy up the clock IDs defined for the DA8xx SOCs. With this new structure in place, it is clear how to define new clock IDs, and how these map to the numbers presented in the technical reference manual. Signed-off-by: Laurence Withers <lwithers@guralp.com> Cc: Tom Rini <trini@ti.com> Cc: Prabhakar Lad <prabhakar.csengg@gmail.com> Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01doc/git-mailrc: Update 'ti' aliasTom Rini
Remove Sandeep, thanks for all the hard work! Signed-off-by: Tom Rini <trini@ti.com>
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