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2016-09-06warp7: Print secure/non-secure mode infoFabio Estevam
warp7 has two targets: - warp7_defconfig: boots in non-secure mode - warp7_secure_defconfig: boots in secure mode Print the mode that is being used to help users to easily identify which target is running on the board. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2016-09-06warp7: Use PARTUUID to specify the rootfs locationFabio Estevam
warp7 can run different kernel versions, such as NXP 4.1 or mainline. Currently the rootfs location is passed via mmcblk number and the problem with this approach is that the mmcblk number for the eMMC changes depending on the kernel version. In order to avoid such issue, use UUID method to specify the rootfs location. Succesfully tested booting a NXP 4.1 and also a mainline kernel. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2016-09-06warp7: Add a secure mode targetFabio Estevam
NXP kernel expects to boot in secure mode, so introduce warp7_secure_defconfig target which selects CONFIG_ARMV7_BOOT_SEC_DEFAULT. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2016-09-06mx6ul_14x14_ev: Enable the CCGR clocks earlierFabio Estevam
To be in the safe side we need to enable the CCGR clocks prior to calling arch_cpu_init(). Inspired by Tim Harvey's commit d783c2744f9 ("imx: ventana: fix boot to SD"). Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Eric Nelson <eric@nelint.com> Tested-by: Eric Nelson <eric@nelint.com>
2016-09-06mx6ul_14x14_evk: Adjust SPL DDR3 settingsFabio Estevam
Adjust DDR3 initialization done in SPL by comparing them against the NXP DCD table. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Eric Nelson <eric@nelint.com>
2016-09-06mx6ul_14x14_evk: Pass refsel and refr fields to avoid hangFabio Estevam
When running a NXP 4.1 kernel with U-Boot mainline on a mx6ul-evk, we observe a hang when going into the lowest operational point of cpufreq. This hang issue does not happen on the NXP U-Boot version. After comparing the SPL DDR initialization against the DCD table from NXP U-Boot, the key difference that causes the hang is the MDREF register setting: DATA 4 0x021B0020 0x00000800 ,which means: REF_SEL = 0 --> Periodic refresh cycle: 64kHz REFR = 1 ---> Refresh Rate - 2 refreshes So adjust the MDREF initialization for mx6ul_evk accordingly to fix the kernel hang issue at low bus frequency. Reported-by: Eric Nelson <eric@nelint.com> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Eric Nelson <eric@nelint.com>
2016-09-06mx6: ddr: Allow changing REFSEL and REFR fieldsFabio Estevam
Currently MX6 SPL DDR initialization hardcodes the REF_SEL and REFR fields of the MDREF register as 1 and 7, respectively for DDR3 and 0 and 3 for LPDDR2. Looking at the MDREF initialization done via DCD we see that boards do need to initialize these fields differently: $ git grep 0x021b0020 board/ board/bachmann/ot1200/mx6q_4x_mt41j128.cfg:DATA 4 0x021b0020 0x00005800 board/ccv/xpress/imximage.cfg:DATA 4 0x021b0020 0x00000800 /* MMDC0_MDREF */ board/freescale/mx6qarm2/imximage.cfg:DATA 4 0x021b0020 0x7800 board/freescale/mx6qarm2/imximage.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6qarm2/imximage_mx6dl.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6qarm2/imximage_mx6dl.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6qsabreauto/imximage.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6qsabreauto/mx6dl.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6qsabreauto/mx6qp.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6sabresd/mx6dlsabresd.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6slevk/imximage.cfg:DATA 4 0x021b0020 0x00001800 board/freescale/mx6sxsabreauto/imximage.cfg:DATA 4 0x021b0020 0x00000800 board/freescale/mx6sxsabresd/imximage.cfg:DATA 4 0x021b0020 0x00000800 board/warp/imximage.cfg:DATA 4 0x021b0020 0x00001800 So introduce a mechanism for users to be able to configure REFSEL and REFR fields as needed. Keep all the mx6 SPL users in their current REF_SEL and REFR values, so no functional changes for the existing users. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Eric Nelson <eric@nelint.com>
2016-09-06mx7dsabresd: Directly write to register LDOGCTLFabio Estevam
Register LDOGCTL contains only bit 0 as a valid bit, so there is no need to do a read-modify-write operation. Simplify the code by writing directly to this register. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2016-09-06mx7dsabresd: Directly write to register LDOGCTLFabio Estevam
Register LDOGCTL contains only bit 0 as a valid bit, so there is no need to do a read-modify-write operation. Simplify the code by writing directly to this register. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2016-09-06pico-imx6ul: Directly write to register LDOGCTLFabio Estevam
Register LDOGCTL contains only bit 0 as a valid bit, so there is no need to do a read-modify-write operation. Simplify the code by writing directly to this register. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2016-09-06ARM: board: cm_fx6: fix mtd partition fixupChristopher Spinrath
ft_board_setup may return early in the case that the board revision cannot be obtained. In that case it is assumed that no revision specific correction in the fdt is neccessary. But the mtd partitions will not be fixed up either altough they are not revision specific. Move the call to fdt_fixup_mtdparts in front of the revision specific part to ensure that the partitions are fixed up even if the board revision cannot be obtained. While on it, fix a spelling mistake in a comment introduced by the same commit. Fixes: 62d6bac66038 ("ARM: board: cm_fx6: fixup mtd partitions in the fdt") Signed-off-by: Christopher Spinrath <christopher.spinrath@rwth-aachen.de> Reviewed-by: Stefano Babic <sbabic@denx.de> Reviewed-by: Nikita Kiryanov <nikita@compulab.co.il>
2016-09-06mx6ul_14x14_evk: don't use array for SD2 card detect padEric Nelson
Only a single pad is changed to change sdhc2_dat3 from an SDIO pin to and from GPIO4:5, so remove the array and use the imx_iomux_v3_setup_pad() routine. Signed-off-by: Eric Nelson <eric@nelint.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2016-09-06warp7: Modify fdt_file environment variableBreno Lima
Use imx7s-warp.dts as fdt_file because this is the name that upstream kernel will deploy. Signed-off-by: Breno Lima <breno.lima@nxp.com> Acked-by: Fabio Estevam <fabio.estevam@nxp.com>
2016-09-06warp: Fix RAM size runtime detectionFabio Estevam
Since commit a13d3757f7df ("warp: Use imx_ddr_size() for calculating the DDR size") warp board no longer boots. The reason for the breakage is that the warp board is using the DDR configuration from mx6slevk. A fundamental difference between warp and mx6slevk is that warp only uses one DDR chip select while mx6slevk uses two. The imx_ddr() function calculates the RAM size in runtime by reading the values of registers MDCTL and MDMISC. So in order to fix this warp boot issue, create a imximage DDR file specific to warp, where the MDCTL register is configured to only activates a single chip select. Reported-by: Breno Lima <breno.lima@nxp.com> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Tested-by: Breno Lima <breno.lima@nxp.com>
2016-09-06warp7: Add PMIC supportVanessa Maegima
Add PMIC support. Tested by command "pmic PFUZE3000 dump". Signed-off-by: Vanessa Maegima <vanessa.maegima@nxp.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
2016-09-06arm: imx: Add support for Advantech DMS-BA16 boardAkshay Bhat
Add support for Advantech DMS-BA16 board. The board is based on Advantech BA16 module which has a i.MX6D processor. The board supports: - FEC Ethernet - USB Ports - SDHC and MMC boot - SPI NOR - LVDS and HDMI display Basic information about the module: - Module manufacturer: Advantech - CPU: Freescale ARM Cortex-A9 i.MX6D - SPECS: Up to 2GB Onboard DDR3 Memory; Up to 16GB Onboard eMMC NAND Flash Supports OpenGL ES 2.0 and OpenVG 1.1 HDMI, 24-bit LVDS 1x UART, 2x I2C, 8x GPIO, 4x Host USB 2.0 port, 1x USB OTG port, 1x micro SD (SDHC),1x SDIO, 1x SATA II, 1x 10/100/1000 Mbps Ethernet, 1x PCIe X1 Gen2 Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com> Cc: u-boot@lists.denx.de Cc: sbabic@denx.de
2016-09-06mx7dsabresd: Print secure/non-secure mode infoFabio Estevam
mx7dsabresd has two targets: - mx7dsabresd_defconfig: boots in non-secure mode - mx7dsabresd_secure_defconfig: boots in secure mode Print the mode that is being used to help users to easily identify which target is running on the board. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
2016-09-06mtd: nand: mxs: fix cache alignment for cache lines >32Stefan Agner
Currently the command buffer gets allocated with a size of 32 bytes. This causes warning messages on systems with cache lines bigger than 32 bytes: CACHE: Misaligned operation at range [9df17a00, 9df17a20] Define command buffer to be at least 32 bytes, but more if cache line is bigger. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
2016-09-06imx: ventana: enable splashscreen supportTim Harvey
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2016-09-06board: tbs2910: fix HDMI pre-console bufferSoeren Moch
HDMI output must be enabled very early to also enable the pre-console buffer Signed-off-by: Soeren Moch <smoch@web.de> Reviewed-by: Stefano Babic <sbabic@denx.de>
2016-09-06board: tbs2910: always enable usbkbdSoeren Moch
'usb start' is much faster now, so always enable usb keyboard Signed-off-by: Soeren Moch <smoch@web.de> Reviewed-by: Stefano Babic <sbabic@denx.de>
2016-09-01ARM: tegra: Add support for TK1-SOM board from Colorado EngineeringPeter Chubb
The Colorado TK1 SOM is a small form factor board similar to the Jetson TK1. The main differences lie in the pinmux, and in that the PCIe controller is set to use in 4lanes+1lane, rather than 2+2. The pinmux header here was generated from a spreadsheet provided by Colorado Engineering using the tegra-pinmux scripts. The spreadsheet was converted from v09 to v11 by me. Signed-off-by: Peter Chubb <peter.chubb@data61.csiro.au> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-08-30ARM: tegra: use numeric versioning for p2771-0000Stephen Warren
The board ID EEPROM and board ID stickers on p2771-0000 will use a numeric versioning scheme, with version numbers such as 000/100/200/300/400/500. Within NVIDIA, these versions are also known as A00/A01/A02/A03/A04/B00. However, that numbering scheme is not easily visible outside of NVIDIA, and so does not make much sense to use. Convert U-Boot to use the readily visible numeric scheme. Also, it turns out that the current A02 DT actually applies to board versions 000/100/200 (A00..A02). Consequently rename this to 000 not 200 so that all U-Boot builds are named after the first version of the HW they support. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2016-08-30x86: qemu: efi: Add two boards for EFI 32-bit and 64-bit payloadBin Meng
This introduces two board defconfig files for generating EFI 32-bit and 64-bit payloads, to run on QEMU x86 target. With these in place, hopefully buildman will catch any build error with EFI payload support on x86. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-08-30x86: efi: Fix EFI 64-bit payload build warningsBin Meng
There are lots of warnings when building EFI 64-bit payload. include/asm-generic/bitops/__fls.h:17:2: warning: left shift count >= width of type if (!(word & (~0ul << 32))) { ^ In fact, U-Boot itself as EFI payload is running in 32-bit mode. So BITS_PER_LONG needs to still be 32, but EFI status codes are 64-bit when booting from 64-bit EFI. Introduce EFI_BITS_PER_LONG to bridge those status codes with U-Boot's BITS_PER_LONG. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-08-30x86: efi: payload: Make EFI payload build againBin Meng
Since commit 73c5c39 "Makefile: Drop unnecessary -dtb suffixes", EFI payload does not build anymore. This fixes the build. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-08-30x86: Add debugging when cpu_common_init() failsSimon Glass
Add a debug() at this point to help figure out what is wrong. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-08-30x86: ivybridge: Allow microcode to be collatedSimon Glass
Generally the microcode is combined into a single block only (and removed from the device tree) when there are multiple blocks. But this is not a requirement. Adjust the ivybridge code to avoid assuming this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-08-30x86: Add debugging when a microcode update failsSimon Glass
Add a debug() at this point to help figure out what is wrong. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher<hs@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-08-28Merge branch 'master' of git://git.denx.de/u-boot-uniphierTom Rini
2016-08-28ARM: uniphier: enable CONFIG_CMD_CACHEMasahiro Yamada
This will be useful, for example, to load firmware to DRAM and make it visible to other agents. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-08-28ARM: uniphier: change UNIPHIER_SERIAL to default y optionMasahiro Yamada
This is very likely to be necessary for normal use cases. Set its default to 'y' for shorter defconfig files. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-08-28ARM: dts: uniphier: add u-boot, dm-pre-reloc to use eMMC boot on sLD3Masahiro Yamada
The eMMC on sLD3 is assigned with dedicated pins (only multiplexed with GPIO), so it shouldn't hurt to enable eMMC on SPL all the time. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-08-28ARM: uniphier: increase CONFIG_SYS_MALLOC_F_LEN for sLD3Masahiro Yamada
Commit 76c52ce29fd7 ("ARM: uniphier: increase CONFIG_SYS_MALLOC_F_LEN to bind all nodes") missed to increase this config for sLD3. This change is needed to add "u-boot,dm-pre-reloc" to some nodes; more devices are bound, more malloc memory is needed. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-08-28ARM: uniphier: display revision of Micro Support Card 3.6.x kindlyMasahiro Yamada
The revision of the original support card (rev 3.5, rev 3.6) fits in the 8 bit width revision register. When it was extended in a weird way, it was versioned in the format of "3.6.x" (where it should have been "3.7", of course). What is worse, only the sub-level version "6.x" was recorded in the 8 bit width register, completely ignoring the compatibility of the revision register format. This patch saves madly-versioned support cards by assuming the major version "3" when the MSB 4 bit of the register is read as "6". With this, the support card revision that were displayed as "6.10" is now corrected to "3.6.10". Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-08-28ARM: uniphier: support system reset functionality for PSCIMasahiro Yamada
This supports the system reset via PSCI for ARMv7 SoCs. Because the system reset is not supported on PSCI 0.1, let's define CONFIG_ARMV7_PSCI_1_0. (it is supported since PSCI 0.2, but there is no CONFIG to enable it in U-Boot for now.) Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-08-28mmc: uniphier-sd: just return if already set to desired clock rateMasahiro Yamada
With this, we can save unnecessary udelay(). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-08-28mmc: uniphier-sd: return error code if unsupported width is givenMasahiro Yamada
With the CONFIG_DM_MMC_OPS migration, the .set_ios callback can return an integer now. Return an appropriate error value rather than sudden death by BUG(). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-08-28mmc: uniphier-sd: move uniphier_sd_init() belowMasahiro Yamada
No more reason to define this function above the ops structure. Move it near the caller. Also, change its return type to void because it never fails. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-08-28mmc: uniphier-sd: migrate to CONFIG_DM_MMC_OPSMasahiro Yamada
Catch up with the DM migration. As struct dm_mmc_ops does not have .init callback, call the init function directly from the probe function. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-08-28mmc: uniphier-sd: add static qualifiers to probe and remove callbacksMasahiro Yamada
They are both only referenced in this file. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-08-27Merge git://git.denx.de/u-boot-rockchipTom Rini
2016-08-27rockchip: rk3399: update MAINTAINER fileKever Yang
This patch add maintainer information for rk3399 evb. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andreas Färber <afaerber@suse.de>
2016-08-26Merge branch 'master' of http://git.denx.de/u-boot-sunxiTom Rini
2016-08-26nand: Fix set_dev checks for no deviceTony Lindgren
If we do nand device 0 command in u-boot on a device that has NAND support enabled but no NAND chip, we can get data abort at least on omaps. Fix the issue by replacing the check with nand_info[dev] as suggested by Scott Wood. The check for name existed before because before the array-to-pointer conversion there was no way to directly test nand_info[dev] for emptiness. Signed-off-by: Tony Lindgren <tony@atomide.com>
2016-08-26treewide: fix "followings" to "following"Masahiro Yamada
Most of them are my mistakes. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-08-26tools: moveconfig: add Xtensa GCC prefix to CROSS_COMPILE listMasahiro Yamada
This is needed to move CONFIG options for the recently-added xtfpga_defconfig. The tarball of the pre-built toolchain can be downloaded from: https://www.kernel.org/pub/tools/crosstool/files/bin/x86_64/4.9.0/ Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-08-26arm: cache: always flush cache line size for page tableStefan Agner
The page table is maintained by the CPU, hence it is safe to always align cache flush to a whole cache line size. This allows to use mmu_page_table_flush for a single page table, e.g. when configure only small regions through mmu_set_region_dcache_behaviour. Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Tested-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
2016-08-26arm: cache: add support for LPAE for region D$ behaviorStefan Agner
Add LPAE support for mmu_set_region_dcache_behaviour. The function is in use in some LPAE capable board such TI DRA7xx or NXP i.MX 7. Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
2016-08-26arch/arm/Kconfig: Whitespace correctionTom Rini
Use a tab not 8 spaces. Signed-off-by: Tom Rini <trini@konsulko.com>
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