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2013-02-18am33xx: pcm051: Remove wp pin mux for sd-cardLars Poeschel
The pcm051 does not have the wp pin connected to the sd-card socket. Therefore remove the pinmux for the pin. The was a carry-over from the am335x evm code. Signed-off-by: Lars Poeschel <poeschel@lemonage.de>
2013-02-18beagle: expansion boards: add LSR COM6L adapterrobertcnelson@gmail.com
http://www.lsr.com/wireless-products/com6l The eeprom on this expansion board requires 16bit addressing. Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
2013-02-18beagle: expansion boards: retry i2c_read with 16bit addressingrobertcnelson@gmail.com
Some expansion boards now ship with at24 eeproms that need to communicate via 16bit addressing. Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
2013-02-18da8xx: Add the missing pinmux for da830 to the gpio driverTomas Novotny
The pinmux was generated from linux/arch/arm/mach-davinci/da830.c as of kernel version 3.7.5. If the driver is used for the da850, then SoC variant must be specified by CONFIG_SOC_DA850. Signed-off-by: Tomas Novotny <tomas@novotny.cz> Cc: Tom Rini <trini@ti.com>
2013-02-18da8xx: ea20: Add the configuration define for the exact SoC variantTomas Novotny
Signed-off-by: Tomas Novotny <tomas@novotny.cz> Cc: Tom Rini <trini@ti.com> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
2013-02-15Merge branch 'fixes' of git://git.denx.de/u-boot-mipsTom Rini
2013-02-15MIPS: board.c: remove manual relocation of env_name_specDaniel Schwierzeck
Remove the manual relocation of env_name_spec. This has been missed in the previous patch series for introducing dynamic relocation on MIPS. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2013-02-14x86: Remove unused real mode codeSimon Glass
This code is pretty old and we want to support only 32-bit systems now. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Graeme Russ <graeme.russ@gmail.com>
2013-02-14x86: Rename CONFIG_NO_X86_RESET_VECTOR to CONFIG_X86_RESET_VECTORSimon Glass
Invert the polarity of this option to simplify the Makefile logic. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Gabe Black <gabeblack@chromium.org>
2013-02-14x86: Remove unneeded cruft from main MakefileSimon Glass
These lines are dealt with in the x86 Makefile and link script, so punt them. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Gabe Black <gabeblack@chromium.org>
2013-02-14x86: Remove sc520 cpuSimon Glass
This x86 CPU variant is no longer required as the boards that use it have been removed. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Graeme Russ <graeme.russ@gmail.com>
2013-02-14x86: Remove eNET boardsSimon Glass
These are no longer used and should be removed. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Graeme Russ <graeme.russ@gmail.com>
2013-02-12Merge branch 'next' of git://git.denx.de/u-boot-mipsTom Rini
2013-02-12MIPS: add dynamic relocation supportGabor Juhos
The code handles relocation entries with the following relocation types only: mips32: R_MIPS_REL32 mips64: R_MIPS_REL+R_MIPS_64 xburst: R_MIPS_REL32 Other relocation entries are skipped without processing. The code must be extended if other relocation types must be supported. Add -pie to LDFLAGS_FINAL to generate the .rel.dyn fixup table, which will be applied to the relocated image before transferring control to it. The CONFIG_NEEDS_MANUAL_RELOC is not needed after the patch, so remove that as well. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2013-02-12MIPS: u-boot.lds: add relocation specific sectionsGabor Juhos
This section contain the table needed for dynamic relocation. Also provide symbols for the relocation code to access the table. Discard all sections which are not needed in the final ELF binary and U-Boot image. Section .dynsym cannot be discarded or GNU ld crashes otherwise. This section will be stripped by GNU objcpy in a later patch. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2013-02-12MIPS: start.S: use symbol __image_copy_end for U-Boot image relocationDaniel Schwierzeck
Use the newly introduced symbol __image_copy_end as end address for relocation of U-Boot image. This is needed for dynamic relocation added in later patches. This patch obsoletes the symbols uboot_end and uboot_end_data which are removed. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2013-02-12MIPS: start.S: optimize BSS initializationDaniel Schwierzeck
Get the start and end address for clearing BSS from the newly introduced symbols __bss_start and __bss_end. After GOT is relocated, those symbols are already pointing to the correct addresses. Also optimize the loop by moving the address incrementation to the delay slot to avoid the initial sub instruction. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2013-02-12MIPS: board.c: switch to new symbols __bss_end and __image_copy_endDaniel Schwierzeck
Use the newly introduced symbols __image_copy_end and __bss_end for setting up the memory area for the relocated U-Boot. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2013-02-12MIPS: u-boot.lds: introduce symbol __image_copy_endDaniel Schwierzeck
This symbol is used in later patches as end address for relocation of the U-Boot image into RAM. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2013-02-12MIPS: u-boot.lds: merge all BSS sections and introduce symbols __bss_[start|end]Daniel Schwierzeck
These symbols are used in later patches for as addresses for clearing the BSS area in the relocated U-Boot image. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2013-02-12MIPS: compute num_got_entries from .got section's sizeGabor Juhos
The '__got_start' and '__got_end' symbols are used only in the linker script to compute the value of the 'num_got_entries' symbol. Remove the symbols and use the SIZEOF(.got) command to get the size of the .got section. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2013-02-12MIPS: start.S: unify and simplify reset vector handlingDaniel Schwierzeck
Adopt reset vector handling from Yamon. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2013-02-12MIPS: start.S: remove obsolete 64 bit handling in setup_c0_statusDaniel Schwierzeck
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2013-02-12MIPS: xburst: fix broken access to global_dataDaniel Schwierzeck
Fix access to global_data which is broken since commits: commit 035cbe99cd2fd4adf9d7fd95aeebb5f814e37eb9 Author: Simon Glass <sjg@chromium.org> Date: Thu Dec 13 20:49:08 2012 +0000 mips: Move per_clk and dev_clk to arch_global_data Move these field into arch_global_data and tidy up. The other CONFIG_JZSOC fields are used by various architectures, so just remove the #ifdef bracketing for these. Signed-off-by: Simon Glass <sjg@chromium.org> commit 582601da2f90b1850aa19f7820b1623c79b3dac6 Author: Simon Glass <sjg@chromium.org> Date: Thu Dec 13 20:48:35 2012 +0000 arm: Move lastinc to arch_global_data Move this field into arch_global_data and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org> commit 66ee69234795c0596f84b25f06b7fbc2e8ed214c Author: Simon Glass <sjg@chromium.org> Date: Thu Dec 13 20:48:34 2012 +0000 arm: Move tbl to arch_global_data Move this field into arch_global_data and tidy up. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Xiangfu Liu <xiangfu@openmobilefree.net>
2013-02-12am335x_evm: Fix CPSW ethernet on GP EVM and EVM-SKTom Rini
In commit cfd4ff6 we implemented part of advisory 1.0.10 (internal delay for RGMII mode not supported). This in turn however requires that we set the tx clock delay feature in the PHY itself. Signed-off-by: Tom Rini <trini@ti.com>
2013-02-12i.MX6Q: mx6qsabre*: Configure to allow CONFIG_SYS_ALT_MEMTESTEric Nelson
In order to use the more thorough memory test, the macro CONFIG_SYS_MEMTEST_SCRATCH must be defined with a usable address. Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
2013-02-12mx23evk: Turn on cachesFabio Estevam
It is safe to turn on data and instruction caches for mx23. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-02-12mx23evk: Remove CONFIG_SYS_BAUDRATE_TABLEFabio Estevam
The baudrate is already defined by CONFIG_BAUDRATE and there is no need to keep CONFIG_SYS_BAUDRATE_TABLE. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Otavio Salvador <otavio@ossystems.com.br>
2013-02-12build: imx: Fix 'u-boot.imx' build without full OBJTREE referenceOtavio Salvador
When calling 'make u-boot.imx' the build were failing as it were expecting the full path for the file; this regression has been included by commit 71a988a (imximage.cfg: run files through C preprocessor). The direct references for u-boot.imx were replaced by $(obj) as config.mk handles the proper setting of it making it set to $(OBJTREE) when required. The build has been test using: - ./MAKEALL -s mx5 -s mx6 - make u-boot.imx - make O=/tmp/build Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
2013-02-12Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini
2013-02-12mx6: Disable Power Down Bit of watchdogFabio Estevam
On a mx6qsabresd revision C board with rev1.2 mx6q, the system gets resetted and it is not able to reach the Linux prompt. Comparing the watchdog behaviour on a revB versus revC board: - On a mx6qsabresd revB: U-Boot > reset resetting ... U-Boot 2013.01-10524-g432a3aa-dirty (Feb 07 2013 - 13:34:46) CPU: Freescale i.MX6Q rev1.1 at 792 MHz Reset cause: WDOG ... - On a mx6qsabresd revC: U-Boot > reset resetting ... U-Boot 2013.01-10524-g432a3aa-dirty (Feb 07 2013 - 13:34:46) CPU: Freescale i.MX6Q rev1.1 at 792 MHz Reset cause: POR So due to revC POR/watchdog circuitry whenever a watchdog occurs, it causes a POR. Clearing the PDE - Power Down Enable bit of WMCR registers fixes the problem and is also safe for all mx6 boards. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Otavio Salvador <otavio@ossystems.com.br> Acked-by: Stefano Babic <sbabic@denx.de>
2013-02-12imx: mx6q DDR3 init: Benefit from available CL = 7Benoît Thébaudeau
All the users of mx6q_4x_mt41j128.cfg (DDR3-1333H Micron MT41J128M16HA-15E or SK hynix H5TQ2G63BFR-H9C for i.MX6Q SABRE Lite, and DDR3-1600K Micron MT41K128M16JT-125:K for i.MX6 SABRE SD) support the optional down binning to DDR3-1066F (CL = 7, CWL = 6), which is possible at 532 MHz, so use it. In these conditions: tRCD(min) = 13.125 ns tRP(min) = 13.125 ns tRC(min) = max(tRAS(min, DDR3-1333H), tRAS(min, DDR3-1600K)) + tRP(min) tRAS(min, DDR3-1333H) = 36 ns tRAS(min, DDR3-1600K) = 35 ns MMDC1_MDCFG0.tCL should be set to 7 nCK, encoded as 0x4 in the bit-field MMDC1_MDCFG0[3:0]. MR0.CL should be set as in MMDC1_MDCFG0.tCL, i.e. to 7 nCK, which is encoded as 0x6 in MRS.LMR.MR0.{A6:A4, A2} and MMDC1_MDSCR[22:20, 18]. MMDC1_MDCFG1.tCWL should be set to 6 nCK, encoded as 0x4 in the bit-field MMDC1_MDCFG1[2:0]. MMDC1_MDCFG1.tRCD should be set to 13.125 ns, which is 7 nCK at 532 MHz, encoded as 0x6 in the bit-field MMDC1_MDCFG1[31:29]. MMDC1_MDCFG1.tRP should be set to 13.125 ns, which is 7 nCK at 532 MHz, encoded as 0x6 in the bit-field MMDC1_MDCFG1[28:26]. MMDC1_MDCFG1.tRC should be set to 49.125 ns, which is 27 nCK at 532 MHz, encoded as 0x1A in the bit-field MMDC1_MDCFG1[25:21]. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-02-12imx: mx6q DDR3 init: Fix MR0.PPDBenoît Thébaudeau
MR0.PPD should be set as in MMDCx_MDPDC.SLOW_PD, i.e. to fast-exit mode, which is encoded as 1 in MRS.LMR.MR0.A12 and MMDCx_MDSCR[28]. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-02-12imx: mx6q DDR3 init: Fix RST_to_CKEBenoît Thébaudeau
MMDC1_MDOR.RST_to_CKE should be set to 500 µs according to the JEDEC specification for DDR3. With a cycle of 15.258 µs, this gives 33 cycles encoded as 0x23 for the bit-field MMDC1_MDOR[5:0]. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-02-12imx: mx6q DDR3 init: Fix SDE_to_RSTBenoît Thébaudeau
MMDC1_MDOR.SDE_to_RST should be set to 200 µs according to the JEDEC specification for DDR3. With a cycle of 15.258 µs, this gives 14 cycles encoded as 0x10 for the bit-field MMDC1_MDOR[13:8]. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-02-12imx: mx6q DDR3 init: Fix tXPRBenoît Thébaudeau
MMDC1_MDOR.tXPR should be set as specified for the JEDEC DDR3 timing tXPR. For all DDR3 speed bins: tXPR(min) = max(5 nCK, tRFC(min) + 10 ns) tRFC(2 Gb) = 160 ns All the users of mx6q_4x_mt41j128.cfg have a 2-Gb density (Micron MT41J128M16HA-15E or SK hynix H5TQ2G63BFR-H9C for i.MX6Q SABRE Lite, and Micron MT41K128M16JT-125:K for i.MX6 SABRE SD). Hence, MMDC1_MDOR.tXPR should be set to max(5 nCK, 170 ns), which is 170 ns and 91 nCK at 532 MHz, encoded as 0x5A in the bit-field MMDC1_MDOR[23:16]. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-02-12imx: mx6q DDR3 init: Fix tMRDBenoît Thébaudeau
MMDC1_MDCFG1.tMRD should be set to max(tMRD, tMOD) for DDR3. For all DDR3 speed bins: tMRD(min) = 4 nCK tMOD(min) = max(12 nCK, 15 ns) Hence, MMDC1_MDCFG1.tMRD should be set to max(12 nCK, 15 ns), which is 12 nCK at 532 MHz, encoded as 0xB in the bit-field MMDC1_MDCFG1[8:5]. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Tested-by: Eric Nelson <eric.nelson@boundarydevices.com>
2013-02-11arm: fix CONFIG_DELAY_ENVIRONMENT to act like it claims in the READMELucas Stach
No one expects to end up in a delayed environment if CONFIG_DELAY_ENVIRONMENT isn't defined. Signed-off-by: Lucas Stach <dev@lynxeye.de> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Allen Martin <amartin@nvidia.com>
2013-02-11Tegra114: Add/enable Dalmore build (T114 reference board)Tom Warren
This build is stripped down. It boots to the command prompt. GPIO is the only peripheral supported. Others TBD. Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-02-11Tegra114: Add generic Tegra114 build supportTom Warren
This patch adds basic Tegra114 (T114) build support - no specific board is targeted. Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-02-11Tegra114: Dalmore: Add DT filesTom Warren
These are stripped down for bringup, They'll be filled out later to match-up with the kernel DT contents, and/or as devices are brought up (mmc, usb, spi, etc.). Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-02-11Tegra114: Add common CPU (shared) filesTom Warren
These files are used by both SPL and main U-Boot. Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-02-11Tegra114: Add CPU (armv7) filesTom Warren
These files are for code that runs on the CPU (A15) on T114 boards. At this time, there is no A15-specific code here. As T114-specific run-time code is added, it'll go here. Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-02-11Tegra114: Add AVP (arm720t) filesTom Warren
This provides SPL support for T114 boards - AVP early init, plus CPU (A15) init/jump to main U-Boot. Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-02-11Tegra114: Add arch-tegra114 include filesTom Warren
Common Tegra files are in arch-tegra, shared between T20/T30/T114. Tegra114-specific headers are in arch-tegra114. Note that some of these will be filled in as more T114 support is added (drivers, WB/LP0 support, etc.). Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
2013-02-11tegra: cardhu: config: enable SPIAllen Martin
Turn on SPI in cardhu config file Signed-off-by: Allen Martin <amartin@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-02-11tegra: add SPI SLINK driverAllen Martin
Add driver for tegra SPI "SLINK" style driver. This controller is similar to the tegra20 SPI "SFLASH" controller. The difference is that the SLINK controller is a genernal purpose SPI controller and the SFLASH controller is special purpose and can only talk to FLASH devices. In addition there are potentially many instances of an SLINK controller on tegra and only a single instance of SFLASH. Tegra20 is currently ths only version of tegra that instantiates an SFLASH controller. This driver supports basic PIO mode of operation and is configurable (CONFIG_OF_CONTROL) to be driven off devicetree bindings. Up to 4 devices per controller may be attached, although typically only a single chip select line is exposed from tegra per controller so in reality this is usually limited to 1. To enable this driver, use CONFIG_TEGRA_SLINK Signed-off-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-02-11tegra: add addresses of SPI SLINK controllersAllen Martin
Add I/O addresses of SPI SLINK controllers 1-6 Signed-off-by: Allen Martin <amartin@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-02-11tegra30: fdt: add SPI SLINK nodesAllen Martin
Add tegra30 SPI SLINK nodes to fdt. Signed-off-by: Allen Martin <amartin@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-02-11tegra30: add SBC1 to periph id mapping tableAllen Martin
SBC1 is SPI controller 1 on tegra30 Signed-off-by: Allen Martin <amartin@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
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