summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2020-05-04configs: P5040DS: enable DM_I2CBiwen Li
This enable DM_I2C in P5040DS defconfigs, except P5040DS SECURE_BOOT defconfigs Signed-off-by: Biwen Li <biwen.li@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-05-04dm: powerpc: P5040DS: add i2c DM supportBiwen Li
This supports i2c DM for board P5040DS Signed-off-by: Biwen Li <biwen.li@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-05-04powerpc: create dts component of i2c to build up an SoCBiwen Li
Provide a common i2c components that we can utilize to build up the various device tree. Signed-off-by: Biwen Li <biwen.li@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-05-04rtc: pt7c4338: Add driver model supportBiwen Li
Add support of driver model of pt7c4338 Signed-off-by: Biwen Li <biwen.li@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-05-04rtc: ds1337: Add driver model supportBiwen Li
Add support of driver model of ds1337 Signed-off-by: Biwen Li <biwen.li@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-05-01Merge branch '2020-05-01-master-imports'Tom Rini
- Assorted bug fixes - Framework for enabling D-CACHE in SPL on ARM
2020-05-01.readthedocs.yml: fix type docs/Heinrich Schuchardt
Out documentation directory is doc/ and not docs/. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-05-01actions: Fix syntax for enabling SYS_RELOC_GD_ENV_ADDRTom Rini
The correct syntax is 'select SYS_...' and not 'select CONFIG_SYS...' Fixes: d5c819b885c2 ("actions: Move defconfig options to Kconfig") Signed-off-by: Tom Rini <trini@konsulko.com>
2020-05-01common/board_r: Drop initr_bedbug wrapperOvidiu Panait
Drop initr_bedbug wrapper and call bedbug_init directly during the init sequence. Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-05-01cmd/bedbug.c: Make bedbug_init have a return valueOvidiu Panait
Do this as a preparation for removing initr_bedbug wrapper from common/board_r.c. Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-05-01common/board_r: arm: Merge initr_enable_interrupts into interrupts_initOvidiu Panait
initr_enable_interrupts() is an ARM-specific wrapper over enable_interrupts(), which is run during the common init sequence. It can be eliminated by moving the enable_interrupts() call to the end of interrupt_init() function, in arch/arm/lib/interrupts*.c. Signed-off-by: Ovidiu Panait <ovpanait@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-05-01malloc: dlmalloc: add an ability for the malloc to be re-init/init multiple ↵Marek Bykowski
times Malloc gets initialized with a call to mem_malloc_init() with the address the allocation starts to and its size. Currently it is not possible to move the malloc from one memory area to another as the malloc would eventually fail. This patch adds in the ability to re-init the malloc with the updated start address and the size. One of the use cases of this feature is SPL U-Boot running from within the static memory and calling to malloc init from within board_init_f(): arch/arm/cpu/armv8/start.S:reset vector arch/arm/cpu/armv8/start.S:main() arch/arm/lib/crt0_64.S:board_init_f() board/<my_board>/common/spl.c:board_init_f() board/<my_board>/common/spl.c:mem_malloc_init((ulong)CONFIG_SYS_SPL_MALLOC_START, CONFIG_SYS_SPL_MALLOC_SIZE); Shortly after the DDR (main) memory is init and ready we call to malloc init again but this time with the start address in the DDR memory and a much greater size for moving the allocation off the static to the DDR memory: board/<my_board>/common/spl.c:mem_malloc_init((ulong)CONFIG_SPL_MALLOC_OFFSET, CONFIG_SPL_MALLOC_SIZE); Where CONFIG_SYS_SPL_MALLOC_START and CONFIG_SPL_MALLOC_OFFSET are the start addresses of the malloc in the static and DDR memories respectively and CONFIG_SYS_SPL_MALLOC_SIZE=SZ_16K and CONFIG_SPL_MALLOC_SIZE=SZ_2M are the sizes of the mallocs in these memories. Note, now we have a much greater memory, enlarging from 16K to 2M, available for allocation. There is an alternative approach already existing in U-Boot with the use of an early (simplified) malloc and the proper (dlamalloc) malloc however necessitating managing the two mallocs whereas this approach proposes using a single dlmalloc. Signed-off-by: Marek Bykowski <marek.bykowski@gmail.com>
2020-05-01rsa: sig: fix config signature check for fit with paddingPhilippe Reynes
The signature check on config node is broken on fit with padding. To compute the signature for config node, U-Boot compute the signature on all properties of requested node for this config, except for the property "data". But, when padding is used for binary in a fit, there isn't a property "data" but two properties: "data-offset" and "data-size". So to fix the check of signature, we also don't use the properties "data-offset" and "data-size" when checking the signature on config node. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2020-05-01test/py: vboot: add a test to check fit signature on fit with paddingPhilippe Reynes
The pytest vboot does all his tests on fit without padding. We add the same tests on fit with padding. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2020-05-01hush: avoid NULL check before free()Heinrich Schuchardt
free() checks if its argument is NULL. Don't duplicate this in the calling code. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-05-01fs: ext4: avoid NULL check before free()Heinrich Schuchardt
free() checks if its argument is NULL. Don't duplicate this in the calling code. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-05-01cmd/gpt: avoid NULL check before free()Heinrich Schuchardt
free() checks if its argument is NULL. Do not duplicate this in the calling code. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
2020-05-01tools/fit-image: print a warning when cmd-line for dtc might be truncatedSven Roederer
Signed-off-by: Sven Roederer <devel-sven@geroedel.de>
2020-05-01tools/mkimage: fix handling long filenamesSven Roederer
The cmdline for calling the dtc was cut-off when using long filenames (e.g. 245 bytes) for output-file and datafile of "-f" parameter. For FIT-images cmd[MKIMAGE_MAX_DTC_CMDLINE_LEN] is declared (hardcoded 512 bytes), and contains some static values, the path of a tmpfile and a datafile. tmpfile is max MKIMAGE_MAX_TMPFILE_LEN (256) and datafile might be also this size. Having two very long pathname results in a truncation os the executed shell command, as the truncated datafile path will not be found. Redefine MKIMAGE_MAX_DTC_CMDLINE_LEN to "2 * MKIMAGE_MAX_TMPFILE_LEN + 35 for the parameters. This likely applies to the "-d" parameter, too. Signed-off-by: Sven Roederer <devel-sven@geroedel.de>
2020-05-01arm: enable distro boot for bananapi-r2Matthias Brugger
This patch enables distro boot for the bananapi-r2, based on a MediaTek mt7623n. Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2020-05-01watchdog MediaTek add upstream compatibleMatthias Brugger
The upstream compatible is called mt6589-wdt. Add this compatible to the driver. Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2020-05-01timer MediaTek use upstream compatibleMatthias Brugger
The timers compatible string in upstream is called mt6577-timer. Add this compatible to the driver. Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2020-05-01doc: describe the analysis of crash dumpsHeinrich Schuchardt
Provide an overview of the analysis of U-Boot crash dumps. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2020-05-01rtc: pcf2127: don't add/subtract 1 to tm_monRasmus Villemoes
As noted in rtc_def.h, the tm_mon field in struct rtc_time is 1-12, unlike in struct tm where it is 0-11. Currently, running "date" prints the wrong Date: 2020-04-01 (Friday) Time: 13:05:30 and setting the RTC via the date command is also broken. Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2020-05-01arm: caches: manage phys_addr_t overflow in mmu_set_region_dcache_behaviourPatrick Delaunay
Solved the overflow on phys_addr_t type for start + size in mmu_set_region_dcache_behaviour() function. This overflow is avoided by dividing start and end by 2 before addition, and we only expecting that start and size are even. This patch doesn't change the current function behavior if the parameters (start or size) are not aligned on MMU_SECTION_SIZE. For example, this overflow occurs on ARM32 with: start = 0xC0000000 and size = 0x40000000 then start + size = 0x100000000 and end = 0x0. For information the function behavior change with risk of regression, if we just shift start and size before the addition. Example with 2MB section size: MMU_SECTION_SIZE 0x200000 and MMU_SECTION_SHIFT = 21 with start = 0x1000000, size = 0x1000000, - with the proposed patch, start = 0 and end = 0x1 as previously - with the more simple patch: end = (start >> MMU_SECTION_SHIFT) + (size >> MMU_SECTION_SHIFT) the value of end change: start >> 21 = 0, size >> 21 = 0 and end = 0x0 !!! Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-05-01arm: caches: add DCACHE_DEFAULT_OPTIONPatrick Delaunay
Add the new flags DCACHE_DEFAULT_OPTION to define the default option to use according the compilation flags CONFIG_SYS_ARM_CACHE_*. This new compilation flag allows to simplify dram_bank_mmu_setup() and can be used as third parameter (option=dcache option to select) of mmu_set_region_dcache_behaviour function. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-05-01arm: caches: protect dram_bank_mmu_setup access to bi_dramPatrick Delaunay
Add protection in dram_bank_mmu_setup() to avoid access to bd->bi_dram before relocation. This patch allow to use the generic weak function dram_bank_mmu_setup to activate the MMU and the data cache in SPL or in U-Boot before relocation, when bd->bi_dram is not yet initialized. In this cases, the MMU must be initialized explicitly with mmu_set_region_dcache_behaviour function. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-05-01configs: migrate CONFIG_SYS_ARM_CACHE_* in KconfigPatrick Delaunay
Move CONFIG_SYS_ARM_CACHE_WRITETHROUGH and CONFIG_SYS_ARM_CACHE_WRITEALLOC into Kconfig done by moveconfig.py. Kconfig uses a choice between the 3 values supported in U-Boot, including the new configuration CONFIG_SYS_ARM_CACHE_WRITEBACK (the default configuration). The patch also avoids to select simultaneously 2 configurations. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-05-01tiny-printf: Support %iMarek Vasut
The most basic printf("%i", value) formating string was missing, add it for the sake of convenience. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de>
2020-04-30Merge https://gitlab.denx.de/u-boot/custodians/u-boot-spiTom Rini
- distro boot support for SPI flash - sifive spi flash driver
2020-04-30Merge tag 'efi-2020-07-rc2' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-efi Pull request for UEFI sub-system for efi-2020-07-rc2 This pull request contains bug fixes needed due to the merged changes for EFI secure boot. Patches are supplied to identify EFI system partitions.
2020-04-30sifive: fu540: Enable spi-nor flash supportJagan Teki
HiFive Unleashed A00 support is25wp256 spi-nor flash, So enable the same and add test result log for future reference. Tested on SiFive FU540 board. Thanks to Sagar for various use cases and tests. [QUAD mode in dt with spi-tx-bus-width: <4>] pp opcode = 0x34 [QUAD MODE] read opcode = 0x6c [QUAD MODE] erase opcode = 0x21 SPI-NOR: 1. erase entire flash: Pass 2. write entire flash: Pass 3. read entire flash: Pass 4. cmp 32MiB read back data: Pass 5. MMC: Booted Linux and dtb from mmc [SPI MODE in dt with spi-tx-bus-width: <1>] pp opcode = 0x12 [SPI MODE] read opcode = 0xc [SPI MODE] erase opcode = 0x21 SPI-NOR: 1. erase entire flash: Pass 2. write entire flash: Pass 3. read entire flash: Pass 4. cmp 32MiB read back data: Pass 5. MMC: Booted Linux and dtb from mmc Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Sagar Kadam <sagar.kadam@sifive.com>
2020-04-30riscv: dts: hifive-unleashed-a00: Add -u-boot.dtsiJagan Teki
Add U-Boot specific dts file for hifive-unleashed-a00, this would help to add u-boot specific properties and other node changes without touching the base dts(i) files which are easy to sync from Linux. Added spi2 alias for qspi2 as an initial u-boot specific property change. spi probing in current dm model is very much rely on aliases numbering. Even though the qspi2 can't come under any associated spi nor flash it would require to specify the same to make proper binding happen for other spi slaves. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Sagar Kadam <sagar.kadam@sifive.com>
2020-04-30spi: sifive: Fix QPP transferJagan Teki
The guessed reason is that the existing logic of filling tx fifo with data, rx fifo with NULL for tx transfer and filling rx fifo with data, tx fifo with NULL for rx transfer is not clear enough to support the Quad Page Program.     SiFive SPI controllers have specific sets of watermark registers and SPI I/O directions bits in order to program SPI controllers clear enough to support all sets of operating modes.     Here is the exact programing sequence that would follow on this patch and tested via SPI-NOR and MMC_SPI.     - set the frame format proto, endian - set the frame format dir, set it for tx and clear it for rx - TX transfer:   fill tx fifo with data.   wait for TX watermark bit to clear. - RX transfer:   fill tx fifo with 0xff.   write nbytes to rx watermark register   wait for rx watermark bit to clear.   read the rx fifo data. So, this patch adopts this program sequence and fixes the existing I/O direction bit. Cc: Vignesh R <vigneshr@ti.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Sagar Kadam <sagar.kadam@sifive.com>
2020-04-30spi: sifive: Fix format register proto fieldJagan Teki
SiFive SPI controller has a proto bit field in frame format register which would be used to configure the SPI I/O protocol lines used on specific transfer.  Right now the driver is configuring this proto using slave->mode, for all types of transctions. This makes the driver unable to function since the proto needs to configure dynamically for each and every transaction separately at runtime. Now, the controller driver supports per transfer via spi-mem exec_opo, so add the fmt_proto flag and fill the per transfer buswidth so that the controller configures the proto bit at runtime. This patch fixes the SPI controller works with SPI NOR flash on quad read with page program. Cc: Vignesh R <vigneshr@ti.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Sagar Kadam <sagar.kadam@sifive.com>
2020-04-30spi: sifive: Add spi-mem exec opJagan Teki
SiFive SPI controller is responsible to handle the slave devices like mmc spi and spi nor flash. The controller is designed such a way that it would handle the slave transactions based on the I/O protocol numbers, example if spi nor slave send quad write opcode it has to send alone with I/O protocol number of 4 and if it try to send data it has to send I/O protocol number along with 4 line data. But the current spi-xfer code from spi-mem is combining the opcode and address in a single transaction, so the SPI controller will be unable to identify the I/O protocol number of opcode vs address. So, add the spi-mem exec_op with spi-xfer of opcode, address and data as a separate transaction. This doesn't remove the .xfer of dm_spi_ops since mmc spi will make use of it. Note: This code might have moved to the spi-mem core area once we have done the dedicated tests on other controllers and have real reason to move. Cc: Vignesh R <vigneshr@ti.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Sagar Kadam <sagar.kadam@sifive.com>
2020-04-30mtd: spi-nor-ids: Add Spansion s25fs512s flash entryKuldeep Singh
Spansion "s25fs512s" flash is incorrectly decoded as "s25fl512s" on various platforms as former is not present. Add the entry. Linux already has both the flashes present. A snippet below: { "s25fl512s", INFO6(0x010220, 0x4d0080, 256 * 1024, 256...}, { "s25fs512s", INFO6(0x010220, 0x4d0081, 256 * 1024, 256...}, Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-04-30watchdog: kconfig: Enable designware for rk3399Jagan Teki
Enable designware watchdog driver for rk3399 if WDT defined. Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-04-30mtd: spi-nor-ids: Enable 4B_OPCODES for is25wp256Jagan Teki
IS25WP256 flash chips do support 4byte address opcodes, so enable support for it. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Sagar Kadam <sagar.kadam@sifive.com>
2020-04-30mtd: spi-nor: Enable QE bit for ISSI flashJagan Teki
Enable QE bit for ISSI flash chips. QE enablement logic is similar to what Macronix has, so reuse the existing code itself. Cc: Sagar Shrikant Kadam <sagar.kadam@sifive.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2020-04-30spi: sifive: Tidy up dm_spi_slave_platdata variableJagan Teki
Usually variable name slave is used for spi_slave structure and slave_plat for the dm_spi_slave_platdata. Let's follow this meaningful notation by replacing slave with slave_plat for dm_spi_slave_platdata structure. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-04-30rk3399: Enable SF distro bootcmdJagan Teki
Enable SPI flash(SF) distro boot command in rk3399. This distro boot will read the boot script at specific location at the flash and start sourcing the same. Included the SF device at the last of the target devices list since all the rest of the devices on the list have more possibility to boot the distribution due to the size of the SPI flash is concern. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-04-30Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86Tom Rini
- DM ACPI support (Part A) - Improve support for chain-loading x86 U-Boot
2020-04-30Merge tag 'xilinx-for-v2020.07-rc2' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2020.07-rc2 mmc: - Fix dt property handling via generic function clk: - Fix versal watchdog clock setting nand: - Fix zynq nand command comparison xilinx: - Enable ubifs - Sync board_late_init configurations with initrd_high setup - Make custom distro boot more verbose zynq: - Kconfig alignments - Fix nand cse configuration zynqmp: - Fix zcu104 low level qspi configuration - Small DT updates Signed-off-by: Tom Rini <trini@konsulko.com>
2020-04-30Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriqTom Rini
- Add DM_ETH support for DPAA1, DPAA2 based RDB platforms: ls1046ardb, ls1043ardb, lx2160ardb, ls2088ardb, ls1088ardb. - Add GICv3 support for ls1028a, ls2088a, ls1088a. - Add lpuart support on ls1028aqds. - Few bug fixes and updates on ls2088a, ls1012a, ls1046a, ls1021a based platforms.
2020-04-30x86: Add documentation for the chain-load featureSimon Glass
Add a few notes about this feature, which is aimed for development. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-04-30x86: Use the existing stack when chain-loadingSimon Glass
With chromebook_coral we normally run TPL->SPL->U-Boot. This is the 'bare metal' case. When running from coreboot we put u-boot.bin in the RW_LEGACY portion of the image, e.g. with: cbfstool image-coral.serial.bin add-flat-binary -r RW_LEGACY \ -f /tmp/b/chromebook_coral/u-boot.bin -n altfw/u-boot \ -c lzma -l 0x1110000 -e 0x1110000 In this case U-Boot is run from coreboot (actually Depthcharge, its payload) so we cannot access CAR. Use the existing stack instead. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-04-30x86: Add a way to detect running from corebootSimon Glass
If U-Boot is running from coreboot we need to skip low-level init. Add an way to detect this and to set the gd flag. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-04-30x86: Move coreboot-table detection into common codeSimon Glass
To support detecting booting from coreboot, move the code which locates the coreboot tables into a common place. Adjust the algorithm slightly to use a word comparison instead of string, since it is faster. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the comments to 960KB] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2020-04-30board: Add a gd flag for chain loadingSimon Glass
When U-Boot is run from another boot loader, much of the low-level init needs to be skipped. Add a flag for this and adjust ll_boot_init() to use it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
generated by cgit (git 2.34.1) at 2024-12-23 23:04:54 +0000