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2018-01-15board/ls2081ard: Correct code to get QMAP value in checkboardPriyanka Jain
QMAP value contains information about QSPI chip-selects. These bits are used to display information of boot device in checkboard() function. QMAP value is stored in most significant 3-bits of 8-bit register brdcfg[0] in Qixis, this patch corrects code to get QMAP bits using below logic: (brdcfg[0] >> 5) & 0x7 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-01-15board/ls2081ardb: Update board related printsPriyanka Jain
Remove Board Arch print as its value is always constant '1' and does not contain any important information to display during boot. Add print to display Board FPGA version. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-01-15configs: SECURE_BOOT: Enable CONFIG_CMD_EXT4_WRITESumit Garg
As part of chain of trust with confidentiality along with distro boot, linux kernel image needs to be stored in encrypted form on ext4 boot partition. So enable CONFIG_CMD_EXT4_WRITE in case of Secure boot on ARM based platforms. Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-01-15armv8/ls1088a: configure PMU's PCTBENR to enable WDTZhang Ying-22455
The SP805-WDT module on LS1088A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-01-15serial: lpuart: Proper device identificationSriram Dash
Identify and distinguish between platform device type of MX7ULP and LS1021A. This is a fix to commit 7edf5c45("serial: lpuart: add i.MX7ULP support"). Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Acked-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-01-15board: ls1012a: LS1012A-2G5RDB board supportBhaskar Upadhaya
LS1012A-2G5RDB belongs to LS1012A family with features 2 2.5G SGMII PFE MAC, SATA, USB 2.0/3.0, WiFi DDR, eMMC, QuadSPI, UART. Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-01-15armv8/kconfig: Align boards of same family at one placeBhaskar Upadhaya
Align boards belonging to LS1012A, LS2080A SoC at one place. Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-01-14Merge git://git.denx.de/u-boot-mmcTom Rini
2018-01-12Merge git://git.denx.de/u-boot-tegraTom Rini
2018-01-12Makefile: ensure DTB doesn't overflow into initial stackStephen Warren
With CONFIG_SYS_INIT_SP_BSS_OFFSET enabled, the initial (pre-relocation) stack is placed some distance after bss_start. The control DTB is appended to the U-Boot binary at bss_start. If the DTB is too large, or the SP BSS offset too small, then the initial stack could corrupt the DTB. Enhance the Makefile to check whether this is likely to occur. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2018-01-12ARM: Tegra: p2771-0000: use calculate env var featureStephen Warren
Request that all environment variables containing hard-coded address be calculated at boot time instead. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2018-01-12ARM: Tegra186: calculate load addresses at bootStephen Warren
In the presence of potentially fragemented memory, we cannot hard-code addresses into environment variables such as kernel_addr_r. Instead, we must calculate those addresses at run-time based on available memory locations. Implement the code to perform such runtime calculation, based on requirements described in environment variables, to allow the user full control over the allocation. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2018-01-12ARM: Tegra186: don't map memory not in RAM banksStephen Warren
Tegra186 currently restricts its DRAM usage to entries in the /memory node in the DTB passed to it. However, the MMU configuration always maps the entire first 2GB of RAM. This could allow the CPU to speculatively access RAM that isn't part of the in-use banks. This patch switches to runtime construction of the table that's used to construct the MMU translation tables, and thus prevents access to RAM that's not part of a valid bank. Note: This patch is intended to prevent access to RAM regions which U-Boot does not need to access, with the primary purpose of avoiding theoretical speculative access to physical regions for which the HW will throw errors (e.g. carve-outs that the CPU has no permission to access at a bus level, bad ECC pages, etc.). In particular, this patch is not deliberately related to the speculation-related security issues that were recently announced. The apparent similarity is a coincidence. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2018-01-12ARM: tegra: p2771-000: increase max DRAM bank countStephen Warren
On this platform, there may be up to 1024 unusable chunks of memory. Increase CONFIG_NR_DRAM_BANKS so that U-Boot can remember all the banks required to represent such fragmented memory. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2018-01-12ARM: Tegra186: search for best RAM bankStephen Warren
In the future, the list of DRAM regions passed to U-Boot in the DTB may be quite long and fragmented. Due to this, U-Boot must search through the regions to find the best region to relocate into, rather than relying on the current assumption that the top of bank 0 is a reasonable relocation target. This change implements such searching. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2018-01-12ARM: bootm: don't assume sp is in DRAM bank 0Stephen Warren
arch_lmb_reserve() currently assumes that the stack pointer is within DRAM bank 0. This is not necessarily true. Enhance the code to search through DRAM banks until the bank that does contain SP is found, and then reserve the tail of that bank. Fixes: 2d1916e48bd8 ("ARM: add flat device tree support") Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2018-01-12ARM: Tegra186: mem parsing fixes from downstreamStephen Warren
Apply a few small fixes for the DTB /memory node parsing from NVIDIA's downstream U-Boot: - Allow arbitrary number of DRAM banks. - Correctly calculate the number of DRAM banks. - Clip PCIe memory in the same way as U-Boot CPU memory use. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2018-01-12ARM: tegra: use LINUX_KERNEL_IMAGE_HEADERStephen Warren
Enable CONFIG_LINUX_KERNEL_IMAGE_HEADER for all 64-bit Tegra boards. cboot (the boot SW that runs before U-Boot) will eventually use this information. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2018-01-12ARMv8: add optional Linux kernel image headerStephen Warren
Allow placing a Linux kernel image header at the start of the U-Boot binary. This is useful since the image header reports the amount of memory (BSS and similar) that U-Boot needs to use, but that isn't part of the binary size. This can be used by the code that loads U-Boot into memory to determine where to load U-Boot, based on other users of memory. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2018-01-12ARM: tegra: use CONFIG_SYS_INIT_SP_BSS_OFFSETStephen Warren
Enable CONFIG_SYS_INIT_SP_BSS_OFFSET for all 64-bit Tegra boards. Place the stack/... 512KiB from the end of the U-Boot binary. This should be plenty to accommodate the current DTBs (max 64 KiB), early malloc region (6KiB), stack usage, and plenty of slack, while still not placing it too far away from the U-Boot binary. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2018-01-12ARMv8: Allow dynamic early stack pointerStephen Warren
U-Boot typically uses a hard-coded value for the stack pointer before relocation. Implement option SYS_INIT_SP_BSS_OFFSET to instead calculate the initial SP at run-time. This is useful to avoid hard-coding addresses into U-Boot, so that can be loaded and executed at arbitrary addresses and thus avoid using arbitrary addresses at runtime. This option's value is the offset added to &_bss_start in order to calculate the stack pointer. This offset should be large enough so that the early malloc region, global data (gd), and early stack usage do not overlap any appended DTB. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2018-01-12ARM: tegra: remove SPL config for non-SPL SoCsStephen Warren
No 64-bit Tegra uses SPL. Remove various unused definitions from config headers. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2018-01-12ARM: tegra: don't use CONFIG_SPL_TEXT_BASE when no SPLStephen Warren
64-bit Tegra don't use SPL, and soon won't define CONFIG_SPL_TEXT_BASE when building. Fix the binman .dts file so that it doesn't use undefined values. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
2018-01-13mmc: fsl_esdhc: Fix eMMC 1.8v setting issuePeng Fan
Current USDHC driver will reset VSELECT to 0 (3.3v) during mmc init, then set to 1 for 1.8v eMMC I/O. When booting from eMMC, since ROM has already set VSELECT to 1.8v before running the u-boot. This reset in USDHC driver causes a short 2.2v pulse on CMD pin. Fix this issue by not reset VSELECT to 0 when 1.8v flag is set. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2018-01-13power: Rearrange code to guard power command with CONFIG_SPL_BUILD guardTom Rini
In order to discard this code when unused in SPL we need to guard the command with a check for CONFIG_SPL_BUILD and we rearrange the code slightly to make this cleaner. Cc: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Tom Rini <trini@konsulko.com>
2018-01-12travis.yml: Support RISC-VRick Chen
Enable travis-ci support with a link having built. Signed-off-by: Chih-Mao Chen <cmchen@andestech.com> Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com>
2018-01-12riscv: doc: Add relative doc to describe RISC-VRick Chen
Add documents to describe NX25 and AE250. Also update other documents for RISC-V. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com>
2018-01-12riscv: Modify generic codes to support RISC-VRick Chen
Support common commands bdinfo and image format, also modify common generic flow for RISC-V. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2018-01-12riscv: Support standaloneRick Chen
Run hello_world successfully. U-Boot 2018.01-rc2-00033-gb265b91-dirty (Dec 22 2017 - 13:54:21 +0800) DRAM: 1 GiB MMC: mmc@f0e00000: 0 SF: Detected mx25u1635e with page size 256 Bytes, erase size 4 KiB, total 2 MiB In: serial@f0300000 Out: serial@f0300000 Err: serial@f0300000 Net: Warning: mac@e0100000 (eth0) using random MAC address - 0a:47:9b:f8:b4:f2 eth0: mac@e0100000 RISC-V # mmc rescan RISC-V # fatls mmc 0:1 318907 u-boot-ae250-64.bin 1252 hello_world_ae250_32.bin 328787 u-boot-ae250-32.bin 3 file(s), 0 dir(s) RISC-V # fatload mmc 0:1 0x600000 hello_world_ae250_32.bin reading hello_world_ae250_32.bin 1252 bytes read in 23 ms (52.7 KiB/s) RISC-V # go 0x600000 Example expects ABI version 9 Actual U-Boot ABI version 9 Hello World argc = 1 argv[0] = "0x600000" argv[1] = "$B@" Hit any key to exit ... RISC-V # Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com>
2018-01-12riscv: tools: Prelink u-bootRick Chen
Add prelink-riscv to arrange .rela.dyn and .rela.got in compile time. So that u-boot can be directly executed without fixup. Signed-off-by: Chih-Mao Chen <cmchen@andestech.com> Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com>
2018-01-12riscv: defconfig: Add nx25-ae250 defconfig to support RISC-VRick Chen
Add nx25-ae250 default configuration for RISC-V Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com>
2018-01-12riscv: configs: Add nx25-ae250.h to support RISC-VRick Chen
Add nx25-ae250 board configuartion options for RISC-V Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com>
2018-01-12riscv: board: Add nx25-ae250 to support RISC-VRick Chen
Add nx25-ae250 board to do platform initializations. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com>
2018-01-12riscv: Add Kconfig to support RISC-VRick Chen
Add Kconfig and makefile for RISC-V Also modify MAINTAINERS for it. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com> Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>
2018-01-12riscv: nx25: include: Add header files to support RISC-VRick Chen
Add header files for RISC-V. Cache, ptregs, data type and other definitions are included. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com>
2018-01-12riscv: nx25: dts: Add AE250 dts to support RISC-VRick Chen
AE250 is the Soc using NX25 cpu core base on RISC-V arch. Details please see the doc/README.ae250. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com>
2018-01-12riscv: nx25: lib: Add relative lib funcs to support RISC-VRick Chen
Add makefile, interrupts.c and boot.c,... functions to support RISC-V arch. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com> Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>
2018-01-12riscv: cpu: Add nx25 to support RISC-VRick Chen
Add Andes nx25 cpu core (called AndesStar V5) to support RISC-V arch Verifications: 1. startup and relocation ok. 2. boot from rom or ram both ok. 2. timer driver ok. 3. uart driver ok 4. mmc driver ok 5. spi driver ok. 6. 32/64 bit both ok. Detail verification message please see doc/README.ae250. Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Signed-off-by: Greentime Hu <green.hu@gmail.com> Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>
2018-01-12mmc: remove hc_wp_grp_size from struct mmc if not neededJean-Jacques Hiblot
hc_wp_grp_size is needed only if hardware partitionning is used. On ARM removing it saves about 30 bytes of code space. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-01-12mmc: don't read the size of eMMC enhanced user data area in SPLJean-Jacques Hiblot
This information is only used by the "mmc info" command. On ARM removing this information from SPL saves about 140 of code space. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-01-12mmc: compile out erase and write mmc commands if write operations are not ↵Jean-Jacques Hiblot
enabled Also remove erase_grp_size and write_bl_len from struct mmc as they are not used anymore. On ARM, removing them saves about 100 bytes of code space in SPL. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-01-12mmc: read ssr only if MMC write support is enabledJean-Jacques Hiblot
The content of ssr is useful only for erase operations. on ARM, removing sd_read_ssr() saves around 300 bytes. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-01-12mmc: add a Kconfig option to enable the support for MMC write operationsJean-Jacques Hiblot
This allows using CONFIG_IS_ENABLED(MMC_WRITE) to compile out code needed only if write support is required. The option is added for u-boot and for SPL Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-01-12mmc: reworked version lookup in mmc_startup_v4Jean-Jacques Hiblot
Using a table versus a switch() structure saves a bit of space Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-01-12mmc: compile out more code if support for UHS and HS200 is not enabledJean-Jacques Hiblot
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-01-12mmc: atmel: when sending a data command, use the provided block sizeJean-Jacques Hiblot
struct mmc_data contains the block size to use for the data transfer. Use this information instead of using the default value or the block length information stored in struct mmc. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-01-12common: do not compile common fastboot code when building the SPLJean-Jacques Hiblot
This is not required as fastboot can't be started from SPL. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2018-01-12am335x_hs_evm: Trim options in SPL to reduce binary sizeTom Rini
The am335x_hs_evm runs into size constraint problems at times with various toolchains as changes come in due to the config have a large number of options in SPL (to showcase what is possible) while also having rather constrained binary limits. Gain some of this room back by lowering the loglevel, disabling HW partition support and switching over to the tiny FIT image support. Cc: Andrew F. Davis <afd@ti.com> Signed-off-by: Tom Rini <trini@konsulko.com> --- I'd really appreciate a run-time test of this patch if at all possible as I'm a little worried about TINY_FIT being incompatible with all of the security options. Thanks!
2018-01-12dm: mmc: sandbox: Update SD card emulationJean-Jacques Hiblot
The SDcard initialization procedure does a few more things than it did earlier: * switch the bus width even for 1-bit bus width * check that speed has been properly set (in resp[4] of SD_CMD_SWITCH_FUNC) Update the SD simulator to handle those requests gracefully. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2018-01-12configs: omapl138_lcdk: decrease the loglevel to reduce the size of the SPLJean-Jacques Hiblot
The changes in the MMC stack have increased its footprint up to the point were its breaks the generation of the SPL for this platform. Fix this by reducing the loglevel. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Peter Howard <phoward@gme.net.au>
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