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every compilation shows this error
Hack for sunxi which doesn't have a proper binman definition for
64-bit boards
not only for sunxi-boards/arm64
fix this by changing to real comments
Fixes: 9f55ee259d0c ("Makefile: sunxi: Don't use binman to build ATF image")
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
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https://gitlab.denx.de/u-boot/custodians/u-boot-ti
- Added support for J7200 evm
- DM_ETH and DM_USB migrations for omap3
- USB DFU and mass storage support for AM65x evm
- RTI watchdog support for K3 devices
- Fix an issue with L3 cache on K3 devices
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Enable CPSW2G port to support networking in U-Boot
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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Add MCU NAVSS, UDMA and CPSW2G DT nodes.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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J7200 SoM has Cypress HyperFlash connected to HyperBus interface, add DT
entries for the same.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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Add wkup_gpio0 node required for detecting whether board mux is set
HyperFlash.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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On J7200 SoC OSPI0 and HypeFlash are muxed at HW level and only one of
them can be used at any time. J7200 EVM has both HyperFlash and OSPI
flash on board. There is a user switch (SW3.1) that can be toggled to
select OSPI flash vs HyperFlash.
Read the state of this switch via wkup_gpio0_6 line and fixup the DT
nodes to select OSPI0 vs HyperFlash
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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Add USB related DT entries to enable USB device mode.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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Add initial A72 defconfig support.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
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Add initial R5 defconfig support
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
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Add the basic a72 basic dts for j7200. Following nodes were supported:
- UART
- MMC SD
- I2C
- TISCI communication
- LPDDR with 1600MTs configuration.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
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Add the basic a72 dts for j7200. Following nodes were supported:
- UART
- MMC SD
- I2C
- TISCI communication
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Vishal Mahaveer <vishalm@ti.com>
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
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Add device identification for J7200 SoC
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Suman Anna <s-anna@ti.com>
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k3-j721e ddr driver sanity checks for product id and version number.
Version number gets changed for every minor update in the IP. So discard
the version check and just sanity check for product id.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
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Add board detection support for j7200 common processor board.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Reviewed-by: Suman Anna <s-anna@ti.com>
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j7200-evm has minor differences with j721e-evm based on the IPs
available in the SoC. Introduce separate build targets for j7200-evm
to incorporate the differences.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Suman Anna <s-anna@ti.com>
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Detect if sysfw is already loaded by ROM and pass this information to
sysfw loader. Based on this information sysfw loader either loads the
sysfw image from boot media or just receives the boot notification
message form sysfw.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Suman Anna <s-anna@ti.com>
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Starting J7200 SoC, ROM supports for loading sysfw directly from boot
image. ROM passes this information on number of images that are loaded
to bootloader at certain location. Add support for storing this
information before it gets corrupted.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Suman Anna <s-anna@ti.com>
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The J7200 SoC is a part of the K3 Multicore SoC architecture platform.
It is targeted for automotive gateway, vehicle compute systems,
Vehicle-to-Vehicle (V2V) and Vehicle-to-Everything (V2X) applications.
The SoC aims to meet the complex processing needs of modern embedded
products.
Some highlights of this SoC are:
* Dual Cortex-A72s in a single cluster, two clusters of lockstep
capable dual Cortex-R5F MCUs and a Centralized Device Management and
Security Controller (DMSC).
* Configurable L3 Cache and IO-coherent architecture with high data
throughput capable distributed DMA architecture under NAVSS.
* Integrated Ethernet switch supporting up to a total of 4 external ports
in addition to legacy Ethernet switch of up to 2 ports.
* Upto 1 PCIe-GEN3 controller, 1 USB3.0 Dual-role device subsystems,
20 MCANs, 3 McASP, eMMC and SD, OSPI/HyperBus memory controller, I3C and
I2C, eCAP/eQEP, eHRPWM among other peripherals.
* One hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL
management.
See J7200 Technical Reference Manual (SPRUIU1, June 2020)
for further details: https://www.ti.com/lit/pdf/spruiu1
Add support for detection J7200 SoC
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
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In main control mmr there is no partition 4 and partition 6 is available
only on J721e. Fix the same in ctrl_mmr_unlock function
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Suman Anna <s-anna@ti.com>
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Add an api soc_is_j721e(), and use it to enable certain functionality
that is available only on j721e. This detection is needed when DT is not
available.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
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Starting J7200 SoC, ROM supports for loading sysfw directly from boot
image. In such cases, SPL need not load sysfw from boot media, but need
to receive boot notification message from sysfw. So separate out
remoteproc calls for system controller from sysfw loader and just
receive the boot notification if sysfw is already loaded.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Suman Anna <s-anna@ti.com>
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mmr_unlock api is common for all k3 devices. Move it to a common
location.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Suman Anna <s-anna@ti.com>
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If SPL_MULTI_DTB_FIT is not enabled, then CONFIG_SPL_OF_LIST is not defined
And in turn tispl.bin ends up not embedding any DTB.
Fixing it by using CONFIG_DEFAULT_DEVICE_TREE if SPL_OF_LIST is empty.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
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The DT nodes on J721E SoCs currently use a node name "interconnect" for
the various interconnects. This name is not following the DT schema, and
should simply be "bus". Update the fdt fixup logic to use both the current
and the expected corrected path names so that this logic won't be broken
with newer kernels.
Signed-off-by: Suman Anna <s-anna@ti.com>
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Guard all eeprom probe with TI_I2C_BOARD_DETECT to avoid reading eeprom
when eeprom is not available
Reviewed-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
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Current usage of eeprom apis produce a build failure when
CONFIG_TI_I2C_BOARD_DETECT is not defined. Add stub function for these
apis to avoid build failures.
Reviewed-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
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Because of space constraints, create a new USB defconfig for R5 to
faciliate booting from USB mass storage devices
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
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Because of space constraints, create a new USB defconfig for R5 to
faciliate booting in USB peripheral (DFU) bootmode
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
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Enable configs to facilitate booting from USB Mass Storage devices
as well as USB peripheral boot
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
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Add offset and environment related configs used for booting
from DFU.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
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Add nodes for USB0 in SPL to enable USB host boot mode
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
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Add USB0 nodes and set them to host mode to support USB host and
peripheral boot modes
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
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Add support for identifying USB host and device boot modes
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
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U-boot only supports either USB host or device mode for a node at a
time in dts. To support both host and dfu bootmodes, set "peripheral"
as the default dr_mode but fixup property to "host" if host bootmode
is detected.
This needs to happen before the dwc3 generic layer binds the usb device
to a host or device driver. Therefore, add an fdtdec_setup_board()
implementation to fixup the dt based on the boot mode.
Also use the same fixup function to set the USB-PCIe Serdes mux to PCIe
in both the host and device cases. This is required for accessing the
interface at USB 2.0 speeds.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
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config
Gate mmc related system related configurations with DM_MMC to avoid build
errors when MMC is not enabled
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
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Add support for loading system firmware from a USB mass storage device
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
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In order to be able to use things like file system drivers early on in
SPL (before relocation) in a memory-constrained environment when DDR is
not yet available we cannot use the simple malloc scheme which does not
implement the freeing of previously allocated memory blocks. To address
this issue go ahead and enable the use of the full malloc by manually
initializing the required functionality inside board_init_f by creating
a full malloc pool inside the pre-relocation malloc pool.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
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usb_init() may be called multiple times for fetching multiple images
from SPL. Skip reinitializing USB if its already been done
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
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Create a new API spl_usb_load() that takes the filename as a parameter
instead of taking the default U-boot PAYLOAD_NAME
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
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The DT nodes on AM65x SoCs currently use a node name "interconnect" for
the various interconnects. This name is not following the DT schema, and
should simply be "bus". Update the fdt fixup logic to use both the
current and the expected corrected path names so that this logic won't
be broken with newer kernels.
The logic also corrects the crypto node name as the DT node
unit-addresses are all expected to be lower case.
Signed-off-by: Suman Anna <s-anna@ti.com>
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The hardcoded array size leads to array overflows with changes in
speed modes enum in mmc core. Use MMC_MODES_END for otap_del_sel
array declaration to fix this.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
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The various CBASS interconnect nodes on K3 J721E SoCs are defined
using the node name "interconnect". This is not a valid node name
as per the dt-schema. Fix these node names to use the standard name
used for SoC interconnects, "bus".
Signed-off-by: Suman Anna <s-anna@ti.com>
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The various CBASS interconnect nodes on K3 AM65x SoCs are defined
using the node name "interconnect". This is not a valid node name
as per the dt-schema. Fix these node names to use the standard name
used for SoC interconnects, "bus".
Signed-off-by: Suman Anna <s-anna@ti.com>
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This commit completes the migrations for DM_ETH and DM_USB. The board
is now consistent with omap3_beagle and other remaining OMAP3 boards.
Cc: Tom Rini <trini@konsulko.com>
Cc: Adam Ford <aford173@gmail.com>
Signed-off-by: Derald D. Woods <woods.technical@gmail.com>
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https://gitlab.denx.de/u-boot/custodians/u-boot-efi
Pull request for UEFI sub-system for efi-2020-10-rc3
Bugs in the UEFI sub-system are fixed:
* use the optional data of the BootXXXX variables as load options
* simplify function public_key_verify_signature()
* amend a copyright notice
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When switching on or off the ARM caches some care must be taken to ensure
existing cache line allocations are not left in an inconsistent state.
An example of this is when cache lines are considered non-shared by
and L3 controller even though the lines are shared. To prevent these
and other issues all cache lines should be cleared before enabling
or disabling a coherent master's cache. ARM cores and many L3 controllers
provide a way to efficiently clean out all cache lines to allow for
this, unfortunately there is no such easy way to do this on current K3
MSMC based systems.
We could explicitly clean out every valid external address tracked by
MSMC (all of DRAM), or we could attempt to identify only the set of
addresses accessed by a given boot stage and flush only those
specifically. This patch attempts the latter. We start with cleaning the
SPL load address. More addresses can be added here later as they are
identified.
Note that we perform a flush operation for both the flush and invalidate
operations, this is not a typo. We do this to avoid the situation that
some ARM cores will promote an invalidate to a clean+invalidate, but only
emit the invalidation operation externally, leading to a loss of data.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Tested-by: Faiz Abbas <faiz_abbas@ti.com>
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Add DT entries for main domain watchdog0 and 1 instances on the J721e
well as RTI1-based watchdog on the AM65x. RTI0 does not work for this
purpose on the AM65x, so leave it out.
On AM65x, we mark the power-domain as shared because RTI firmware such
as https://github.com/siemens/k3-rti-wdt may request it as well in order
to prevent accidental shutdown of the watchdog.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
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This is based on the Linux kernel driver for the RTI watchdog.
To actually reset the system on an AM65x, it requires firmware running
on the R5 that accepts the NMI and issues the actual system reset via
TISCI. Kind of an iTCO, except that this watchdog hardware has support
for no-way-out, and only for that.
On the J721E, reset works without extra firmware help when routing the
RTI interrupt via the ESM.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
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Signed-off-by: Tom Rini <trini@konsulko.com>
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