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2011-07-04cpuat91: use atmel_usartAndreas Bießmann
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Cc: Eric Bénard <eric@eukrea.com>
2011-07-04eb_cpux9k2: use atmel_usartAndreas Bießmann
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> CC: Jens Scharsig <js_at_ng@scharsoft.de> Acked-by: Jens Scharsig<js_at_ng@scharsoft.de> Tested-by: Jens Scharsig<js_at_ng@scharsoft.de> (for eb_cpux9k2 board)
2011-07-04at91rm9200ek: use atmel_usartAndreas Bießmann
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2011-07-04arm920t/at91: add at91rm9200_devices.cAndreas Bießmann
This is a copy of arm926ejs/at91 api for perpherial initialisation. At the moment we just need the usart part of the api. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2011-07-04arm920t/at91: use new clock.c featuresAndreas Bießmann
This patch enables the new clock features from arm920t/at91/clock.c. This is an required step to get at91rm9200_usart replaced by atmel_usart driver. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Cc: Jens Scharsig <js_at_ng@scharsoft.de> Cc: Eric Bénard <eric@eukrea.com>
2011-07-04arm920t/at91: add clock.cAndreas Bießmann
This patch adds an copy of arm926ejs/at91/clock.c to arm920t/at91. The arm926ejs specialities are removed from arm920t version and vice versa. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2011-07-04at91rm9200.h: fix ATMEL_PMX_AA_TXD2Andreas Bießmann
This patch sets the ATMEL_PMX_AA_TXD2 to the correct value. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> CC: Jens Scharsig <js_at_ng@scharsoft.de> CC: eric@eukrea.com Acked-by: Eric Bénard <eric@eukrea.com>
2011-07-04vision2: Fix build due to WEIM registers name changeFabio Estevam
commit 0015de1a (MX5: Make the weim structure complete) fixed the name for the WEIM registers in order to match with the MX51/MX53 manuals. Fix the WEIM register for vision2 board so that it can build again. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2011-07-04MX53: Add initial support for MX53ARDFabio Estevam
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2011-07-04MX5: Introduce a function for setting the chip select sizeFabio Estevam
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2011-07-04MX5: Add iomux structureFabio Estevam
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2011-07-04MX5: Make the weim structure completeFabio Estevam
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2011-07-04arm: Update jadecpu boardMatthias Weisser
Enable dcache and arch memset/memcpy for speed reasons Remove of config.mk and some environment overwrites Some generic cleanup Signed-off-by: Matthias Weisser <weisserm@arcor.de>
2011-07-04arm: omap2: apollon: fix broken buildIgor Grinberg
Define CONFIG_SYS_SDRAM_BASE to physical SDRAM address and CONFIG_SYS_INIT_SP_ADDR to physical SRAM address Signed-off-by: Igor Grinberg <grinberg@compulab.co.il> Cc: Kyungmin Park <kyungmin.park@samsung.com>
2011-07-04OMAP[34]: fix broken timerJohn Rigby
As implemented now the timer used to implement __udelay counts to 0xffffffff and then gets stuck there because the the programmed reload value is 0xffffffff. This value is not only wrong but illegal according to the reference manual. One can reproduce the bug by leaving a board at the u-boot prompt for sometime then issuing a sleep command. The sleep will hang forever. The timer is a count up timer that reloads as it rolls over from 0xffffffff so the correct load value is 0. Change TIMER_LOAD_VAL from 0xffffffff to 0 and introduce a new constant called TIMER_OVERFLOW_VAL set to 0xffffffff. Signed-off-by: John Rigby <john.rigby@linaro.org> Tested-by: Igor Grinberg <grinberg@compulab.co.il>
2011-07-04arm: Tegra2: GPIO: enable GPIO for Tegra2 boardsTom Warren
Signed-off-by: Tom Warren <twarren@nvidia.com>
2011-07-04GPIO: Tegra2: add GPIO driver for Tegra2Tom Warren
Signed-off-by: Tom Warren <twarren@nvidia.com>
2011-07-04VCMA9: various cleanups/code style fixesDavid Müller (ELSOFT AG)
Signed-off-by: David Müller <d.mueller@elsoft.ch>
2011-07-04VCMA9: use CFI driver (and remove the old one)David Müller (ELSOFT AG)
Signed-off-by: David Müller <d.mueller@elsoft.ch>
2011-07-04VCMA9: remove unneeded config.mkDavid Müller (ELSOFT AG)
Signed-off-by: David Müller <d.mueller@elsoft.ch>
2011-07-04armv7: adapt s5pc1xx to the new cache maintenance frameworkAneesh V
adapt s5pc1xx to the new layered cache maintenance framework Signed-off-by: Aneesh V <aneesh@ti.com>
2011-07-04armv7: adapt omap3 to the new cache maintenance frameworkAneesh V
adapt omap3 to the new layered cache maintenance framework Signed-off-by: Aneesh V <aneesh@ti.com>
2011-07-04armv7: adapt omap4 to the new cache maintenance frameworkAneesh V
adapt omap4 to the new layered cache maintenance framework Signed-off-by: Aneesh V <aneesh@ti.com>
2011-07-04armv7: add PL310 support to u-bootAneesh V
PL310 is the L2$ controller from ARM used in many SoCs including the Cortex-A9 based OMAP4430 Add support for some of the key PL310 operations - Invalidate all - Invalidate range - Flush(clean & invalidate) all - Flush range Signed-off-by: Aneesh V <aneesh@ti.com>
2011-07-04arm: minor fixes for cache and mmu handlingAneesh V
1. make sure that page table setup is not done multiple times 2. flush_dcache_all() is more appropriate while disabling cache than a range flush on the entire memory(flush_cache()) Provide a default implementation for flush_dcache_all() for backward compatibility and to avoid build issues. Signed-off-by: Aneesh V <aneesh@ti.com>
2011-07-04armv7: integrate cache maintenance supportAneesh V
- Enable I-cache on bootup - Enable MMU and D-cache immediately after relocation - Do necessary initialization before enabling d-cache and MMU - Changes to cleanup_before_linux() - Make changes according to the new framework Signed-off-by: Aneesh V <aneesh@ti.com>
2011-07-04armv7: rename cache related CONFIG flagsAneesh V
Replace the cache related CONFIG flags with more meaningful names. Following are the changes: CONFIG_L2_OFF -> CONFIG_SYS_L2CACHE_OFF CONFIG_SYS_NO_ICACHE -> CONFIG_SYS_ICACHE_OFF CONFIG_SYS_NO_DCACHE -> CONFIG_SYS_DCACHE_OFF Signed-off-by: Aneesh V <aneesh@ti.com> V2: * Changed CONFIG_L2_OFF -> CONFIG_SYS_NO_L2CACHE V4: * Changed all three flags to the final names suggested as above and accordingly changed the commit message
2011-07-04armv7: cache maintenance operations for armv7Aneesh V
- Add a framework for layered cache maintenance - separate out SOC specific outer cache maintenance from maintenance of caches known to CPU - Add generic ARMv7 cache maintenance operations that affect all caches known to ARMv7 CPUs. For instance in Cortex-A8 these opertions will affect both L1 and L2 caches. In Cortex-A9 these will affect only L1 cache - D-cache operations supported: - Invalidate entire D-cache - Invalidate D-cache range - Flush(clean & invalidate) entire D-cache - Flush D-cache range - I-cache operations supported: - Invalidate entire I-cache - Add maintenance functions for TLB, branch predictor array etc. - Enable -march=armv7-a so that armv7 assembly instructions can be used Signed-off-by: Aneesh V <aneesh@ti.com>
2011-07-04arm: make default implementation of cache_flush() weakly linkedAneesh V
make default implementation of cache_flush() weakly linked so that sub-architectures can override it Signed-off-by: Aneesh V <aneesh@ti.com>
2011-07-01Makefile: need to remove generated u-boot-nand_spl.ldsKumar Gala
On MPC85xx based NAND_SPL builds we generate a u-boot-nand_spl.lds based on output from preprocessor. We where never removed it. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Scott Wood <scottwood@freescale.com>
2011-07-01NAND: Add 16bit NAND support for the NDFCAlex Waterman
This patch adds support for 16 bit NAND devices attached to the NDFC on ppc4xx processors. Two config entries were added: CONFIG_SYS_NDFC_16 - Setting this tells the NDFC that a 16 bit device is attached. CONFIG_SYS_NDFC_EBC0_CFG - This is for the External Bus Controller configuration register. Also, a new ndfc_read_byte() function was added which does not first convert the data to little endian. The NAND SPL was also modified to do 16bit bad block testing when a 16 bit chip is being used. Signed-off-by: Alex Waterman <awaterman@dawning.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
2011-07-01cmd_nand: add nand write.trimffs commandBen Gardiner
Add another nand write. variant, trimffs. This command will request of nand_write_skip_bad() that all trailing all-0xff pages will be dropped from eraseblocks when they are written to flash as-per the reccommended behaviour of the UBI FAQ [1]. The function that implements this timming is the drop_ffs() function by Artem Bityutskiy, ported from the mtd-utils tree. [1] http://www.linux-mtd.infradead.org/doc/ubi.html#L_flasher_algo Signed-off-by: Ben Gardiner <bengardiner@nanometrics.ca> CC: Artem Bityutskiy <dedekind1@gmail.com> CC: Detlev Zundel <dzu@denx.de> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
2011-07-01nand_util: drop trailing all-0xff pages if requestedBen Gardiner
Add a flag to nand_read_skip_bad() such that if true, any trailing pages in an eraseblock whose contents are entirely 0xff will be dropped. The implementation is via a new drop_ffs() function which is based on the function of the same name from the ubiformat utility by Artem Bityutskiy. This is as-per the reccomendations of the UBI FAQ [1] [1] http://www.linux-mtd.infradead.org/doc/ubi.html#L_flasher_algo Signed-off-by: Ben Gardiner <bengardiner@nanometrics.ca> CC: Artem Bityutskiy <dedekind1@gmail.com> Acked-by: Detlev Zundel <dzu@denx.de> CC: Scott Wood <scottwood@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
2011-07-01nand_util: treat WITH_YAFFS_OOB as a modeBen Gardiner
When specified in the flags argument of nand_write, WITH_YAFFS_OOB causes an operation which is mutually exclusive with the 'usual' way of writing. Add a check that client code does not specify WITH_YAFFS_OOB along with any other flags and add a comment indicating that the WITH_YAFFS_OOB flag should not be mixed with other flags. Signed-off-by: Ben Gardiner <bengardiner@nanometrics.ca> CC: Scott Wood <scottwood@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
2011-07-01nand_util: convert nand_write_skip_bad() to flagsBen Gardiner
In a future commit the behaviour of nand_write_skip_bad() will be further extended. Convert the only flag currently passed to the nand_write_ skip_bad() function to a bitfield of only one allocated member. This should avoid an explosion of int's at the end of the parameter list or the ambiguous calls like nand_write_skip_bad(info, offset, len, buf, 0, 1, 1); nand_write_skip_bad(info, offset, len, buf, 0, 1, 0); Instead there will be: nand_write_skip_bad(info, offset, len, buf, WITH_YAFFS_OOB | WITH_OTHER); Signed-off-by: Ben Gardiner <bengardiner@nanometrics.ca> Acked-by: Detlev Zundel <dzu@denx.de> Signed-off-by: Scott Wood <scottwood@freescale.com>
2011-07-01nand_base: trivial: fix comment read/write commentBen Gardiner
Replace an incorrect 'read' with 'write' in a comment. Signed-off-by: Ben Gardiner <bengardiner@nanometrics.ca> Acked-by: Detlev Zundel <dzu@denx.de> Signed-off-by: Scott Wood <scottwood@freescale.com>
2011-07-01Merge branch 'next' of git://git.denx.de/u-boot-niosWolfgang Denk
* 'next' of git://git.denx.de/u-boot-nios: nios2: move generic config to boards.cfg
2011-06-30nios2: move generic config to boards.cfgMike Frysinger
I can't build test this, but just looking at the config files written and it seems OK ... Tested-by: Thomas Chou <thomas@wytron.com.tw> Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Scott McNutt <smcnutt@psyent.com>
2011-06-29cfi_flash: reverse geometry for newer STM partsMike Frysinger
For newer STM parts where CFI >= 1.1, there is a byte in the extended structure that declares the flash layout type (just like the AMD parts), so key off of that to find out when we need to reverse the geometry. This can be seen with M29W640 parts where U-Boot does: Bank # 1: CFI conformant FLASH (16 x 16) Size: 8 MB in 135 Sectors AMD Standard command set, Manufacturer ID: 0x20, Device ID: 0x22ED Erase timeout: 8192 ms, write timeout: 1 ms Buffer write timeout: 1 ms, buffer size: 16 bytes Sector Start Addresses: 20000000 RO 20002000 RO 20004000 RO 20006000 RO 20008000 RO 2000A000 RO 2000C000 RO 2000E000 RO 20010000 RO 20020000 RO ... But Linux does: physmap platform flash device: 00800000 at 20000000 physmap-flash.0: Found 1 x16 devices at 0x0 in 16-bit bank. Manufacturer ID 0x000020 Chip ID 0x0022ed physmap-flash.0: Swapping erase regions for top-boot CFI table. Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Stefan Roese <sr@denx.de>
2011-06-27Prepare v2011.06Wolfgang Denk
Signed-off-by: Wolfgang Denk <wd@denx.de>
2011-06-27Minor coding style fixes.Wolfgang Denk
Signed-off-by: Wolfgang Denk <wd@denx.de>
2011-06-25usb: convert to partial linkingMike Frysinger
Looks like this was missed during the conversion to partial linking. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-06-25ehci-pci: Fix PCI EHCI driver for 36-bitZhao Chenhui
Convert the PCI base address into a virtual address. Signed-off-by: Zhao Chenhui <b35336@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com>
2011-06-25musb: process control messages after roothub accepted itCliff Cai
When dealing with non-multipoint devices, if the software root hub code accepted the message, then we still need to process it normally. So only return quickly when the root hub skipped the message or is otherwise in an error state. Signed-off-by: Cliff Cai <cliff.cai@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2011-06-23Merge branch 'master' of git://git.denx.de/u-boot-armWolfgang Denk
* 'master' of git://git.denx.de/u-boot-arm: run arm_pci_init after relocation IXP42x PCI rewrite update/fix PDNB3 board update/fix IXDP425 / IXDPG425 boards add dvlhost (dLAN 200 AV Wireless G) board IXP NPE: add support for fixed-speed MII ports update/fix AcTux4 board update/fix AcTux3 board update/fix AcTux2 board update/fix AcTux1 board use -ffunction-sections / --gc-sections on IXP42x support CONFIG_SYS_LDSCRIPT on ARM fix "depend" target in npe directory Fix IXP code to work after relocation was added trigger hardware watchdog in IXP42x serial driver add support for IXP42x Rev. B1 and newer add XScale sub architecture (IXP/PXA) to maintainer list Conflicts: arch/arm/lib/board.c Signed-off-by: Wolfgang Denk <wd@denx.de>
2011-06-23run arm_pci_init after relocationMichael Schwingen
Signed-off-by: Michael Schwingen <michael@schwingen.org>
2011-06-23IXP42x PCI rewriteMichael Schwingen
clean up IXP PCI handling: get rid of IXP-private bus scan, BAR assign etc. code and use u-boot's PCI infrastructure instead. Move board-specific PCI setup code (clock/reset) to board directory. Signed-off-by: Michael Schwingen <michael@schwingen.org>
2011-06-23update/fix PDNB3 boardMichael Schwingen
Signed-off-by: Michael Schwingen <michael@schwingen.org>
2011-06-23update/fix IXDP425 / IXDPG425 boardsMichael Schwingen
Signed-off-by: Michael Schwingen <michael@schwingen.org>
2011-06-23add dvlhost (dLAN 200 AV Wireless G) boardMichael Schwingen
Signed-off-by: Michael Schwingen <michael@schwingen.org>
generated by cgit (git 2.34.1) at 2024-12-28 12:13:59 +0000