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2013-05-05nand: Add SPL_NAND support to mxc_nand_splMarek Vasut
Add support for generic NAND SPL via the SPL framework into the mxc_nand_spl driver. This is basically just a simple rename and publication of the already implemented functions. To avoid the bare-bones functions getting in the way of the NAND_SPL, build them only if CONFIG_SPL_FRAMEWORK is not defined. Also make sure the requested payload is aligned to full pages, otherwise this simple driver fails to load the last page. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Scott Wood <scottwood@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Tom Rini <trini@ti.com> Acked-by: Scott Wood <scottwood@freescale.com>
2013-05-05imx: Align the imximage header and payload to multiples of 4kMarek Vasut
The MX53 ROM loads the data from NAND in multiples of pages and supports maximum page size of 4k. Thus, align the image and header to 4k to be safe from ROM bugs. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Scott Wood <scottwood@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Tom Rini <trini@ti.com>
2013-05-05mxs: spl_mem_init: Change EMI port priorityFabio Estevam
FSL bootlets code set the PORT_PRIORITY_ORDER field of register HW_EMI_CTRL as 0x2, which means: PORT0231 = 0x02 Priority Order: AXI0, AHB2, AHB3, AHB1 Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-05-05mxs: spl_mem_init: Skip the initialization of some DRAM_CTL registersFabio Estevam
HW_DRAM_CTL27, HW_DRAM_CTL28 and HW_DRAM_CTL35 are not initialized as per FSL bootlets code. mx23 Reference Manual mark HW_DRAM_CTL27 and HW_DRAM_CTL28 as "reserved". HW_DRAM_CTL8 is setup as the last element. So skip the initialization of these DRAM_CTL registers. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-05-05mxs: spl_mem_init: Remove erroneous DDR settingFabio Estevam
On mx23 there is no 'DRAM init complete' in register HW_DRAM_CTL18. Remove this erroneous setting. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-05-05mxs: spl_mem_init: Fix comment about start bitFabio Estevam
Start bit is part of HW_DRAM_CTL8 register, so fix the comment. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-05-05mx23_olinuxino: Fix DDR pin iomux settingsFabio Estevam
Change MUX_CONFIG_EMI to use the same drive strength as the bootlets code from Freescale, which results in much better stability. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-05-05mx23evk: Fix DDR pin iomux settingsFabio Estevam
Change MUX_CONFIG_EMI to use the same drive strength as the bootlets code from Freescale, which results in much better stability. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2013-05-05mx23: Fix pad voltage selection bitFabio Estevam
On mx23 the pad voltage selection bit needs to be always '0', since '1' is a reserved value. For example: Pin 108, EMI_A06 pin voltage selection: 0= 1.8V (mDDR) or 2.5V (DDR1); 1= reserved. Fix the pad voltage definitions for the mx23 case. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de>
2013-05-03P1022DS: Set CONFIG_SPL_MAX_SIZE directlyTom Rini
With the u-boot-with-spl.bin rule calling $(OBJCOPY) with CONFIG_SPL_PAD_TO, and CONFIG_SPL_PAD_TO defaulting to CONFIG_SPL_MAX_SIZE we cannot use math here, so set it to 4096 rather than 4 * 1024. Signed-off-by: Tom Rini <trini@ti.com>
2013-05-02Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini
2013-05-02powerpc/85xx: set USB2 default mode to 'device' for (super)hydra boardsShaohui Xie
The Hydra and Superhydra (P3041DS, P5020DS, and P5040DS) boards have a second USB port that can be configured in either host, peripheral (aka device), or OTG (on-the-go) mode. When configured in host mode, if the port is connected to another USB host, damage to the board can occur. To avoid this, we change the default setting to peripheral mode. Ideally, we'd set it to OTG mode, but currently there is no OTG support for these boards. Setting the hwconfig variable will also update the device tree, and so Linux will configure the port for peripheral mode as well. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Timur Tabi <timur@tabi.org> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-02powerpc/p1_p2_rdb_pc: Add a pin to reset the DDR chip for P1021RDB-PCXu Jiucheng
When P1021RDB-PC reboot system, the board will hung at uboot DDR configuration. For P1021RDB-PC DDR reset pin is multiplex with QE, so uboot will reserve this pin for QE and skip DDR reset. Other platforms without QE will do this reset. This patch adds a slight code to reset DDR chip by QE CE_PB8 pin for NAND and NOR FLASH boot. For booting from SPI FALSH and SD card, it seems possible to use the rom on chip to write to the GPIO pins before configuring the DDR. Signed-off-by: Xu Jiucheng <B37781@freescale.com> Signed-off-by: Xie Xiaobo <X.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-02powerpc/mpc85xx: Changed LIODN offset valuesCristian Sovaiala
Extending LIODN offset range from 1-5 to 1-10 While using a qman portal with a higher index the LIODN offset is incorrectly set, thus extending the range of offsets covers all 10 qman portals Signed-off-by: Cristian Sovaiala <cristian.sovaiala@freescale.com> Acked-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-02powerpc/mpc85xx: Extend workaround for erratum DDR_A003 to other SoCsYork Sun
Erratum DDR_A003 applies to P5020, P3041, P4080, P3060, P2041, P5040. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-02powerpc/p1010rdb: add readme document for p1010rdbShengzhou Liu
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-02powerpc/p1010rdb: Change flexcan compatible stringShengzhou Liu
Change flexcan compatible string from "fsl,flexcan-v1.0" to "fsl,p1010-flexcan" to match the device tree. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-02powerpc/85xx: add SerDes bank 4 lanesTimur Tabi
Only some chips have four SerDes banks, so don't define lanes for a bank that doesn't exist. Signed-off-by: Timur Tabi <timur@tabi.org> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-02qoriq/p1_p2_rdb_pc: USB device-tree fixups for P1020Zhicheng Fan
Resolve P1020 second USB controller multiplexing with eLBC - mandatory to mention USB2 in hwconfig string to select it over eLBC, otherwise USB2 node is removed - works only for SPI and SD boot Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Zhicheng Fan <B32736@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-02doc/ramboot.mpc85xx: Documented the RAMBOOT for MPC85xxPoonam Aggrwal
There could be scenarios where the user would like to manually(via JTAG) configure the DDR/L2SRAM and load the bootloader binary onto DDR/L2SRAM. This document explains thse usecases and the detailed explanation of what needs to be done to use it. Most of the code from CONFIG_SYS_RAMBOOT will be used except for small changes of CCSRBAR etc. The changes are not very large, but it is good to document them so that user can get it working at once. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-02powerpc/mpc85xx:IFC Errata A003399 is not valid for BSC913xPrabhakar Kushwaha
As per Errata list of BSC9131 and BSC9132, IFC Errata A003399 is no more valid. So donot compile its workaround. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-02mpc85xx: Fix a compiler warning when CONFIG_WATCHDOG is turned onHorst Kronstorfer
cpu.c:288:2: warning: implicit declaration of function 'reset_85xx_watchdog' [-Wimplicit-function-declaration] Signed-off-by: Horst Kronstorfer <hkronsto@frequentis.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-02powerpc/85xx: Add workaround for errata USB-14 (enable on P204x/P3041/P50x0)Xulei
On P204x/P304x/P50x0 Rev1.0, USB transmit will result in false internal multi-bit ECC errors, which has impact on performance, so software should disable all ECC reporting from USB1 and USB2. In formal release document, the errata number should be USB14 instead of USB138. Signed-off-by: xulei <Lei.Xu@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: xulei <B33228@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-02powerpc/b4860qds: Add the tlb entries for SRIO interfacesLiu Gang
Add the tlb entries based on the configuration of the SRIO interfaces. Every SRIO interface has 256M space: #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-02fman/mEMAC: set SETSP bit in IF_MODE regisgter for RGMII speedZang Roy-R61911
Some legacy RGMII phys don't have in band signaling for the speed information. so set the RGMII MAC mode according to the speed got from PHY. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Reported-by: John Traill <john.traill@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-02powerpc/mpc85xx: set clock-frequency for T4/B4 clockgen nodeTang Yuantian
For T4/B4, the clockgen node compatible string is updated to version 2. Add clock-frequency setting for this new version. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-02powerpc/b4860: Adding workaround errata A-005871Shengzhou Liu
Per the latest errata updated, B4860/B4420 Rev 1.0 has also errata A-005871, so adding define A-005871 for B4 SoCs. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-02powerpc/b4: Fix the wrong register offset of B4 PCIE moduleLiu Gang
B4420/B4860 PCIE can not work because of the wrong definition of the PCIE register offset in the file: arch/powerpc/include/asm/immap_85xx.h Add the judgement of B4420/B4860 to make the register offset to: #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x200000 Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-02powerpc/p1022ds: Add support for NAND and NAND boot using SPLMatthew McClintock
Add defines needed to access NAND, remove second flash bank that is actually connected to NAND. Add nand booting support for P1022DS with hardcoded DDR config using SPL framework from 2011 Signed-off-by: Matthew McClintock <msm@freescale.com> Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: Jiang Yutang <b14898@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-02powerpc/mpc85xx: add setting of clock-frequency for mpic nodeDongsheng.wang@freescale.com
Set the device tree property associated with the mpic source frequency. The frequency is used for mpic timer. Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-02powerpc/mpc85xx: Add revision properties in portal device tree node 'pme'Jeffrey Ladouceur
The 'fsl,pme-rev1' and 'fsl-pme-rev2' properties have been added to the pme portal node. This is required for software to determine which version of PME hardware is present and take appropriate actions. These properties are a direct reflection of the corresponding ccsr pme register value. Also removed unnecessary static global variables. Signed-off-by: Jeffrey Ladouceur <Jeffrey.Ladouceur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-02board/freescale/common/cds_pci_ft.c: Fix rotate wrong cells in interrupt-map ↵Jiang Bin
property For linux 3.x, the size of each item in interrupt-map property is 9 not 7. Don't use the static value and calculate the size with following cells: PCI #address-cells, PCI #interrupt-cells, PIC address, PIC #address-cells, PIC #interrupt-cells. Signed-off-by: Bin Jiang <bin.jiang@windriver.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-02Merge branch 'master' of git://git.denx.de/u-boot-mpc5xxxTom Rini
2013-05-02mpc5200: a3m071/a4m2k: Miscellaneous updates and fixesStefan Roese
The changes to a3m071/a4m2k in summary are: - Enable CAN1 on I2C in GPS Port Configuration - Enable SPI on PSC2 - Activate network console - New flash partitioning - Fix some typos - Pass host name to Linux - Change rootfs to squashfs,jffs2 - Enable UBI/UBIFS support - Enable FIT support Signed-off-by: Stefan Roese <sr@denx.de>
2013-05-02mpc5200: a3m071/a4m2k: Fix problem with increased global_data structStefan Roese
The v2013.04 release has this patch set included: 5cb48582 "Add architecture-specific global data" With this, the global_data struct is now common and new variables have been added. Resulting in a bigger struct. Unfortunately the currently allocated 128 bytes are just a bit too small for this new struct. This patch now uses the automatically generated struct size instead to not run into this problem again. Please note that this problem might hit some other platforms which currently reserve a tight space of 128 bytes for the global_data struct! Signed-off-by: Stefan Roese <sr@denx.de>
2013-05-02mpc5200: a3m071/a4m2k: Enable flash verify optionStefan Roese
Signed-off-by: Stefan Roese <sr@denx.de>
2013-05-02mpc512x: remove dead codeAnatolij Gustschin
The prt_mpc512x_clks() function isn't referenced anywhere and its prototype is wrong. Remove it. Signed-off-by: Anatolij Gustschin <agust@denx.de>
2013-05-01omap5_uevm: Enable redundant MMC environmentTom Rini
Cc: Sricharan R <r.sricharan@ti.com> Signed-off-by: Tom Rini <trini@ti.com>
2013-05-01mx28evk: Guard NAND-related ENV defines with CONFIG_ENV_IS_IN_NANDTom Rini
The redundancy related defines are only correct for NAND, so guard all of that area with CONFIG_ENV_IS_IN_NAND Cc: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Tom Rini <trini@ti.com>
2013-05-01env_mmc: add support for redundant environmentMichael Heimpold
This patch add support for storing the environment redundant on mmc devices. Substantially it re-uses the logic from the NAND implementation, that means using an incremental counter for marking newer data. Signed-off-by: Michael Heimpold <mhei@heimpold.de>
2013-05-01lib: consolidate hang()Andreas Bießmann
Delete all occurrences of hang() and provide a generic function. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Acked-by: Albert ARIBAUD <albert.u.boot@aribaud.net> [trini: Modify check around puts() in hang.c slightly] Signed-off-by: Tom Rini <trini@ti.com>
2013-05-01tx25: add CONFIG_SPL_LIBGENERIC_SUPPORTAndreas Bießmann
In order to use the generic hang() later on pull libgeneric in SPL. This has no impact on the SPL size. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2013-05-01mx31pdk: add CONFIG_SPL_LIBGENERIC_SUPPORTAndreas Bießmann
In order to use the generic hang() later on pull libgeneric in SPL. This has no impact on the SPL size. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2013-05-01nios2: fix style in board.c.Andreas Bießmann
Make nios2's board.c checkpatch clean. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2013-05-01microblaze: fix style in board.cAndreas Bießmann
Make microblaze's board.c checkpatch clean. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Reviewed-by: Michal Simek <monstr@monstr.eu>
2013-05-01part/dev_desc: Add log2 of blocksize to block_dev_desc data structEgbert Eich
log2 of the device block size serves as the shift value used to calculate the block number to read in file systems when implementing avaiable block sizes. It is needed quite often in file systems thus it is pre-calculated and stored in the block device descriptor. Signed-off-by: Egbert Eich <eich@suse.com>
2013-05-01fs/fat: Don't multiply fatsize with sector sizeEgbert Eich
Bugfix: Here at this place we need the fat size in sectors not bytes. This was found during code review when adding support for storage devices with blocksizes != 512. Signed-off-by: Egbert Eich <eich@suse.com>
2013-05-01disk/iso: Add Support for block sizes > 512 byte to ISO partition supportEgbert Eich
For ISO we check the block size of the device if this is != the CD sector size we assume that the device has no ISO partition. Signed-off-by: Egbert Eich <eich@suse.com>
2013-05-01disk/gpt: Fix GPT partition handling for blocksize != 512Egbert Eich
Disks beyond 2T in size use blocksizes of 4096 bytes. However a lot of code in u-boot still assumes a 512 byte blocksize. This patch fixes the handling of GPTs. Signed-off-by: Egbert Eich <eich@suse.com>
2013-05-01disk/part_dos: check harder for partition tableEgbert Eich
Devices that used to have a whole disk FAT filesystem but got then partitioned will most likely still have a FAT or FAT32 signature in the first sector as this sector does not get overwritten by a partitioning tool (otherwise the tool would risk to kill the mbr). The current partition search algorithm will erronously detects such a device as a raw FAT device. Instead of looking for the FAT or FAT32 signatures immediately we use the same algorithm as used by the Linux kernel and first check for a valid boot indicator flag on each of the 4 partitions. If the value of this flag is invalid for the first entry we then do the raw partition check. If the flag for any higher partition is wrong we assume the device is neiter a MBR nor PBR device. Signed-off-by: Egbert Eich <eich@suse.com>
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