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2020-04-30spi: sifive: Fix QPP transferJagan Teki
The guessed reason is that the existing logic of filling tx fifo with data, rx fifo with NULL for tx transfer and filling rx fifo with data, tx fifo with NULL for rx transfer is not clear enough to support the Quad Page Program.     SiFive SPI controllers have specific sets of watermark registers and SPI I/O directions bits in order to program SPI controllers clear enough to support all sets of operating modes.     Here is the exact programing sequence that would follow on this patch and tested via SPI-NOR and MMC_SPI.     - set the frame format proto, endian - set the frame format dir, set it for tx and clear it for rx - TX transfer:   fill tx fifo with data.   wait for TX watermark bit to clear. - RX transfer:   fill tx fifo with 0xff.   write nbytes to rx watermark register   wait for rx watermark bit to clear.   read the rx fifo data. So, this patch adopts this program sequence and fixes the existing I/O direction bit. Cc: Vignesh R <vigneshr@ti.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Sagar Kadam <sagar.kadam@sifive.com>
2020-04-30spi: sifive: Fix format register proto fieldJagan Teki
SiFive SPI controller has a proto bit field in frame format register which would be used to configure the SPI I/O protocol lines used on specific transfer.  Right now the driver is configuring this proto using slave->mode, for all types of transctions. This makes the driver unable to function since the proto needs to configure dynamically for each and every transaction separately at runtime. Now, the controller driver supports per transfer via spi-mem exec_opo, so add the fmt_proto flag and fill the per transfer buswidth so that the controller configures the proto bit at runtime. This patch fixes the SPI controller works with SPI NOR flash on quad read with page program. Cc: Vignesh R <vigneshr@ti.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Sagar Kadam <sagar.kadam@sifive.com>
2020-04-30spi: sifive: Add spi-mem exec opJagan Teki
SiFive SPI controller is responsible to handle the slave devices like mmc spi and spi nor flash. The controller is designed such a way that it would handle the slave transactions based on the I/O protocol numbers, example if spi nor slave send quad write opcode it has to send alone with I/O protocol number of 4 and if it try to send data it has to send I/O protocol number along with 4 line data. But the current spi-xfer code from spi-mem is combining the opcode and address in a single transaction, so the SPI controller will be unable to identify the I/O protocol number of opcode vs address. So, add the spi-mem exec_op with spi-xfer of opcode, address and data as a separate transaction. This doesn't remove the .xfer of dm_spi_ops since mmc spi will make use of it. Note: This code might have moved to the spi-mem core area once we have done the dedicated tests on other controllers and have real reason to move. Cc: Vignesh R <vigneshr@ti.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Sagar Kadam <sagar.kadam@sifive.com>
2020-04-30mtd: spi-nor-ids: Add Spansion s25fs512s flash entryKuldeep Singh
Spansion "s25fs512s" flash is incorrectly decoded as "s25fl512s" on various platforms as former is not present. Add the entry. Linux already has both the flashes present. A snippet below: { "s25fl512s", INFO6(0x010220, 0x4d0080, 256 * 1024, 256...}, { "s25fs512s", INFO6(0x010220, 0x4d0081, 256 * 1024, 256...}, Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-04-30watchdog: kconfig: Enable designware for rk3399Jagan Teki
Enable designware watchdog driver for rk3399 if WDT defined. Cc: Marek Vasut <marex@denx.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-04-30mtd: spi-nor-ids: Enable 4B_OPCODES for is25wp256Jagan Teki
IS25WP256 flash chips do support 4byte address opcodes, so enable support for it. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Sagar Kadam <sagar.kadam@sifive.com>
2020-04-30mtd: spi-nor: Enable QE bit for ISSI flashJagan Teki
Enable QE bit for ISSI flash chips. QE enablement logic is similar to what Macronix has, so reuse the existing code itself. Cc: Sagar Shrikant Kadam <sagar.kadam@sifive.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2020-04-30spi: sifive: Tidy up dm_spi_slave_platdata variableJagan Teki
Usually variable name slave is used for spi_slave structure and slave_plat for the dm_spi_slave_platdata. Let's follow this meaningful notation by replacing slave with slave_plat for dm_spi_slave_platdata structure. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-04-30rk3399: Enable SF distro bootcmdJagan Teki
Enable SPI flash(SF) distro boot command in rk3399. This distro boot will read the boot script at specific location at the flash and start sourcing the same. Included the SF device at the last of the target devices list since all the rest of the devices on the list have more possibility to boot the distribution due to the size of the SPI flash is concern. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-04-30Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86Tom Rini
- DM ACPI support (Part A) - Improve support for chain-loading x86 U-Boot
2020-04-30Merge tag 'xilinx-for-v2020.07-rc2' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2020.07-rc2 mmc: - Fix dt property handling via generic function clk: - Fix versal watchdog clock setting nand: - Fix zynq nand command comparison xilinx: - Enable ubifs - Sync board_late_init configurations with initrd_high setup - Make custom distro boot more verbose zynq: - Kconfig alignments - Fix nand cse configuration zynqmp: - Fix zcu104 low level qspi configuration - Small DT updates Signed-off-by: Tom Rini <trini@konsulko.com>
2020-04-30Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriqTom Rini
- Add DM_ETH support for DPAA1, DPAA2 based RDB platforms: ls1046ardb, ls1043ardb, lx2160ardb, ls2088ardb, ls1088ardb. - Add GICv3 support for ls1028a, ls2088a, ls1088a. - Add lpuart support on ls1028aqds. - Few bug fixes and updates on ls2088a, ls1012a, ls1046a, ls1021a based platforms.
2020-04-30x86: Add documentation for the chain-load featureSimon Glass
Add a few notes about this feature, which is aimed for development. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-04-30x86: Use the existing stack when chain-loadingSimon Glass
With chromebook_coral we normally run TPL->SPL->U-Boot. This is the 'bare metal' case. When running from coreboot we put u-boot.bin in the RW_LEGACY portion of the image, e.g. with: cbfstool image-coral.serial.bin add-flat-binary -r RW_LEGACY \ -f /tmp/b/chromebook_coral/u-boot.bin -n altfw/u-boot \ -c lzma -l 0x1110000 -e 0x1110000 In this case U-Boot is run from coreboot (actually Depthcharge, its payload) so we cannot access CAR. Use the existing stack instead. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-04-30x86: Add a way to detect running from corebootSimon Glass
If U-Boot is running from coreboot we need to skip low-level init. Add an way to detect this and to set the gd flag. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-04-30x86: Move coreboot-table detection into common codeSimon Glass
To support detecting booting from coreboot, move the code which locates the coreboot tables into a common place. Adjust the algorithm slightly to use a word comparison instead of string, since it is faster. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: correct the comments to 960KB] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2020-04-30board: Add a gd flag for chain loadingSimon Glass
When U-Boot is run from another boot loader, much of the low-level init needs to be skipped. Add a flag for this and adjust ll_boot_init() to use it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-04-30pci: Avoid auto-config when chain loadingSimon Glass
When U-Boot is not the first-stage bootloader we don't want to re-configure the PCI devices, since this has already been done. Add a check to avoid this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-04-30x86: cpu: Skip init code when chain loadingSimon Glass
When U-Boot is not the first-stage bootloader the interrupt and cache init must be skipped, as well as init for various peripherals. Update the code to add checks for this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-04-30x86: apl: Skip init code when chain loadingSimon Glass
When U-Boot is not the first-stage bootloader the FSP-S init must be skipped. Update it to add a check. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-04-30x86: fsp: Allow skipping init code when chain loadingSimon Glass
It is useful to be able to boot the same x86 image on a device with or without a first-stage bootloader. For example, with chromebook_coral, it is helpful for testing to be able to boot the same U-Boot (complete with FSP) on bare metal and from coreboot. It allows checking of things like CPU speed, comparing registers, ACPI tables and the like. When U-Boot is not the first-stage bootloader much of this code is not needed and can break booting. Add checks for this to the FSP code. Rather than checking for the amount of available SDRAM, just use 1GB in this situation, which should be safe. Using 2GB may run into a memory hole on some SoCs. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-04-30acpi: Add an acpi commandSimon Glass
It is useful to dump ACPI tables in U-Boot to see what has been generated. Add a command to handle this. To allow the command to find the tables, add a position into the global data. Support subcommands to list and dump the tables. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-04-30acpi: Move the xsdt pointer to acpi_ctxSimon Glass
Put this in the context along with the other important pointers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-04-30acpi: Put table-setup code in its own functionSimon Glass
We always write three basic tables to ACPI at the start. Move this into its own function, along with acpi_fill_header(), so we can write a test for this code. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-04-30acpi: Move acpi_add_table() to generic codeSimon Glass
Move this code to a generic location so that we can test it with sandbox. This requires adding a few new fields to acpi_ctx, so drop the local variables used in the original code. Also use mapmem to avoid pointer-to-address casts which don't work on sandbox. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-04-30acpi: Drop code for missing XSDT from acpi_write_rsdp()Simon Glass
We don't actually support tables without an XSDT so we can drop this dead code. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-04-30x86: Allow devices to write ACPI tablesSimon Glass
Call the new core function to permit devices to write their own ACPI tables. These tables will appear after all other tables. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-04-30acpi: Convert part of acpi_table to use acpi_ctxSimon Glass
The current code uses an address but a pointer would result in fewer casts. Also it repeats the alignment code in a lot of places so this would be better done in a helper function. Update write_acpi_tables() to make use of the new acpi_ctx structure, adding a few helpers to clean things up. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-04-30acpi: Add a method to write tables for a deviceSimon Glass
A device may want to write out ACPI tables to describe itself to Linux. Add a method to permit this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-04-30acpi: Add a binding for ACPI settings in the device treeSimon Glass
Devices need to report various identifiers in the ACPI tables. Rather than hard-coding these in drivers it is typically better to put them in the device tree. Add a binding file to describe this. Signed-off-by: Simon Glass <sjg@chromium.org>
2020-04-30x86: cbfs: Drop unwanted declarationSimon Glass
The intention here is add a forward declaration, not actually declare a variable. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-04-30efi_loader: fix 'efidebug bootorder'Heinrich Schuchardt
* don't copy GUIDs for no reason * shorten print format strings by using variable names * don't use the run-time table to access exported functions * check the result of malloc() (fixes Coverity CID 300331) Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-04-30efi_loader: efidebug, avoid illegal memory accessHeinrich Schuchardt
For EFI_PERSISTENT_MEMORY_TYPE the 'efidebug memmap' command produces an illegal memory access. * Add the missing descriptive string for EFI_PERSISTENT_MEMORY_TYPE. * Replace the check for EFI_MAX_MEMORY_TYPE by the ARRAY_SIZE() macro. Reported-by: Coverity (CID 300336) Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-04-30efi_loader: fix 'efidebug boot dump'Heinrich Schuchardt
* Do not recreate a variable name that we already have as u16 string. * Check the return value of malloc() * EFI_NOT_FOUND cannot occur for a variable name returned by GetNextVariableName(). Remove a print statement. * Don't copy a GUID for no reason. * Don't use the run-time service table to call exported functions. * Don't pass NULL to show_efi_boot_opt_data() (fixes Coverity CID 300338). Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-04-30MAINTAINERS: assign test/py/tests/test_efi*/ to EFI PAYLOADHeinrich Schuchardt
Some UEFI related files are not assigned currently. Add them to the EFI PAYLOAD area. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-04-30efi_loader: remove CONFIG_EFI_SECURE_BOOT in efi_loader.hAKASHI Takahiro
The guard doesn't make any difference, so remove it. Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org> Suggested-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-04-30doc/efi: rework secure boot descriptionHeinrich Schuchardt
Ensure a uniform formatting. Some rephrasing. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-04-30efi_loader: identify EFI system partitionHeinrich Schuchardt
In subsequent patches UEFI variables shalled be stored on the EFI system partition. Hence we need to identify the EFI system partition. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-04-30part: detect EFI system partitionHeinrich Schuchardt
Up to now for MBR and GPT partitions the info field 'bootable' was set to 1 if either the partition was an EFI system partition or the bootable flag was set. Turn info field 'bootable' into a bit mask with separate bits for bootable and EFI system partition. This will allow us to identify the EFI system partition in the UEFI sub-system. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-04-30efi_loader: remove superfluous NULL check in bootefi.cHeinrich Schuchardt
efi_free_pool() and efi_delete_handle() both check if their argument is NULL. The caller should not duplicate this check. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-04-30test/py: fix test_efi_secboot/conftest.pyHeinrich Schuchardt
If udisksctl is present test/py/tests/test_efi_secboot/conftest.py fails because the disk image is never mounted. Normal users can only mount fuse file systems. Unfortunately fusefat is still in an experimental state and seems not to work here correctly. So as we have to be root or use the sudo command anyway delete all coding referring to udisksctl. -- We should not use mount point /mnt as this directory or one of its sub-directories might already be in use as active mount points. Instead create a new directory in the build root as mount point. -- Remove debug print statements that have been commented out. print without parentheses is anyway invalid in Python 3. And pytest anyway filters out the output if there is no exception reported. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-04-29Merge https://gitlab.denx.de/u-boot/custodians/u-boot-shTom Rini
- rmobile gen2/gen3 DTS sync and defconfig consolidation
2020-04-29configs: ls2088ardb: Correct DEFAULT_DEVICE_TREE valueKuldeep Singh
LS2088A-RDB has CONFIG_DEFAULT_DEVICE_TREE value correctly set as "fsl-ls2088a-rdb-qspi" for QSPI secure/non-secure boot and TFA non-secure boot mode. Fix the value for TFA secure boot mode. Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-04-29configs: enable DM_ETH support for LS1046ARDBMadalin Bucur
Enable DM_ETH on all the defconfigs for the LS1046ARDB board. Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-04-29configs: enable DM_ETH support for LS1043ARDBMadalin Bucur
Enable DM_ETH on all the defconfigs for the LS1043ARDB board. Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-04-29driver: net: fm: add DM ETH supportMadalin Bucur
Probe the FMan MACs based on the device tree while retaining the legacy code/functionality. One notable change introduced here is that, for DM_ETH, the name of the interfaces is corrected to the fmX-macY format, that avoids the referral to the MAC block names which were incorrect for FMan v3 devices (i.e. DTSEC, TGEC) and had weird formatting (i.e. FM1@DTSEC6, FM1@TGEC1). The legacy code is left unchanged in this respect. Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-04-29driver: net: fm: add DM MDIO supportMadalin Bucur
Allow the MDIO devices to be probed based on the device tree. Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-04-29driver: net: fm: separate receive buffer free codeMadalin Bucur
Move the receive buffer free code in a separate function. Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-04-29driver: net: fm: change init_phy() paramMadalin Bucur
Change the init_phy() parameter to simplify the code. Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-04-29ARM: dts: add QorIQ DPAA 1 FMan v3 to LS1046ARDBMadalin Bucur
Introduce the QorIQ DPAA 1 Frame Manager nodes in the LS1046ARDB device tree. The device tree fragments are copied over with little modification from the Linux kernel source code. Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
generated by cgit (git 2.34.1) at 2025-01-27 13:57:48 +0000