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2020-05-22Merge tag 'u-boot-rockchip-20200522' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip - Fix rk3288 chromebook veyron support; - Add pcie driver support for rk3399; - other fixes for rk3399 boards
2020-05-22Merge tag 'imx8qxp-fixes' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-video - Fix i.MX8QXP boot hang when getting CPU temperature
2020-05-22Merge tag 'efi-2020-07-rc3-2' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-efi Pull request for UEFI sub-system for efi-2020-07-rc3 (2) Problems fixed with these patches are: * UEFI sub-system not working with virtio block devices * Missing SATA support in UEFI sub-system * A superfluous debug statement
2020-05-22Merge tag 'uniphier-v2020.07' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-uniphier UniPhier SoC updates for v2020.07 - De-assert write protect for Denali NAND driver - Clean up include directives - Migrate to DM_ETH, and remove legacy board_eth_init()
2020-05-22eth/r8152: fix typo in register nameHayes Wang
The PAL_BDC_CR should be PLA_BDC_CR. Signed-off-by: Hayes Wang <hayeswang@realtek.com>
2020-05-22usb: dwc3: fix NULL pointer issueChunfeng Yun
The phy_bulk pointer *usb_phys is used before allocated, fix it by using a phy_bulk variable instead in xhci_dwc3_platdata struct Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
2020-05-22usb: ehci-omap: Add Support for DM_USB and OF_CONTROLAdam Ford
The omap3.dtsi file shows the usbhshost node with two sub-nodes for ohci and ehci. This patch file creates the usbhshost, and pulls the portX-mode information. It then locates the EHCI sub-node, and initializes the EHCI controller with the info pulled from the usbhshost node. There is still more to do since there isn't an actual link between the 'phys' reference and the corresponding phy driver, and there is no nop-xceiv driver yet. In the meantime, the older style reference to CONFIG_OMAP_EHCI_PHYx_RESET_GPIO is still needed to pull the phy out of reset until the phy driver is completed and the phandle reference is made. Signed-off-by: Adam Ford <aford173@gmail.com>
2020-05-22rockchip: rk3328: rock64 - fix gen3 SPL hangKurt Miller
Use the same approach as ROC-RK3328-CC which enables SPL GPIO, pinctl and regulator support. This allows the gen3 board to boot through SPL and does not break gen2 in the process. Signed-off-by: Kurt Miller <kurt@intricatesoftware.com> Acked-by: Matwey V. Kornilov <matwey.kornilov@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-22defconfig: veyron: no need for CONFIG_SPL_PINCTRL_FULLUrja Rannikko
Veyrons do not need full pinctrl support for SPL. The full pinctrl support does nothing when enabled with OF_PLATDATA, thus was already unused. This frees about 4kB of SPL size. Signed-off-by: Urja Rannikko <urjaman@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-22rockchip: spl-boot-order: do not attempt to access fdt if OF_PLATDATAUrja Rannikko
gd->fdt_blob is null if using OF_PLATDATA in SPL, which causes a hang after f0921f5098 ("fdt: Sync up to the latest libfdt"). We use the same test that is used in spl_common_init on whether to call fdtdec_setup to unconditionally avoid linking in the fdt-using code when not necessary and thus reduce SPL size. Signed-off-by: Urja Rannikko <urjaman@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-22rockchip: veyron: move board_early_init_f to _r (after reloc)Urja Rannikko
Previously veyron_init() was called in board_init() context, which is called after relocation. Moving it to veyron.c used board_early_init_f which is called way earlier, and causes veyron_init to hang. Using board_early_init_r instead fixes this. Fixes: b678f2790c ("rockchip: rk3288: Move veyron_init() back to veyron.c") Signed-off-by: Urja Rannikko <urjaman@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-22rockchip: spl: veyron speedy boots from SPIUrja Rannikko
Apparently speedy was forgotten from this list of veyron devices. Fixes: 49105fb7ed ("rockchip: add common spl board file") Signed-off-by: Urja Rannikko <urjaman@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-22tools: value checks in rkcommon_check_params()Heinrich Schuchardt
Building with -Wtype-limits yields tools/rkcommon.c: In function ‘rkcommon_check_params’: tools/rkcommon.c:158:27: warning: comparison of unsigned expression < 0 is always false [-Wtype-limits] 158 | if (spl_params.init_size < 0) | ^ tools/rkcommon.c:165:28: warning: comparison of unsigned expression < 0 is always false [-Wtype-limits] 165 | if (spl_params.boot_size < 0) | Fix the value checks. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-22rockchip: Enable PCIe/M.2 on rock960 boardJagan Teki
Due to board limitation some SSD's would work on rock960 PCIe M.2 only with 1.8V IO domain. So, this patch enables grf io_sel explicitly to make PCIe/M.2 to work. Cc: Tom Cubie <tom@radxa.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-22rockchip: Enable PCIe/M.2 on rk3399 board w/ M.2Jagan Teki
Enable PCIe/M.2 support on - NanoPC-T4 - ROC-RK3399-PC Mezzanine boards. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Suniel Mahesh <sunil@amarulasolutions.com> #roc-rk3399-pc Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-22pci: Add Rockchip PCIe PHY controller driverJagan Teki
Yes, it is possible to have a dedicated UCLASS PHY driver for this Rockchip PCIe PHY but there are some issues on Generic PHY framework to support the same. The Generic PHY framework is unable to get the PHY if the PHY parent is of a different uclass. Say if we try to get the PCIe PHY then the phy-uclass will look for PHY in the first instance if it is not in the root node it will try to probe the parent by assuming that the actual PHY is inside the parent PHY of UCLASS_PHY. But, in rk3399 hardware representation PHY like emmc, usb and pcie are part of syscon which is completely a different of UCLASS_SYSCON. Example: grf: syscon@ff770000 { compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; reg = <0x0 0xff770000 0x0 0x10000>; #address-cells = <1>; #size-cells = <1>; pcie_phy: pcie-phy { compatible = "rockchip,rk3399-pcie-phy"; clocks = <&cru SCLK_PCIEPHY_REF>; clock-names = "refclk"; #phy-cells = <1>; resets = <&cru SRST_PCIEPHY>; drive-impedance-ohm = <50>; reset-names = "phy"; status = "disabled"; }; }; Due to this limitation, this patch adds a separate PHY driver for Rockchip PCIe. This might be removed in future once Generic PHY supports this limitation. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Suniel Mahesh <sunil@amarulasolutions.com> #roc-rk3399-pc Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-22pci: Add Rockchip PCIe controller driverJagan Teki
Add Rockchip PCIe controller driver for rk3399 platform. Driver support Gen1 by operating as a Root complex. Thanks to Patrick for initial work. Signed-off-by: Patrick Wildt <patrick@blueri.se> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Suniel Mahesh <sunil@amarulasolutions.com> #roc-rk3399-pc
2020-05-22clk: rk3399: Enable/Disable the PCIEPHY clkJagan Teki
Enable/Disable the PCIEPHY clk for rk3399. CLK is clear in both enable and disable functionality. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Suniel Mahesh <sunil@amarulasolutions.com> #roc-rk3399-pc Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-22clk: rk3399: Add enable/disable clksJagan Teki
Yes, most of the high speed peripheral clocks in rk3399 enabled by default. But it would be better to handle them via clk enable/disable API for handling proper reset conditions like 'usb reset' over command line. So, enable USB, GMAC clock via enable/disable ops. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Suniel Mahesh <sunil.m@amarulasolutions.com> # roc-rk3399-pc Tested-by: Suniel Mahesh <sunil@amarulasolutions.com> #roc-rk3399-pc Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-22rockpro64: Enable HDMI output on rockpro64 boardAndrius Štikonas
Reference to commit that adds HDMI to other rk3399 boards: commit 9778edae5576 ("rockchip: Enable HDMI output on rk3399 board w/ HDMI") Signed-off-by: Andrius Štikonas <andrius@stikonas.eu> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Jagan Teki <jagan@amarulasolutions.com> Cc: Kever Yang <kever.yang@rock-chips.com> Tested-by: Mark Kettenis <kettenis@openbsd.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-22thermal: imx_scu_thermal: prevent boot hang with zero pdataAnatolij Gustschin
Should initialization of pdata values have failed for some reason, we end up in endless loop when getting the CPU temperature value and can not boot. Check alert value in pdata and only retry reading temperature if alert value is not zero. Also shorten the temperature info string. Signed-off-by: Anatolij Gustschin <agust@denx.de>
2020-05-22cpu: imx8: use intended cpu-thermal device when getting temp valueAnatolij Gustschin
This fixes getting DT alert and critical pdata values in imx_scu_thermal driver. On i.MX8QXP using not initialized alert pdata value resulted in boot hang and endless loop outputting: CPU Temperature (47200C) has beyond alert (0C), close to critical (0C) waiting... While at it, preset CPU type values once to avoid multiple calls of device_is_compatible() for same property. Fixes: 3ee6ea443eb4 ("cpu: imx_cpu: Print the CPU temperature for iMX8QM A72") Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2020-05-22cpu: imx8: fix type and rate detectionAnatolij Gustschin
CPU type and rate detection is broken, for A35 cpu we get A53: ... sc_pm_get_clock_rate: resource:0 clk:2: res:3 Could not read CPU frequency: -22 CPU: NXP i.MX8QXP RevB A53 at 0 MHz at 47C Fixes: 55bc96f3b675 ("cpu: imx8: fix get core name and rate") Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2020-05-22rockchip: rk3399: enable spl-fifo-mode for sdmmcDeepak Das
adapting commit fa2047c47310 ("rockchip: rk3328: enable spl-fifo-mode for emmc and sdmmc") for rk3399. Since mmc to sram can't do dma, add patch to prevent aborts transferring TF-A parts. Signed-off-by: Deepak Das <deepakdas.linux@gmail.com>
2020-05-22board: puma: use dtb given on the commandline instead of using u-boot.dtbHeiko Stuebner
The make_fit_spl scripts get the dtb to use as commandline option, so use it for puma as well. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
2020-05-22ARM: uniphier: remove board_eth_init()Masahiro Yamada
This platform completely migrated to CONFIG_DM_ETH. board_eth_init() is only called from net/eth_legacy.c Remove the legacy hook. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-05-22ARM: uniphier: delete or replace <common.h> includesMasahiro Yamada
<common.h> pulls in a lot of bloat. <common.h> is unneeded in most of places. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-05-22ARM: uniphier: drop #include <log.h> againMasahiro Yamada
I do not understand the changes made to these files by commit f7ae49fc4f36 ("common: Drop log.h from common header"). git show f7ae49fc4f36 -- arch/arm/mach-uniphier/ None of them uses the log function feature. Simply revert the changes made to these files. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-05-22ARM: uniphier: drop #include <init.h> again from umc-pxs2.cMasahiro Yamada
I do not understand the change made to this file by commit 691d719db718 ("common: Drop init.h from common header"). git show 691d719db718 -- arch/arm/mach-uniphier/dram/umc-pxs2.c This file does not call or define any functions declared in <init.h> Simply revert the change made to this file. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-05-22ARM: uniphier: remove #include <net.h> again from micro-support-card.cMasahiro Yamada
I do not understand the changes made to this file by commit 90526e9fbac4 ("common: Drop net.h from common header"). git show 90526e9fbac4 -- arch/arm/mach-uniphier/micro-support-card.c The necessary declaration is already included by <netdev.h> at line 112. It also moved the <dm/of.h> inclusion, but I do not understand the motivation of doing so, either. Simply revert the changes made to this file. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-05-22ARM: uniphier: include <asm/system.h> instead of <asm/cache.h> from psci.cMasahiro Yamada
I do not understand the change made to this file by commit 90526e9fbac4 ("common: Drop net.h from common header"). git show 90526e9fbac4 -- arch/arm/mach-uniphier/arm32/psci.c It added <asm/cache.h> while this file does not call the standard cache functions at all. All the uniphier-specific cache functions, uniphier_cache_*() are declared in cache-uniphier.h, which is already included from this file. Including <asm/system.h> is sensible to fix the -Wmissing-prototypes warnings because this file defines psci_cpu_on and psci_system_reset(). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2020-05-22mtd: rawnand: denali: deassert write protect pinMasahiro Yamada
[ Linux commit 9afbe7c0140f663586edb6e823b616bd7076c00a ] If the write protect signal from this IP is connected to the NAND device, this IP can handle the WP# pin via the WRITE_PROTECT register. The Denali NAND Flash Memory Controller User's Guide describes this register like follows: When the controller is in reset, the WP# pin is always asserted to the device. Once the reset is removed, the WP# is de-asserted. The software will then have to come and program this bit to assert/de-assert the same. 1 - Write protect de-assert 0 - Write protect assert The default value is 1, so the write protect is de-asserted after the reset is removed. The driver can write to the device unless someone has explicitly cleared register before booting the kernel. The boot ROM of some UniPhier SoCs (LD4, Pro4, sLD8, Pro5) is the case; the boot ROM clears the WRITE_PROTECT register when the system is booting from the NAND device, so the NAND device becomes read-only. Set it to 1 in the driver in order to allow the write access to the device. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2020-05-22ARM: uniphier: select DM_ETHMasahiro Yamada
drivers/net/smc911x.c has been converted to DM. select DM_ETH to enable it for all the UniPhier platform boards. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-05-22mtd: rawnand: denali: configure SPARE_AREA_SKIP_BYTES only for denali_splMasahiro Yamada
This CONFIG option is only used in denali_spl.c Move it close to SPL_NAND_DENALI, and make it depend on SPL_NAND_DENALI. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-05-21Merge git://git.denx.de/u-boot-shTom Rini
- Enable -ffunction-sections / -fdata-sections --gc-sections to SH - RCar Gen3 updates
2020-05-21efi_loader: check device path is not installed twiceHeinrich Schuchardt
Prior to corrective patches for virtio and SATA devices the same device path was installed on two different handles. This is not allowable. With this patch we will throw an error if this condition occurs for block devices. Update a comment for the installation of the simple file system protocol. Reported-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-05-21efi_loader: device path for SATA devicesHeinrich Schuchardt
Provide device path nodes for SATA devices. This avoids creation of two handles with the same device path indicating our root node. This is what the device paths for a SATA drive with four partitions could like: /VenHw(..)/Sata(0x0,0xffff,0x0) /VenHw(..)/Sata(0x0,0xffff,0x0)/HD(1,MBR,0x81ea591f,0x800,0x63ff830) /VenHw(..)/Sata(0x0,0xffff,0x0)/HD(2,MBR,0x81ea591f,0x6400800,0x9ff830) /VenHw(..)/Sata(0x0,0xffff,0x0)/HD(3,MBR,0x81ea591f,0x6e00800,0x16ef2ab0) /VenHw(..)/Sata(0x0,0xffff,0x0)/HD(4,MBR,0x81ea591f,0x1dcf3800,0x1dcedab0) Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-05-21efi_loader: device path for virtio block devicesHeinrich Schuchardt
The UEFI specification does not define a device sub-type for virtio. Let's use a vendor hardware node here. This avoids creation of two handles with the same device path indicating our root node. Reported-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-05-21efi_loader: initialize root node firstHeinrich Schuchardt
With commit 16ad946f41d3 ("efi_loader: change setup sequence") the detection of block device was moved to the start of the initialization sequence. In the case of virtio devices two handles with the same device path being created. The root node handle should be created before anything else. Reported-by: Ard Biesheuvel <ardb@kernel.org> Fixes: 16ad946f41d3 ("efi_loader: change setup sequence") Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-05-21efi_loader: add EFI_MEMORY_SP to memory attributesHeinrich Schuchardt
The UEFI 2.8 specification has introduced the EFI_MEMORY_SP memory attribute. Add it to the 'efidebug memmap' and 'efi mem' commands. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-05-21efi_loader: Remove unnecessary debugPragnesh Patel
Remove unnecessary debug() from efi_set_variable_common(). native_name is NULL, so there is no meaning to print it. Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-05-20Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriqTom Rini
- Add DM_ETH support for lx2160aqds, ls2080aqds, ls1088aqds - QSI related fixes on ls1012a, ls2080a, ls1046a, ls1088a, ls1043a based platforms - Bug-fixes/updtaes related to ls1046afrwy, fsl-mc, msi-map property
2020-05-20Merge branch '2020-05-19-misc-fixes'Tom Rini
- Assorted minor fixes
2020-05-20sh: Enable ffunction-sections and fdata-sectionsMarek Vasut
Enable these two options to let compiler eliminate unused code. On R2Dplus, this results in considerable amount of saved space: text data bss dec hex filename - 266580 13196 39076 318852 4dd84 u-boot + 220214 12797 38745 271756 4258c u-boot Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Tom Rini <trini@konsulko.com>
2020-05-20ARM: dts: rmobile: Enable eMMC DDR52 modes on Gen3 Salvator-X(S),ULCB,EbisuMarek Vasut
Enable DDR52 modes, since the SD core supports correct switching now. For completeness, list HS200 modes, however those were already enabled. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2020-05-20ARM: rmobile: Enable support for OpTee on Gen3Marek Vasut
Enable OpTee support on R-Car Gen3, so that U-Boot would copy the OpTee /firmware and /reserved-memory nodes into the Linux DT. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com>
2020-05-20ARM: rmobile: Merge prior-stage firmware DT fragment into U-Boot DT on Gen3Marek Vasut
The prior-stage firmware generates DT fragment containing the /firmware node, /reserved-memory node and /memory@ nodes. Merge these nodes into the U-Boot DT, so U-Boot can use this information. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com>
2020-05-20ARM: dts: rmobile: Reserve space in R-Car Gen3 DTsMarek Vasut
Reserve 4 kiB of space in R-Car Gen3 DTs when those DTs are compiled to permit patching in OpTee-OS /firmware node, /reserved-memory node and possibly also additional /memory@ nodes. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com>
2020-05-20fdtdec: Add weak function to patch U-Boot DT right after fdtdec_setup()Marek Vasut
Add weak function which is called right after fdtdec_setup() configured the U-Boot DT. This permits board-specific adjustments to the U-Boot DT before U-Boot starts parsing the DT. This could be used e.g. to patch in various custom nodes or merge in DT fragments from prior-stage firmware. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com>
2020-05-20libfdt: Export overlay_apply_node() as fdt_overlay_apply_node()Marek Vasut
This function is useful to merge a subset of DT into another DT, for example if some prior-stage firmware passes a DT fragment to U-Boot and U-Boot needs to merge it into its own DT. Export this function to permit implementing such functionality. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com>
generated by cgit (git 2.34.1) at 2024-12-26 12:40:30 +0000