summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2019-05-08Merge branch 'master' of git://git.denx.de/u-boot-netTom Rini
- Various PHY fixes / enhancements. - TI K2G fixes
2019-05-08net: phy: micrel: Find Micrel PHY node correctlyJames Byrne
In some of the device trees that specify skew values for KSZ90x1 PHYs the values are stored (incorrectly) in the MAC node, whereas in others it is in an 'ethernet-phy' subnode. Previously the code would fail to find and program these skew values, so this commit changes it to look for an "ethernet-phy" subnode first, and revert to looking in the MAC node if there isn't one. The device trees affected (where the skew values are in a subnode) are imx6qdl-icore-rqs.dtsi, r8a77970-eagle.dts, r8a77990-ebisu.dts, r8a77995-draak.dts, salvator-common.dtsi, sama5d3xcm.dtsi, sama5d3xcm_cmp.dtsi, socfpga_cyclone5_vining_fpga.dts, socfpga_stratix10_socdk.dts and ulcb.dtsi. Before this change the skew values in these device trees would be ignored. The device trees where the skew values are in the MAC node are socfpga_arria10_socdk.dtsi, socfpga_arria5_socdk.dts, socfpga_cyclone5_de0_nano_soc.dts, socfpga_cyclone5_de10_nano.dts, socfpga_cyclone5_de1_soc.dts, socfpga_cyclone5_is1.dts, socfpga_cyclone5_socdk.dts, socfpga_cyclone5_sockit.dts. These should be unaffected by this change. The changes were tested on a sama5d3xcm. Signed-off-by: James Byrne <james.byrne@origamienergy.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-05-08net: phy: micrel: Use correct skew values on KSZ9021James Byrne
Commit ff7bd212cb8a ("net: phy: micrel: fix divisor value for KSZ9031 phy skew") fixed the skew value divisor for the KSZ9031, but left the code using the same divisor for the KSZ9021, which is incorrect. The preceding commit c16e69f702b1 ("net: phy: micrel: add documentation for Micrel KSZ90x1 binding") added the DTS documentation for the KSZ90x1, changing it from the equivalent file in the Linux kernel to correctly state that for this part the skew value is set in 120ps steps, whereas the Linux documentation and driver continue to this day to use the incorrect value of 200 that came from the original KSZ9021 datasheet before it was corrected in revision 1.2 (Feb 2014). This commit sorts out the resulting confusion in a consistent way by making the following changes: - Update the documentation to be clear about what the skew values mean, in the same was as for the KSZ9031. - Update the Micrel PHY driver to select the appropriate divisor for both parts. - Adjust all the device trees that state skew values for KSZ9021 PHYs to use values based on 120ps steps instead of 200ps steps. This will result in the same values being programmed into the skew registers as the equivalent device trees in the Linux kernel do, where it incorrectly uses 200ps steps (since that's where all these device trees were copied from). Signed-off-by: James Byrne <james.byrne@origamienergy.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-05-08net: phy: aquantia: Set only autoneg on in register 4.c441Valentin-catalin Neacsu
For AQR405 in register 4.c441 bit 15 was override with 0. This caused the phy to not negotiate at 2.5GB rate with mac. To avoid this override it needed first to know the previous value of reg 4.c441 and set only bit 3. Signed-off-by: Valentin Catalin Neacsu <valentin-catalin.neacsu@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-05-08net: phy: Fix return value check phy_probeSiva Durga Prasad Paladugu
Don't ignore return value of phy_probe() call as the probe may fail and it needs to be reported. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-05-08net: phy: Reloc next and prev pointers inside phy_driversSiva Durga Prasad Paladugu
This patch relocates the pointers inside phy_drivers incase of manual reloc. Without this reloc, these points to invalid pre relocation address and hence causes exception or hang. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-05-08ARM: k2g-ice: Add pinmux support for rgmii interfaceMurali Karicheri
This add pinmux configuration for rgmii interface so that network driver can be supported on K2G ICE boards. The pinmux configurations for this are generated using the pinmux tool at https://dev.ti.com/pinmux/app.html#/default As this required some BUFFER_CLASS definitions, same is re-used from the linux defnitions in include/dt-bindings/pinctrl/keystone.h Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-05-08ARM: k2g-gp-evm: update to rgmii pinmux configurationMurali Karicheri
This patch updates pinmux configuration for K2G GP EVM based on data generated by the pinmux tool at https://dev.ti.com/pinmux/app.html#/default Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-05-08drivers: net: ldpaa_eth: fix resource leakPankaj Bansal
if an error occurs in ldpaa_eth_init, need to free all resources before returning the error. Threfore, free net_dev before returning from ldpaa_eth_init. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-05-08Merge branch 'master' of git://git.denx.de/u-boot-sunxiTom Rini
- H6 Beelink GS1 board (Clément) - Olimex A64-Teres-I board (Jonas) - sunxi build fix for CONFIG_CMD_PXE|DHCP (Ondrej) - Change include order (Jagan) - EPHY clock changes (Jagan) - EMAC enablement on Cubietruck Plus, BPI-M3 (Chen-Yu Tsai)
2019-05-09sunxi: Enable EMAC on the Bananapi M3Chen-Yu Tsai
The Bananapi M3 has an RTL8211E PHY connected to the EMAC using RGMII. The PHY is powered by DCDC1 through SW @ 3.3V. The board is designed to use 3.3V with RGMII, instead of the standard reduced voltage of 2.5V we see everywhere. DLDO3, which provides the I/O voltages, is raised to match. This patch enables the EMAC and Realtek PHY drivers in the defconfig. The device tree file already has the EMAC enabled. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-05-09sunxi: Enable EMAC on the Cubietruck PlusChen-Yu Tsai
The Cubietruck Plus has an RTL8211E PHY connected to the EMAC using RGMII. The PHY is powered by DLDO4 @ 3.3V, while the I/O pins are powered by DLDO3 @ 2.5V. This patch enables the EMAC and Realtek PHY drivers in the defconfig. The device tree file already has the EMAC enabled. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2019-05-09sun50i: a64: Add Olimex A64-Teres-I board initial supportJonas Smedegaard
Olimex A64-Teres-I board is a mainboard (the only one so far) for Olimex Teres-I DIY laptop kit. Key features: - Allwinner A64 Cortex-A53 - Mali-400MP2 GPU - AXP803 PMIC - 2GB DDR3 RAM - MicroSD Slot - 16GB eMMC Flash - eDP LCD display - HDMI - USB Host - Battery management - 5V DC power supply - Certified Open Source Hardware (OSHW) Works: - i2C - MMC/SD - PWM backlight Known broken: - Internal keyboard (seems to be because the keyboard firmware loads a bootloader first, and then disconnects bootloader and connect real keyboard). External ones connected to the USB port work fine. This patch enables support for the A64-Teres-I board to u-boot, including enabling screen backlight (lacking from Linux device-tree). Linux commit details about the sun50i-a64-teres-i.dts sync: "arm64: dts: allwinner: a64: Rename uart0_pins_a label to uart0_pb_pins" (sha1: d91ebb95b96c8840932dc3a10c9f243712555467) Cosmetic warnings regarding whitespace and placement of SPDX notice for dts file was ignored. config and .dtsi file are adapted from pinebook files. Tested-by: Jonas Smedegaard <dr@jones.dk> Signed-off-by: Jonas Smedegaard <dr@jones.dk> Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> [jagan: move board entry in MAINTAINERS file at proper position] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-05-09net: sun8i_emac: Add EPHY CLK and RESET supportJagan Teki
Add EPHY CLK and RESET support for sun8i_emac driver to enable EPHY TX clock and EPHY reset pins via CLK and RESET framework. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Lothar Felten <lothar.felten@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-05-09test/dm: reset: Add reset_get_by_index[_nodev] testJagan Teki
Add sample dm reset test for reset_get_by_index and reset_get_by_index_nodev functionality code. Cc: Stephen Warren <swarren@nvidia.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-05-09reset: Get the RESET by index without deviceJagan Teki
Getting a RESET by index with device is not straight forward for some use-cases like handling clock operations for child node in parent driver. So we need to process the child node in parent probe via ofnode and process RESET operation for child without udevice but with ofnode. So add reset_get_by_index_nodev() and move the common code in reset_get_by_index_tail() to use for reset_get_by_index() Cc: Stephen Warren <swarren@nvidia.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-05-09test/dm: clk: Add clk_get_by_index[_nodev] testJagan Teki
Add sample dm clk test for clk_get_by_index and clk_get_by_index_nodev functionality code. Cc: Stephen Warren <swarren@nvidia.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-05-09clk: Use clk_get_by_index_tail()Jagan Teki
clk_get_by_index_tail() now handle common clk get by index code so use it from clk_get_by_indexed_prop(). Cc: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-05-09clk: Get the CLK by index without deviceJagan Teki
Getting a CLK by index with device is not straight forward for some use-cases like handling clock operations for child node in parent driver. So we need to process the child node in parent probe via ofnode and process CLK operation for child without udevice but with ofnode. So add clk_get_by_index_nodev() and move the common code in clk_get_by_index_tail() to use for clk_get_by_index() Cc: Stephen Warren <swarren@nvidia.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-05-09serial: sifive: Change include orderJagan Teki
Like clk_get_by_index, there is requirement for clk_get_by_index_nodev. In this case to make common code functionalities for dev and nodev, clk_get_by_index is trying to get the index of clock by passing ofnode instead of actual dev like current gpio uclass does. In these scenarios with current order of include files the serial_sifive driver is unable to find CONFIG_ENV_SIZE. In file included from arch/riscv/include/asm/u-boot.h:23:0, from include/dm/of.h:10, from include/dm/ofnode.h:12, from include/clk.h:11, from drivers/serial/serial_sifive.c:6: include/environment.h:145:19: error: 'CONFIG_ENV_SIZE' undeclared here (not in a function); did you mean 'CONFIG_CMD_XIMG'? #define ENV_SIZE (CONFIG_ENV_SIZE - ENV_HEADER_SIZE) So, fix consists of changing the order of include files in serial_sifive.c to include first common.h file. Cc: Anup Patel <Anup.Patel@wdc.com> Cc: Rick Chen <rick@andestech.com> Cc: Paul Walmsley <paul.walmsley@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-05-09clk: sifive: fu540-prci: Change include orderJagan Teki
Like clk_get_by_index, there is requirement for clk_get_by_index_nodev. In this case to make common code functionalities for dev and nodev, clk_get_by_index is trying to get the index of clock by passing ofnode instead of actual dev like current gpio uclass does. In these scenarios with current order of include files the fu540-prci driver is unable to find CONFIG_ENV_SIZE. In file included from arch/riscv/include/asm/u-boot.h:23:0, from include/dm/of.h:10, from include/dm/ofnode.h:12, from include/clk.h:11, from include/clk-uclass.h:13, from drivers/clk/sifive/fu540-prci.c:32: include/environment.h:145:19: error: 'CONFIG_ENV_SIZE' undeclared here (not in a function); did you mean 'CONFIG_CMD_XIMG'? #define ENV_SIZE (CONFIG_ENV_SIZE - ENV_HEADER_SIZE) So, fix consists of changing the order of include files in fu540-prci.c to include first common.h file. Cc: Anup Patel <Anup.Patel@wdc.com> Cc: Rick Chen <rick@andestech.com> Cc: Paul Walmsley <paul.walmsley@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-05-09spi: atcspi200: Change include orderJagan Teki
Like clk_get_by_index, there is requirement for clk_get_by_index_nodev. In this case to make common code functionalities for dev and nodev, clk_get_by_index is trying to get the index of clock by passing ofnode instead of actual dev like current gpio uclass does. In these scenarios with current order of include files the atcspi200_spi driver is unable to find CONFIG_ENV_SIZE. In file included from arch/nds32/include/asm/u-boot.h:24, from include/dm/of.h:10, from include/dm/ofnode.h:12, from include/clk.h:11, from drivers/spi/atcspi200_spi.c:9: include/environment.h:145:19: error: 'CONFIG_ENV_SIZE' undeclared here (not in a function); did you mean 'CONFIG_CMD_XIMG'? #define ENV_SIZE (CONFIG_ENV_SIZE - ENV_HEADER_SIZE) So, fix consists of changing the order of include files in atcspi200_spi.c to include first common.h file. Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-05-08Merge git://git.denx.de/u-boot-x86Tom Rini
- Allow x86 boards to use TPL, SPL and U-Boot proper - Update sysreset x86 driver to utilize ACPI registers to do power off - Add a new chromebook_samus_tpl board for TPL support - Several minor changes in binman tool
2019-05-08Merge tag 'efi-2019-07-rc2-2' of git://git.denx.de/u-boot-efiTom Rini
Pull request for UEFI sub-system for v2019.07-rc2 (2) Fix a bunch of errors in the UEFI sub-system: * implement missing UnloadImage(), * implement missing RegisterProtocolNotify(), * unload images in Exit(), * parameter checks. Provide a unit test for UnloadImage(). Remove a redundant function for unit tests. Clean up the UEFI sub-system initialization
2019-05-08x86: samus: Add a target to boot through TPLSimon Glass
Add a version of samus which supports booting from TPL to SPL and then to U-Boot. This allows TPL to select from an A or B SPL to support verified boot with field upgrade. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: samus: Update device tree for verified bootSimon Glass
Add nvdata drivers for the TPM and RTC as used on samus. These are needed for Chromium OS verified boot on samus. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: samus: Update device tree for SPLSimon Glass
Add tags to allow required nodes to be present in SPL / TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: Add a simple TPL implementationSimon Glass
Add the required CPU code so that TPL builds correctly. Also update the SPL code to deal with being booted from TPL. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: Add a way to jump from TPL to SPLSimon Glass
When TPL finishes it needs to jump to SPL with the stack set up correctly. Add a function to handle this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: samus: Increase the pre-reloc memory againSimon Glass
This is again too small, so increase it slightly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: broadwell: Update PCH to work in TPLSimon Glass
The early init should only happen once. Update the probe method to deal with TPL, SPL and U-Boot proper. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: Enable the RTC on all boardsSimon Glass
With the move to Kconfig this option should be set in Kconfig, not in the config header file. Move it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: Fix device-tree indentationSimon Glass
With the use of a phandle we can outdent the device tree nodes a little. Fix this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: Update device tree for Chromium OS verified bootSimon Glass
The standard image generated by U-Boot on x86 is u-boot.rom. Add a separate image called image.bin for verified boot. This supports verification in TPL of which SPL/U-Boot to start, then jumping to the correct one, with SPL setting up the SDRAM and U-Boot proper providing the user interface if needed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: Update device tree for TPLSimon Glass
Add TPL binaries to the device x86 binman desciption. When enabled, TPL will start first, doing the 16-bit init, then jump to SPL and finally U-Boot proper. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: Add documentation on the samus flashmapSimon Glass
There are quite a few variables which control where things appear in the final ROM image. Add a flashmap in the documentation to make this easier to figure out. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: squashed "x86: Update the memory map a little" in] [bmeng: fixed typo of 'documentation' in the commit title] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: Support PCI VGA ROM when TPL is usedSimon Glass
When TPL is in use, U-Boot proper should support initing the VGA ROM even though the 32-bit init portion is in SPL. Update the condition to handle this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: Don't generate a bootstage report in SPLSimon Glass
This report is normally generated by U-Boot proper. Correct the condition here so that it respects the Kconfig options for bootstage. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: Don't set up MTRRs in SPLSimon Glass
The MTRRs are normally set up in U-Boot proper, so avoid setting them up in SPL as well. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: Support TPL in Intel common codeSimon Glass
Update the Makefie rules to ensure that the correct files are built when TPL is being used. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: sysreset: Implement the get_last() methodSimon Glass
Add a default implementation of this method which always indicates that the last reset was a power-on reset. This is the most likely type of reset and without a PCH-specific driver we cannot determine any other type. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: sysreset: Implement power-off if availableSimon Glass
On modern x86 devices we can power the system off using the power- management features of the PCH. Add an implementation for this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: sysreset: Separate out the EFI codeSimon Glass
The EFI implementation of reset sits inside the driver and is called directly from outside the driver, breaking the normal driver-model conventions. Worse, it passed NULL as the device pointer, hoping that the called function won't use it, which breaks as soon as code is added to use it. Separate out the implementation to improve the situation enough to allow a future patch to add new sysreset features. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: broadwell: Implement PCH_REQ_PMBASE_INFOSimon Glass
Implement this ioctl() to support power off. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: ivybridge: Implement PCH_REQ_PMBASE_INFOSimon Glass
Implement this ioctl() to support power off. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: pch: Add an ioctl to read power-management infoSimon Glass
Add a new ioctl() request to read information about the power-management system. This can be used to power off the device. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: mrccache: Add more debuggingSimon Glass
When the MRC cache fails to save it is useful to have some debugging info to indicate what when wrong. Add some more debug() calls. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: Support saving MRC data from SPLSimon Glass
When SPL is used to set up the memory controller we want to save the MRC data in SPL to avoid needing to pass it up to U-Boot proper to save. Add a function to handle that. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: Add common Intel code for SPLSimon Glass
Add an implementation of arch_cpu_init_f() so that the x86 SPL code builds and identifies the CPU. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08x86: broadwell: Select refcode and CPU code for SPLSimon Glass
Allow broadwell to build for SPL and include the reference code. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
generated by cgit (git 2.34.1) at 2024-12-27 00:23:33 +0000