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2018-05-29riscv: Enable function sectionsAlexander Graf
The linker can remove sections that are never addressed, so it makes a lot of sense to declare every function as an individual section. This reduces the output U-Boot code size by ~30kb for me. Signed-off-by: Alexander Graf <agraf@suse.de>
2018-05-29riscv: Add setjmp/longjmp codeAlexander Graf
To support efi_loader we need to have platform support for setjmp/longjmp. Add it here. Signed-off-by: Alexander Graf <agraf@suse.de>
2018-05-29configs: remove redundant comment sectionsChris Packham
mv-common.h and mv-plug-common.h still had comments delimiting sections of configuration options that have all been moved to Kconfig by previous treewide efforts. Remove the redundant comment sections. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-29configs: remove empty #ifdef block from mv-common.hChris Packham
The last option guarded by this ifdef was removed in commit 68d534201733 ("sf: Move SPI flash drivers to defconfig"). Remove the now empty ifdef/endif block and the associated comment. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-29arm64: mvebu: defconfig: enable CONFIG_AHCI_MVEBUKen Ma
This patch enables the new ahci mvebu driver for marvell arm64 platform SOCs(A3k and A8k). And since AHCI_MVEBU selects SCSI_AHCI, so "CONFIG_SCSI_AHCI=y" is removed from those default config files. Signed-off-by: Ken Ma <make@marvell.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-29ata: ahci_mvebu: add scsi supportKen Ma
Mvebu AHCI is AHCI driver which uses SCSI under the hood. This patch adjusts AHCI setup to support SCSI by creating a SCSI device as a child. Since the functions of creating SCSI device need the kconfig option DM_SCSI, so let AHCI_MVEBU select DM_SCSI. Signed-off-by: Ken Ma <make@marvell.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-29ata: ahci_mvebu: a8040 a0: remove bad port register offsets workaroundsDavid Sniatkiwicz
This workaround was added for A8040/7040 A0. A8040/7040 A0 is no longer supported so this workaround can be removed. Signed-off-by: David Sniatkiwicz <davidsn@marvell.com> Signed-off-by: Ken Ma <make@marvell.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-29ata: mvebu: move mvebu sata driver to drivers/ata directoryKen Ma
Currently mvebu sata driver is in arch/arm/mach_mvebu directory, this patch moves it to drivers/ata directory with renaming "sata.c" to "ahci_mvebu.c" which is aligned to Linux. New ahci driver's kconfig option is added as AHCI_MVEBU which selects SCSI_AHCI and is based on AHCI. Signed-off-by: Ken Ma <make@marvell.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-29dts: mvebu: a80x0: Enable SD/eMMC interfacesKonstantin Porotchkin
Enable SDHCI interface on AP and CP0 in A80x0 DTS files Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Evan Wang <xswang@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-29mvebu: pinctrl: Add SD/eMMC PHY selector to the driverKonstantin Porotchkin
When the pin control driver selects SD/eMMC function for a pin group, there is additional configuration to be done for this case - switch the PHY to work with SDHCI interface. This patch adds the missing functionality into the pin control driver. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Evan Wang <xswang@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-29mvebu: pinctrl: sync compatible string with Linux 4.17-rc4Evan Wang
For pinctrl driver of mvebu, the compatible strings supported are defined differently from Linux version. The patch aligned the compatible string with Linux 4.17-rc4. Signed-off-by: Evan Wang <xswang@marvell.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-29ARM: kirkwood: Add device-tree for keymileChris Packham
Import the dts files from Linux 4.17 and enable CONFIG_OF_CONTROL. Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-29ARM: kirkwood: Add device-tree for netspace & inetspaceChris Packham
Import the dts files from Linux 4.17 and enable CONFIG_OF_CONTROL. Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-29ARM: kirkwood: Add device-tree for lschlv2 & lsxhlChris Packham
Import the dts files from Linux 4.17 and enable CONFIG_OF_CONTROL. Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-29ARM: kirkwood: Add device-tree for ds109Chris Packham
Import the dts files from Linux 4.17 and enable CONFIG_OF_CONTROL. Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-29ARM: kirkwood: Add device-tree for dreamplugChris Packham
Import the dts file from Linux 4.17 and enable CONFIG_OF_CONTROL. Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-29ARM: kirkwood: Add device-tree for d2net_v2 & net2big_v2Chris Packham
Import the dts files from Linux 4.17 and enable CONFIG_OF_CONTROL. Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-29board: turris_mox: Add fixed regulator support to defconfigMarek Behún
Without this USB3 won't work in U-Boot. Signed-off-by: Marek Behun <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
2018-05-29sf: Add Macronix MX25U25635F IDMarek Vasut
Add ID for the Macronix MX25U25635F flash. Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-05-29sf: Add Winbond W25Q256 IDMarek Vasut
Add ID for the Winbond W25Q256 flash. Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-05-26add FIT data-position & data-offset property supportKelvin Cheung
Add FIT data-position & data-offset property support for bootm, which were already supported in SPL. Signed-off-by: Kelvin Cheung <keguang.zhang@gmail.com>
2018-05-26malloc: Use malloc simple before malloc is fully initialized in memalign()Ley Foon Tan
Follow implementation in mALLOc(). Check GD_FLG_FULL_MALLOC_INIT flag and use malloc_simple if GD_FLG_FULL_MALLOC_INIT is unset. Adjust the malloc bytes to align with the requested alignment. The original memalign() function will access mchunkptr struct to adjust the alignment if there is misalignment happen, but mchunkptr struct is not being initialized before full malloc is initialized. This cause the system crash. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Marek Vasut <marek.vasut@gmail.com>
2018-05-26mmc: stm32_sdmmc2: Fix stm32_sdmmc2_start_cmd()Patrice Chotard
SDMMC_CMD_CPSMEN bit is wrongly check and set in SDMMC_ARG register instead of SDMMC_CMD register. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-05-26stm32mp1: use OTP to configure MAC address and serial numberPatrick Delaunay
Use OTP57 and 58 for MAC address - OTP57 = MAC address bits [31:0] - OTP58 = MAC address bit [47:32] stored in OTP LSB's Use manufacture information in OTP13 to OTP15 to build unique chip id saved in env variable "serial#" (used for USB device enumeration) Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-05-26stm32mp1: add FUSE command supportPatrick Delaunay
Add support of fuse command (read/write/program/sense) on bank 0 to access to BSEC SAFMEM (4096 OTP bits). Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-05-26stm32mp1: add bsec driverPatrick Delaunay
Add a MISC driver with read and write access to BSEC IP (Boot and Security and OTP control) - offset 0: shadowed values - offset 0x80000000: OTP fuse box values (SAFMEM) Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-05-26stm32mp1: remove the second TAMP_BOOT_CONTEXT updatePatrick Delaunay
The register TAMP_BOOT_CONTEXT is already updated in get_bootmode() in cpu.c and no need to be done twice. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-05-26stm32mp1: Allow to activate CONFIG_DEBUG_UARTPatrick Delaunay
Add the needed information to enable the debug uart to have printf before the serial driver probe (so before probe for clock, pincontrol and reset drivers) To enable the debug on uart 4 (default console): + CONFIG_DEBUG_UART=y + CONFIG_DEBUG_UART_STM32=y Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-05-26serial: stm32: Add setparity supportPatrick Delaunay
Add possibility to update the serial parity used. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-05-26dm: serial: Add setparityPatrick Delaunay
Implements serial setparity ops to allow uart parity change. It allows to select ODD, EVEN or NONE parity. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-05-26serial: stm32: Fix bits defines namePatrice Chotard
Rename USART_ISR_FLAG_xxx bits to USART_ISR_xxx bits and USART_ICR_OREF to USART_ICR_ORECF in order to match datasheets. Sort defines by descendant order. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-05-26serial: stm32: Add debug uart supportPatrick Delaunay
Add support for early debug printf, before the availability of driver model and device tree support. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-05-26ram: stm32_sdram: Adds stm32f429-disco fixes for HardFault at bootingRadoslaw Pietrzyk
- adds reading FMC swap setting from DTB to SDRAM driver - sets FMC swap for stm32f429-disco board - changes ram start address to 0x90000000 Signed-off-by: Radoslaw Pietrzyk <radoslaw.pietrzyk@gmail.com> Acked-by: Patrice Chotard <patrice.chotard@st.com>
2018-05-26serial: serial_msm: added pinmux & configRamon Fried
Serial port configuration was missing from previous implementation. It only worked because it was preconfigured by LK. This patch configures the uart for 115200 8N1. It also configures the pin mux for uart pins using DT bindings. Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
2018-05-26db410: added pinctrl node and serial bindingsRamon Fried
Added TLMM pinctrl node for pin muxing & config. Additionally, added a serial node for uart. Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
2018-05-26mach-snapdragon: Introduce pinctrl driverRamon Fried
This patch adds pinmux and pinctrl driver for TLMM subsystem in snapdragon chipsets. Currently, supporting only 8016, but implementation is generic and 8096 can be added easily. Driver is using the generic dt-bindings and doesn't introduce any new bindings (yet). Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-05-26mach-snapdragon: Fix UART clock flowRamon Fried
UART clock enabling flow was wrong. Changed the flow according to downstream implementation in LK. Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
2018-05-26serial: serial_msm: initialize uart only before relocationRamon Fried
The uart is already initialized prior to relocation, reinitialization after relocation is unnecessary. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-05-26serial: serial_msm: fail probe if settings clocks failsRamon Fried
Failure to set the clocks will causes data abort exception when trying to write to AHB uart registers. This patch ensures that we don't touch these registers if clock setting failed. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-05-26db820c: set clk node to be probed before relocationRamon Fried
The clock and serial nodes are needed before relocation. This patch ensures that the msm-serial driver will probe and provide uart output before relocation. Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-05-26Remove CONFIG_MVGBE from config_whitelist.txtChris Packham
Now that there are more boards defining this it can be removed from the whitelist. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-05-26PCI: Document pciauto_region_allocate()Tuomas Tynkkynen
Add a doc comment for pciauto_region_allocate(). Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-05-26PCI: autoconfig: Don't allocate 64-bit addresses to 32-bit only resourcesTuomas Tynkkynen
Currently, if we happen to allocate an address requiring 64 bits to a device only supporting 32-bit BARs, the address eventually gets silently truncated to 32 bits. Avoid this by adding a new flag to pciauto_region_allocate() to bail out in such situations. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-05-26PCI: Add newlines to debug prints in pci_auto_common.cTuomas Tynkkynen
All of the debug output from this file is squished to one line. Fix it. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-05-26doc: qemu-arm: Drop highmem=off referencesTuomas Tynkkynen
Now that U-Boot works fine with highmem enabled, there is no need to tell users to disable highmem. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-05-26ARM: qemu-arm: Bump RAM size in AArch64 MMU tableTuomas Tynkkynen
Now that PCI devices work with highmem-enabled QEMU emulation, bump up the RAM size in the MMU tables to gain access to the full 255 GB of RAM potential instead of the puny 3 GB. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-05-26PCI: dm: Ignore 64-bit memory regions if CONFIG_SYS_PCI_64BIT not setTuomas Tynkkynen
Currently, qemu_arm_defconfig and qemu_arm64_defconfig only work with the 'highmem=off' parameter passed to QEMU's virt machine. The reason is that when 'highmem' is not disabled, QEMU appends 64-bit a memory resource to the PCI controller's regions property in DT in addition to the 32-bit PCI memory window in low memory. And the current DT parsing code picks the last (thus the 64-bit one) memory resource, whose address eventually gets silently truncated to 32 bits because CONFIG_SYS_PCI_64BIT is not set, which obviously causes PCI to break. Avoid this problem by ignoring memory regions whose addresses are above the 32-bit boundary when CONFIG_SYS_PCI_64BIT is not set. Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi> Reviewed-by: Simon Glass <sjg@chromium.org>
2018-05-25configs: add TPMv2.x support in SandboxMiquel Raynal
Enable the Sandbox TPMv2 driver in all possible configurations. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2018-05-25sandbox: dts: add Sandbox TPMv2.x nodeMiquel Raynal
This node declares the presence of the Sandbox TPMv2.x emulated chip, available for testing. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
2018-05-25doc: device-tree-bindings: add Sandbox TPMv2.0 module infoMiquel Raynal
Add Sandbox TPMv2.0 module bindings. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
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