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2019-05-22ARM: dts: Freescale: Add ecc addr for sata nodePeng Ma
Move the ecc addr from driver to dts. Signed-off-by: Peng Ma <peng.ma@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22configs: Enable CONFIG_SPI_FLASH for ls1088ardb_defconfigChuanhua Han
Enables CONFIG_SPI_FLASH Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22armv8: ls1028aqds: Add support of LS1028AQDSYuantian Tang
LS1028AQDS Development System is a high-performance computing, evaluation, and development platform that supports LS1028A QorIQ Architecture processor. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang yuantian <andy.tang@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22armv8: ls1028ardb: Add support for LS1028ARDBYuantian Tang
LS1028A is an ARMv8 implementation. LS1028ARDB is an evaluation platform that supports the LS1028A family SoCs. This patch add basic support of the platform. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22armv8: ls1028a: Add NXP LS1028A SoC supportYuantian Tang
Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22armv8: lx2160a: enable PCIe supportHou Zhiqiang
Enable the PCIe Gen4 controller driver and e1000 for LX2160ARDB and LX2160AQDS boards. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22armv8: lx2160a: add PCIe controller DT nodesHou Zhiqiang
The LX2160A integrated 6 PCIe Gen4 controllers. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22pci: ls_pcie_g4: add device tree fixups for PCI Stream IDsHou Zhiqiang
Add the infrastructure for Layerscape SoCs PCIe Gen4 controller to update device tree nodes to convey SMMU stream IDs in the device tree. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22kconfig: add dependency PCIE_LAYERSCAPE_GEN4 for FSL_PCIE_COMPATHou Zhiqiang
The LX2160A PCIe is using driver PCIE_LAYERSCAPE_GEN4 instead of PCIE_LAYERSCAPE. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22pci: Add PCIe Gen4 controller driver for NXP Layerscape SoCsHou Zhiqiang
Add PCIe Gen4 driver for the NXP Layerscape SoCs. This PCIe controller is based on the Mobiveil IP, which is compatible with the PCI Express™ Base Specification, Revision 4.0. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Bao Xiaowei <Xiaowei.Bao@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22armv8: lx2160a: add MMU table entries for PCIeHou Zhiqiang
The lx2160a have up to 6 PCIe controllers and have different address and size of PCIe region. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22armv8: fsl-layerscpae: correct the PCIe controllers' region sizeHou Zhiqiang
The LS2080A has 8GB region for each PCIe controller, while the other platforms have 32GB. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22armv8: layerscape: use PCIe address macro for precompile PCIe MMU entryHou Zhiqiang
Change to use PCIe address macro to determine if precompile the PCIe MMU table entry. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22configs: ls1046: Update mtd-id for QSPI nor in mtdparts variableKuldeep Singh
Update mtd-id for QSPI nor due to change introduced in mtd/spi in linux 5.0. commit 84d043185dbe ("spi: Add a driver for the Freescale/NXP QuadSPI controller") This modification is only for linux kernel version >= 5.0. To use bootargs for kernel < 5.0, use the following bootargs CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.quadspi:2m(uboot),14m(free)" CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.quadspi:2m(uboot),14m(free)" Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-21dm: core: Fix dm_extended_scan_fdt()Patrice Chotard
This function takes an argument, blob, but never uses it, instead uses gd->fdt_blob directly. Fixes: e81c98649b7a ("dm: core: add clocks node scan") Reported-by: AKASHI Takahiro <takahiro.akashi@linaro.org> Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-21core: ofnode: Have ofnode_read_u32_default return a u32Trent Piepho
It was returning an int, which doesn't work if the u32 it is reading, or the default value, will overflow a signed int. While it could be made to work, when using a C standard/compiler where casting negative signed values to unsigned has a defined behavior, combined with careful casting, it seems obvious one is meant to use ofnode_read_s32_default() with signed values. Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Trent Piepho <tpiepho@impinj.com>
2019-05-21buildman: Deal more nicely with invalid build-status fileSimon Glass
The 'done' files created by buildman may end up being empty if buildman runs out of disk space while writing them. At present buildman dies with an exception when using -s to check the build status. Fix this. Seriesl-cc: trini Signed-off-by: Simon Glass <sjg@chromium.org>
2019-05-21core: ofnode: Add ofnode_get_addr_size_indexKeerthy
Add ofnode_get_addr_size_index function to fetch the address and size of the reg space based on index. Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-05-21common: fdt_support: Check mtdparts cell sizeStefan Mavrodiev
When using fdt_fixup_mtdparts() offset and length cell sizes are limited to 4 bytes (1 cell). However if the mtd device is bigger then 4GiB, then #address-cells and #size-cells are 8 bytes (2 cells) [1]. This patch read #size-cells and uses either fdt32_t or fdt64_t cell size. The default is fdt32_t. [1] Documentation/devicetree/bindings/mtd/partition.txt Signed-off-by: Stefan Mavrodiev <stefan@olimex.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-05-21fdtdec: Remove fdt_{addr,size}_unpack()Thierry Reding
U-Boot already defines the {upper,lower}_32_bits() macros that have the same purpose. Use the existing macros instead of defining new APIs. Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-05-21Add an empty stdint.h fileSimon Glass
Some libraries build by U-Boot may include stdint.h. This is not used by U-Boot itself and causes conflicts with the types defined in linux/types.h. To work around this, add an empty file with this name so that it will be used in preference to the compiler version. Signed-off-by: Simon Glass <sjg@chromium.org>
2019-05-21spl: misc: Allow misc drivers in SPL and TPLSimon Glass
In some cases it is necessary to read the keyboard in early phases of U-Boot. The cros_ec keyboard is kept in the misc directory. Update the config to allow this. Signed-off-by: Simon Glass <sjg@chromium.org>
2019-05-21mmc: tmio: sdhi: HS400 manual adjustmentMarek Vasut
Since Gen3 SDHI has an internal DS signal AC-spec violation in HS400 mode, CRC-error may occur in read command in HS400 mode. This phoenomenon occurs at low/high temperature. To fix this, after completion of HS400 tuning, enable manual calibration. However, Gen3 M3 Ver.1.2 or earlier and H3 1.x does not support HS400. These SoC forcibly use HS200 mode by SoC attribute. The DT adjustment of the tuning parameters is not supported until the DT property names become clear. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Adapted from a patch by Takeshi Saito <takeshi.saito.xv@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Peng Fan <peng.fan@nxp.com>
2019-05-21mmc: tmio: sdhi: Minor macro cleanupMarek Vasut
Clean up the whitespaces in macros, no functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Peng Fan <peng.fan@nxp.com>
2019-05-21ARM: renesas: Factor out DRAM setup on R-Car Gen3Marek Vasut
Pull DRAM layout configuration code into rcar-common.c instead of having it in multiple copies across board files. This poses no change for Salvator-X/XS, ULCB and Ebisu boards, however it adds a bit of extra code for Draak and Eagle boards, which now gain the capability of being passed in the DRAM layout by the ATF. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Eugeniu Rosca <roscaeugeniu@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-05-21ARM: rmobile: Add recovery SPL for R-Car Gen3Marek Vasut
Build an SPL which can be started via SCIF download mode on R-Car Gen3 and allows loading and executing U-Boot uImage with the next stage code. This is also useful for starting e.g. ATF BL2, which inits the hardware and returns to the U-Boot SPL, which can then load e.g. U-Boot proper. The H3, M3-W, M3-N SoCs have plenty of SRAM for storing the U-Boot SPL while the payload, e.g. ATF BL2, executes, so there is no problem here. However, E3 and D3 have much less SRAM, hence the loader uses a trick where it copies itself beyond the area used by BL2 and executes from there. That area is 32kiB large and not enough to hold U-Boot SPL, BSS, stack and malloc area, so the later two are placed at +0x4000 offset from start of SRAM, another area not used by ATF BL2. To make things even more complicated, the SCIF loader cannot load to the upper 32kiB of the SRAM directly, hence the copying approach. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-05-21ARM: rmobile: Sync Gen3 defconfigsMarek Vasut
Synchronize R-Car Gen3 defconfigs to remove duplicate pinctrl entries. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-05-21ARM: rmobile: Enable PCIe driver on R-Car Gen3 Salvator-XMarek Vasut
Enable PCIe driver on R-Car Gen3 Salvator-X boards. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-05-21pci: renesas: Add RCar Gen3 PCIe controller driverMarek Vasut
Add driver for the Renesas RCar PCIe controller present on Gen3 SoCs. The PCIe on Gen3 is used both to connect external PCIe peripherals. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-05-21Merge git://git.denx.de/u-boot-mpc83xxTom Rini
- Update MPC83xx platform support to current best practices, etc.
2019-05-21Merge tag 'mmc-5-20' of https://github.com/MrVan/u-bootTom Rini
"Please pull mmc-5-20 for v2019.07, this is to avoid break i.MX53 boot."
2019-05-21Merge tag 'video-for-2019.07-rc3' of git://git.denx.de/u-boot-videoTom Rini
- update for using splashfile instead of location->name when loading the splash image from a FIT - updates for loading internal and external splash data from FIT - DM_GPIO/DM_VIDEO migration for mx53 cx9020 board - fix boot issue on mx6sabresd board after DM_VIDEO migration - increase the max preallocated framebuffer BPP to 32 in ipuv3 driver to prepare for configurations with higher color depth - allow to use vidconsole_put_string() in board code for text output on LCD displays
2019-05-21mpc83xx: Add gazerbeam boardDirk Eibach
The gdsys gazerbeam board is based on a Freescale MPC8308 SOC. It boots from NOR-Flash, kernel and rootfs are stored on SD-Card. On board peripherals include: - 2x 10/100 Mbit/s Ethernet (optional) Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc> Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-21gazerbeam: Add u-boot specific dts include fileMario Six
Add a U-Boot specific dts file, which encapsulates the needed modifications to the Gazerbeam Linux device tree. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-21gazerbeam: Import Linux DTMario Six
Import the Linux device tree for the Gazerbeam board. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-21board: gazerbeam: Fix SC detectionMario Six
The single channel detection in the gazerbeam board driver was not implemented correctly. Fix the detection. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-21gdsys: ioep-fpga: Switch to gazerbeam-style reportingMario Six
Use a more extensive FPGA feature reporting style in the gdsys ioep-fpga driver. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-21gdsys: cmd_ioloop: Make DM compatibleMario Six
Make the ioloop command DM compatible, while keeping the old functionality for not-yet-converted boards. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-21gdsys: cmd_ioloop: Introduce commenting enumMario Six
Replace the boolean parameter of io_check_status that controls whether the status is printed or not with a documenting enum. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-21gdsys: cmd_ioloop: Fix style violationsMario Six
Fix some style violations in the ioloop command, and make the code more readable where possible. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-21gdsys: mpc8308: Add FPGA flavor optionMario Six
More recent versions of IHS FPGAs feature a different memory layout. Add a Kconfig option to differentiate between the legacy layout, and the new layout (which is used on the upcoming "Gazerbeam" and later boards). Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-21gdsys: Introduce GDSYS_LEGACY_DRIVERSMario Six
Future gdsys boards will switch from the legacy drivers in board/gdsys/common to DM-based drivers. Define a Kconfig option that disables the legacy drivers. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-21gdsys: mpc8308: Don't use manual RAM config if RAM driver is activeMario Six
The "manual" RAM configuration should not be used if the DM RAM driver is active, hence, disable the code if the CONFIG_MPC83XX_SDRAM config variable is defined. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-21gdsys: mpc8308: Migrate SYS_FPGA{0, 1}_{BASE, SIZE} to KconfigMario Six
Move CONFIG_SYS_FPGA0_BASE, CONFIG_SYS_FPGA0_SIZE, CONFIG_SYS_FPGA1_BASE, and CONFIG_SYS_FPGA1_SIZE to Kconfig. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-21gdsys: mpc8308: Use shadow register for output GPIO valuesMario Six
Since the gpio output status on MPC8xxx cannot be read back, it has to be buffered locally. Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc> Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-21gdsys: mpc8308: Fix style violationsMario Six
Fix some style violations in the gdsys MPC8308 board files, and make the code more readable. Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-21gdsys: Post ppc4xx removal cleanupMario Six
The ppc4xx architecture was removed, and with it several old gdsys 44x boards, but some "debris" from these purged boards was left over. This patch removes these remnants (mostly entries in Makefiles, some now superfluous data structures and some now obsolete config variables from the whitelist). Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-05-21gdsys: phy: Adapt fixup_88e1518() to latest Release NotesDirk Eibach
The initialization sequence in the newest release notes of the 88e1518 phy omits two commands. Remove them from the sequence. Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
2019-05-21ihs_mdio: Use new regmap interfaceMario Six
For the DM case, use the proper parameter for the regmap_init_mem call (which is the ofnode, not the udevice). Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Simon Glass <sjg@chromium.org>
2019-05-21gdsys_rxaui_ctrl: Use new regmap interfaceMario Six
For the DM case, use the proper parameter for the regmap_init_mem call (which is the ofnode, not the udevice). Signed-off-by: Mario Six <mario.six@gdsys.cc>
generated by cgit (git 2.34.1) at 2025-01-08 18:07:18 +0000