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2008-03-28mpc8323erdb: define CONFIG_PCI_SKIP_HOST_BRIDGEMichael Barkowski
Commit 55774b512fdf63c0516d441cc5da7c54bbffb7f2 broke the onboard USB controller on the PCI bus in Linux on the MPC8323ERDB. This fixes it by defining CONFIG_PCI_SKIP_HOST_BRIDGE in the board's config file. Signed-off-by: Michael Barkowski <michael.barkowski@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-03-28mpc83xx: cleanup System Part and Revision ID Register (SPRIDR) codeKim Phillips
in the spirit of commit 1ced121600b2060ab2ff9f0fddd9421fd70a0dc6, 85xx's "Update SVR numbers to expand support", simplify SPRIDR processing and processor ID display. Add REVID_{MAJ,MIN}OR macros to make REVID dependent code simpler. Also added PARTID_NO_E and IS_E_PROCESSOR convenience macros. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-03-28mpc83xx: display ddr frequency in board_add_ram_info bannerKim Phillips
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-03-28mpc83xx: unreinvent mem_clkKim Phillips
delete ddr_clk and use mem_clk instead. Rename other ddr_*_clk to mem_*_clk for consistency's sake. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-03-28mpc83xx: enable the SATA interface on mpc8315 rdb and mpc837x rdb boardsKim Phillips
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-03-28mpc83xx: enable the SATA interface on mpc837xemds boardDave Liu
Enable the first two SATA interfaces on MPC837xEMDS board, The two SATA ports are on LYNX1. (SATA0/1 on J4/5) Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-03-28mpc83xx: initialize serdes for MPC837xEMDS boardsDave Liu
This patch is stolen from Anton Vorontsov's patch for mpc837xerdb boards. The reference clk and xcorevdd voltage of serdes1/2 is same between mpc837xemds and mpc837xerdb. 8377E: LYNX1- 2 SATA LYNX2- 2 PCIE 8378E: LYNX1- 2 SGMII LYNX2- 2 PCIE 8379E: LYNX1- 2 SATA LYNX2- 2 SATA Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-03-28ppc4xx: Canyonlands: Print SATA/PCIe configuration and board revisionStefan Roese
Canyonlands (460EX) shares the first PCIe interface with the SoC SATA interface. This usage can be configured with the jumper J6. This patch displays the current configuration upon bootup and changes the PCIe init loop, to only initialize the availabel PCIe slots. Signed-off-by: Stefan Roese <sr@denx.de>
2008-03-28MTD/CFI: Add support for 16bit legacy AMD flashTor Krill
Add entry for 512Kx16 AMD flash to jedec_table. Read out 16bit device id if chipwidth is 16bit. Fixed coding style after Stefans feedback Signed-off-by: Tor Krill <tor@excito.com>
2008-03-28ppc: Small change to CFG_MEM_TOP_HIDE descriptionStefan Roese
Signed-off-by: Stefan Roese <sr@denx.de>
2008-03-28sh: Add support stat structure and stat.hNobuhiro Iwamatsu
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2008-03-28sh: Removed warning when compiling drivers/serial/serial_sh.c.Mark Jonas
Signed-off-by: Mark Jonas <mark.jonas@de.bosch.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2008-03-28sh: Remove disable_ctrlc function from R7780MPNobuhiro Iwamatsu
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2008-03-28sh: Add maintainer of R7780MP to MAINTAINER fileNobuhiro Iwamatsu
Update MAINTAINER entry for R7780MP. And fix maintainer's name. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2008-03-28sh: Add support Renesas Solutions R2D plus boardNobuhiro Iwamatsu
R2D plus is SH reference board used with SH7751R. This board has 266Mhz CPU, 64MB SDRAM, Cardbus, CF interface, one PCI bus, VGA, and two Ethernet controller. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2008-03-28sh: Add support SH4 cache controlNobuhiro Iwamatsu
Add support SH4 cache control and flash_cache function Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2008-03-28sh: Add support PCI host driver for SH7751/SH7751RNobuhiro Iwamatsu
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2008-03-28sh: Move SuperH PCI driver from cpu/sh4 to drivers/pciNobuhiro Iwamatsu
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2008-03-28sh: Add support SuperH SH7751/SH7751RNobuhiro Iwamatsu
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2008-03-28sh: Added support for SH7720 based board MPR2.Mark Jonas
Signed-off-by: Mark Jonas <mark.jonas@de.bosch.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2008-03-28sh: Fix receive FIFO level register of SH4ANobuhiro Iwamatsu
Receive FIFO level register is different in SH4A. Because register is different, cannot occasionally receive data. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2008-03-28sh: Add support Renesas Solutions R7780MPYusuke Goda
Renesas Solutions R7780MP is a reference board on SH7780. This board has serial, 10/100 base Ethernet deivice, CF slot and VGA devices. This board can set extension board. Extension board has 10/100/1000 base Ethernet device, PCI slot, S-ATA, iDVR slot. Signed-off-by: Yusuke Goda <goda.yusuke@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2008-03-28sh: Add support PCI of SuperH and SH7780Yusuke Goda
This patch add support PCI of SuperH base code and SH7780 specific code. Signed-off-by: Yusuke Goda <goda.yusuke@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2008-03-28sh: Add support SH7780Yusuke Goda
SH7780 is CPU of Renesas Technology. This CPU has - CPU clock 400MHz - PCI support - DDR-SDRAM controller - etc ... Signed-off-by: Yusuke Goda <goda.yusuke@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2008-03-28sh: Add support Renesas Solutions Migo-R boardgoda.yusuke
Migo-R is a board based on SH7722 and has may devices. In this patch, supported SCIF, NOR flash and Ethernet. Signed-off-by: Yusuke Goda <goda.yusuke@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2008-03-27Fix host tool build breakage, take twoBartlomiej Sieka
Revert commit 87c8431f and fix build breakage so that the build continues to work on FC systems. Signed-off-by: Bartlomiej Sieka <tur@semihalf.com>
2008-03-27ppc4xx: Enable ECC on LWMON5Stefan Roese
Since all ECC related problems seem to be resolved on LWMON5, this patch now enables ECC support. We have to write the ECC bytes by zeroing and flushing in smaller steps, since the whole 256MByte takes too long for the external watchdog. Signed-off-by: Stefan Roese <sr@denx.de>
2008-03-27ppc4xx: Updates to Korat-specific codeLarry Johnson
This patch contains updates for changes for the Korat PPC440EPx board. These changes include: (1) Support for "permanent" and "upgradable" copies of U-Boot, as described in the new "doc/README.korat" file; (2) a new memory map for the registers in the board's CPLD; (3) a revised format for manufacturer's data in serial EEPROM; and (4) changes to track updates to U-Boot for the Sequoia board. Signed-off-by: Larry Johnson <lrj@acm.org>
2008-03-27ppc4xx: PPC405EP Set EMAC noise filter bitsMarkus Brunner
This bug was introduced with commit aee747f19b460a0e9da20ff21e90fdaac1cec359 which enabled CFG_4xx_GPIO_TABLE for PPC405 and unintentionally disabled the setting of the emac noise filter bits for PPC405EP when CFG_4xx_GPIO_TABLE is set. Signed-off-by: Markus Brunner <super.firetwister@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
2008-03-27ppc4xx: Reconfigure PLL for 667MHz processor for PPC440EPxMike Nuss
On PPC440EPx without a bootstrap I2C EEPROM, the PLL can be reconfigured after startup to change the speed of the clocks. This patch adds the option CFG_PLL_RECONFIG. If this option is set to 667, the CPU initialization code will reconfigure the PLL to run the system with a CPU frequency of 667MHz and PLB frequency of 166MHz, without the need for an external EEPROM. Signed-off-by: Mike Nuss <mike@terascala.com> Acked-by: Stefan Roese <sr@denx.de>
2008-03-27new-image: Fix host tool build breakageHaavard Skinnemoen
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-03-27ppc: Set CFG_MEM_TOP_HIDE to 0 if not already definedStefan Roese
Signed-off-by: Stefan Roese <sr@denx.de>
2008-03-27ppc4xx: Add fdt support to Prodrive alprStefan Roese
Since this board will probably be ported to arch/powerpc in the near future, we add device tree support now. This way we are "ready" for arch/powerpc from now on. Signed-off-by: Stefan Roese <sr@denx.de>
2008-03-27ppc4xx: Enable cache support on the ALPR boardPieter Voorthuijsen
Signed-off-by: Pieter Voorthuijsen <pv@prodrive.nl>
2008-03-27ppc: Add CFG_MEM_TOP_HIDE option to hide memory area that doesn't get "touched"Stefan Roese
If CFG_MEM_TOP_HIDE is defined in the board config header, this specified memory area will get subtracted from the top (end) of ram and won't get "touched" at all by U-Boot. By fixing up gd->ram_size the Linux kernel should gets passed the now "corrected" memory size and won't touch it either. This should work for arch/ppc and arch/powerpc. Only Linux board ports in arch/powerpc with bootwrapper support, which recalculate the memory size from the SDRAM controller setup, will have to get fixed in Linux additionally. This patch enables this config option on some PPC440EPx boards as a workaround for the CHIP 11 errata. Here the description from the AMCC documentation: CHIP_11: End of memory range area restricted access. Category: 3 Overview: The 440EPx DDR controller does not acknowledge any transaction which is determined to be crossing over the end-of-memory-range boundary, even if the starting address is within valid memory space. Any such transaction from any PLB4 master will result in a PLB time-out on PLB4 bus. Impact: In case of such misaligned bursts, PLB4 masters will not retrieve any data at all, just the available data up to the end of memory, especially the 440 CPU. For example, if a CPU instruction required an operand located in memory within the last 7 words of memory, the DCU master would burst read 8 words to update the data cache and cross over the end-of-memory-range boundary. Such a DCU read would not be answered by the DDR controller, resulting in a PLB4 time-out and ultimately in a Machine Check interrupt. The data would be inaccessible to the CPU. Workaround: Forbid any application to access the last 256 bytes of DDR memory. For example, make your operating system believe that the last 256 bytes of DDR memory are absent. AMCC has a patch that does this, available for Linux. This patch sets CFG_MEM_TOP_HIDE for the following 440EPx boards: lwmon5, korat, sequoia The other remaining 440EPx board were intentionally not included since it is not clear to me, if they use the end of ram for some other purpose. This is unclear, since these boards have CONFIG_PRAM defined and even comments like this: PMC440.h: /* esd expects pram at end of physical memory. * So no logbuffer at the moment. */ It is strongly recommended to not use the last 256 bytes on those boards too. Patches from the board maintainers are welcome. Signed-off-by: Stefan Roese <sr@denx.de>
2008-03-27ppc4xx: Fix Canyonlands linker script (remove bogus ASSERT)Stefan Roese
Signed-off-by: Stefan Roese <sr@denx.de>
2008-03-27ppc4xx: Correctly pass phyiscal FLASH base address into dtbStefan Roese
The routine ft_board_setup() configures the EBC NOR mappings for the Linux physmap_of driver. Since on 460EX/GT we remap the FLASH from 0x4.fc00.0000 to 0x4.cc00.0000 because of the max. 16MByte boot-CS problem, we need to pass the corrected address here too. Signed-off-by: Stefan Roese <sr@denx.de>
2008-03-27ppc4xx: Fix compilation warning in 4xx_enet.cStefan Roese
Signed-off-by: Stefan Roese <sr@denx.de>
2008-03-27ppc4xx: Add AMCC Glacier 406GT eval board supportStefan Roese
This patch adds support for the AMCC Glacier 460GT eval board. The main difference to the Canyonlands board are listed here: - 4 ethernet ports instead of 2 - no SATA port - no USB port Currently EMAC2+3 are not working. This will be fixed in a later release. Signed-off-by: Stefan Roese <sr@denx.de>
2008-03-27ppc4xx: Mask 'vec' with 0x1f in uic_interrupt() for bit set/clearStefan Roese
Signed-off-by: Stefan Roese <sr@denx.de>
2008-03-27Merge branch 'master' of git+ssh://10.10.0.7/home/wd/git/u-boot/masterWolfgang Denk
2008-03-27Fix out of tree building issueAnatolij Gustschin
Currently U-Boot building in some external directory doesn't work. This patch tries to fix the problem. Signed-off-by: Anatolij Gustschin <agust@denx.de>
2008-03-27Merge branch 'master' of git://www.denx.de/git/u-boot-mpc85xxWolfgang Denk
2008-03-27Merge branch 'master' of git://www.denx.de/git/u-boot-usbWolfgang Denk
2008-03-27README: update documentation (availability, links, etc.)Anatolij Gustschin
Fix typo in README Signed-off-by: Anatolij Gustschin <agust@denx.de>
2008-03-27Fix compilation error in cmd_usb.cAnatolij Gustschin
This patch fixes compilation error cmd_usb.c: In function 'do_usb': cmd_usb.c:552: error: void value not ignored as it ought to be Signed-off-by: Anatolij Gustschin <agust@denx.de>
2008-03-27Add support for setting the I2C bus speed in fsl_i2c.cTimur Tabi
Add support to the Freescale I2C driver (fsl_i2c.c) for setting and querying the I2C bus speed. Current 8[356]xx boards define the CFG_I2C_SPEED macro, but fsl_i2c.c ignores it and uses conservative value when programming the I2C bus speed. Signed-off-by: Timur Tabi <timur@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
2008-03-27Coding style cleanup, update CHANGELOGWolfgang Denk
Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-03-26drivers: add the support for Freescale SATA controllerDave Liu
Add the Freescale on-chip SATA controller driver to u-boot, The SATA controller is used on the 837x and 8315 targets, The driver can be used to load kernel, fs and dtb. The features list: - 1.5/3 Gbps link speed - LBA48, LBA28 support - DMA and FPDMA support - Two ports support Signed-off-by: Dave Liu <daveliu@freescale.com>
2008-03-26ata: add the readme for SATA command lineDave Liu
Signed-off-by: Dave Liu <daveliu@freescale.com>
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