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2019-01-25ARC: cache: define CONFIG_SYS_CACHELINE_SIZE as ARCH_DMA_MINALIGNAlexey Brodkin
Even though we don't use CONFIG_SYS_CACHELINE_SIZE in ARC-specific code it is used a lot in different drivers for alignment purposes. So we define it and make much more drivers at least compilable for ARC. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-12-03ARC: Improve identification of ARC coresAlexey Brodkin
1. Try to guess a ARC core template that was used i.e. not just name a core family but something more menaingful like "ARC HS38", "ARC EM11D" etc. We do it checking availability of the key differentiation features like: - Caches (we actually only check for L1 I$ fpr simplicity) - XY-memory - DSP extensions etc. 2. Identify ARC subsystems 3. Print core clock frequency Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-09-10arch: types.h: factor out fixed width typedefs to int-ll64.hMasahiro Yamada
All architectures have the same definition for s8/16/32/64 and u8/16/32/64. Factor out the duplicated code into <asm-generic/int-ll64.h>. BTW, Linux unified the kernel space definition into int-ll64.h a few years ago as you see in Linux commit 0c79a8e29b5f ("asm/types.h: Remove include/asm-generic/int-l64.h"). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-07-31ARC: Enable unaligned access in hardware if compiler uses itAlexey Brodkin
Even if ARC core might handle unaligned access to data this hardware feature by default is disabled. But GCC starting from 8.1.0 unconditionally uses it for ARC HS cores. Which leads to quite strange and fatal run-time failures like the one below if HW is not configured properly: | hsdk# sf probe | Misaligned data access exception @ 0xbff794d4 | ECR: 0x000d0000 | RET: 0xbff794d4 | BLINK: 0xbff79644 | STAT32: 0x00000800 | GP: 0x1003e000 r25: 0xbfd58f08 | BTA: 0xbff794a4 SP: 0xbfd58cd4 FP: 0xbfd58ef0 | LPS: 0xbff90240 LPE: 0xbff90244 LPC: 0x00000000 | r00: 0x00000000 r01: 0x00000003 r02: 0x000026bf | r03: 0x00000000 r04: 0x00000100 r05: 0x00000000 | r06: 0x00000001 r07: 0x00000000 r08: 0x1dcd6500 | r09: 0x00000000 r10: 0x00200000 r11: 0x00000000 | r12: 0x1b3d4440 r13: 0xbff9eca4 r14: 0xbfd59d68 | r15: 0xbfd60cd0 r16: 0x00000000 r17: 0x00000000 | r18: 0xbff9ed14 r19: 0xbfd59c78 r20: 0xbfd58d40 | r21: 0xbfd58d44 r22: 0x00000000 r23: 0x00000000 | r24: 0xbfd59ba8 | Resetting CPU ... Now we're checking for __ARC_UNALIGNED__ define emitted by the compiler if it's going to use unaligned access and then we force-enable it in hardware too. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-05-07SPDX: Convert all of our single license tags to Linux Kernel styleTom Rini
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-03-21ARC: Implement a function to sync and cleanup cachesEugeniy Paltsev
Implement specialized function to clenup caches (and therefore sync instruction and data caches) which can be used for cleanup before linux launch or to sync caches during U-Boot self-relocation. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-03-21ARC: Move IOC enabling to compile-time optionsEugeniy Paltsev
Use CONFIG_ARC_DBG_IOC_ENABLE Kconfig option instead of ioc_enable global variable. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-03-21ARC: Move cache global variables to arch_global_dataEugeniy Paltsev
There is a problem with current implementation if we start U-Boot from ROM, as we use global variables before ther initialization, so these variables get overwritten when we copy .data section from ROM. Instead we move these global variables into our "global data" structure so that we may really start from ROM. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-03-21ARC: Move BCR encodings to separate header fileEugeniy Paltsev
We're starting to use more and more BCRs and having their definitions in-lined in sources becomes a bit annoying so we move it all to a separate header. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-03-21ARC: Flush & invalidate D$ with a single commandEugeniy Paltsev
We don't implement separate flush_dcache_all() intentionally as entire data cache invalidation is dangerous operation even if we flush data cache right before invalidation. There is the real example: We may get stuck in the following code if we store any context (like BLINK register) on stack in invalidate_dcache_all() function. BLINK register is the register where return address is automatically saved when we do function call with instructions like 'bl'. void flush_dcache_all() { __dc_entire_op(OP_FLUSH); // Other code // } void invalidate_dcache_all() { __dc_entire_op(OP_INV); // Other code // } void foo(void) { flush_dcache_all(); invalidate_dcache_all(); } Now let's see what really happens during that code execution: foo() |->> call flush_dcache_all [return address is saved to BLINK register] [push BLINK] (save to stack) ![point 1] |->> call __dc_entire_op(OP_FLUSH) [return address is saved to BLINK register] [flush L1 D$] return [jump to BLINK] <<------ [other flush_dcache_all code] [pop BLINK] (get from stack) return [jump to BLINK] <<------ |->> call invalidate_dcache_all [return address is saved to BLINK register] [push BLINK] (save to stack) ![point 2] |->> call __dc_entire_op(OP_FLUSH) [return address is saved to BLINK register] [invalidate L1 D$] ![point 3] // Oops!!! // We lose return address from invalidate_dcache_all function: // we save it to stack and invalidate L1 D$ after that! return [jump to BLINK] <<------ [other invalidate_dcache_all code] [pop BLINK] (get from stack) // we don't have this data in L1 dcache as we invalidated it in [point 3] // so we get it from next memory level (for example DDR memory) // but in the memory we have value which we save in [point 1], which // is return address from flush_dcache_all function (instead of // address from current invalidate_dcache_all function which we // saved in [point 2] !) return [jump to BLINK] <<------ // As BLINK points to invalidate_dcache_all, we call it again and // loop forever. Fortunately we may do flush and invalidation of D$ with a single one instruction which automatically mitigates a situation described above. And because invalidate_dcache_all() isn't used in common U-Boot code we implement "flush and invalidate dcache all" instead. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-03-21ARC: Introduce is_isa_X() functionsEugeniy Paltsev
Introduce is_isa_arcv2() and is_isa_arcompact() functions. These functions only check configuration options and return compile-time constant so they can be used instead of #ifdef's to to write cleaner code. Now we can write: -------------->8--------------- if (is_isa_arcv2()) ioc_configure(); -------------->8--------------- instead of: -------------->8--------------- ifdef CONFIG_ISA_ARCV2 ioc_configure(); endif -------------->8--------------- Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-03-21arc: Fine-tune implementation of memory barriersAlexey Brodkin
We improve on 2 things: 1. Only ARC HS family has "dmb" instructions so do compile-time check for automatically defined macro __ARCHS__. Previous check for ARCv2 ISA was not good enough because ARC EM family is v2 ISA as well but still "dmb" instaruction is not supported in EM family. 2. Still if there's no dedicated instruction for memory barrier let's at least insert compile-time barrier to make sure compiler deosn't reorder critical memory operations. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-03-21arc: Get rid of handwritten string routinesAlexey Brodkin
U-Boot is a bit special piese of software because it is being only executed once on power-on as compared to operating system for example. That's why we don't care much about performance optimizations instead we're more concerned about size. And up-to-date compilers might produce much smaller code compared to performance-optimized routines copy-pasted from the Linux kernel. Here's an example: ------------------------------->8-------------------------- --- size_asm_strings.txt +++ size_c_strings.txt @@ -1,2 +1,2 @@ text data bss dec hex filename - 121260 3784 3308 128352 1f560 u-boot + 120448 3784 3308 127540 1f234 u-boot ------------------------------->8-------------------------- See we were able to shave off ~800 bytes of .text section. Also usage of string routines implemented in C gives us an ability to support more HW flavors for free: generated instructions will match our target as long as correct compiler option is used. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2018-01-19ARC: ARCv2: Cache: Fixed operation without IOCEugeniy Paltsev
Previous SLC management implementation is broken. Seems like it was never sufficiently tested probably because most of the time IOC was used instead (i.e. no manual cache operations were done). Now if we disable IOC in U-boot we'll get a lot of errors while using DMA-enabled peripherals. This time we fix it by substitution of broken per-line SLC operations region operations as it is done in the Linux kernel (we took it from v4.14 which is the latest stable as of today). Among other things this implementation might be a bit faster because instead of iteration over each and every cache line we're taking care about entire region in one go. Main changes: * Replaced __slc_line_op (per line operations) by __slc_rgn_op (region operations). * Reworked __slc_entire_op to get rid of __after_slc_op and __before_slc_op functions. Note flush fix (flush only instead of flush-n-inv when OP_FLUSH is used, see [1] for more details) is already incorporated here. * Added SLC invalidation to invalidate_icache_all(). * Added (start >= end) check to invalidate_dcache_range() and flush_dcache_range() as some buggy drivers pass region start == end. * Added read-out of MMU BCR so we may know if PAE40 exists in HW and then act on a particular AUX regs accordingly. [1] http://lists.infradead.org/pipermail/linux-snps-arc/2018-January/003357.html Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2017-12-11ARC: add defines of some cache and xCCM AUX registersEugeniy Paltsev
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2017-12-11ARC: add macro to get CPU idEugeniy Paltsev
ARCNUM [15:8] field in ARC_AUX_IDENTITY register allows us to uniquely identify each core in a multi-core system. I.e. with help of this macro each core may get its index in SMP system. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2017-12-10ARC: add asm/gpio.h to fix compilation error with CONFIG_CMD_GPIOEugeniy Paltsev
With CONFIG_CMD_GPIO compilation reports error: -------------------------->8--------------------- common/cmd_gpio.c:13:22: fatal error: asm/gpio.h: No such file or directory #include <asm/gpio.h> ^ -------------------------->8--------------------- Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2017-10-02arc: Use asm-generic/io.hPaul Burton
Convert the arc architecture to make use of the new asm-generic/io.h to provide address mapping functions. As the generic implementations are suitable for arc this is primarily a matter of removing code. Feedback from architecture maintainers is welcome. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Alexey Brodkin <alexey.brodkin@synopsys.com> Acked-by: Alexey Brodkin <abrodkin@synopsys.com>
2017-06-05arc: Make u-boot-arc.h a private headerSimon Glass
Rather than including this arch-specific header file in common.h, include it from within arc's u-boot.h header. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-04-05board_f: Make relocation functions genericSimon Glass
This header file is used by three archs. It could be used by all of them since relocation is a common function. Move it into a generic file. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-04-05board_f: Make init_helpers genericSimon Glass
This header file is used by two archs. It could be used by all of them since it allows the cache to be on during relocation. Move it into a generic file. Signed-off-by: Simon Glass <sjg@chromium.org>
2017-03-24drivers: timer: Introduce ARC timer driverVlad Zakharov
This commit introduces timer driver for ARC. ARC timers are configured via ARC AUX registers so we use special functions to access timer control registers. This driver allows utilization of either timer0 or timer1 depending on which one is available in real hardware. Essentially only existing timers should be mentioned in board's Device Tree description. Signed-off-by: Vlad Zakharov <vzakhar@synopsys.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-01-25Convert CONFIG_ARCH_EARLY_INIT_R to KconfigSimon Glass
This converts the following to Kconfig: CONFIG_ARCH_EARLY_INIT_R Signed-off-by: Simon Glass <sjg@chromium.org>
2016-09-23Remove arch/${ARCH}/include/asm/errno.hMasahiro Yamada
Unlike Linux, nothing about errno.h is arch-specific in U-Boot. As you see, all of arch/${ARCH}/include/asm/errno.h is just a wrapper of <asm-generic/errno.h>. Actually, U-Boot does not export headers to user-space, so we just have to care about the consistency in the U-Boot tree. Now all of include directives for <asm/errno.h> are gone. Deprecate <asm/errno.h>. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Alexey Brodkin <abrodkin@synopsys.com>
2016-08-05arc: No need in sections defined in sources with newer toolsAlexey Brodkin
Starting from arc-2016.03 GNU tools linker properly works with symbols defined in linker script and so external declarations are no longer required, dump them. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2016-07-04arc: make global_data.h usable in assembly filesAlexey Brodkin
Currently on attempt to use global_data.h in an assembly file following will happen: -------------------->8----------------- ./arch/arc/include/asm/global_data.h: Assembler messages: ./arch/arc/include/asm/global_data.h:11: Error: bad instruction 'struct arch_global_data{' ./arch/arc/include/asm/global_data.h:12: Error: junk at end of line, first unrecognized character is `}' scripts/Makefile.build:316: recipe for target 'arch/arc/lib/start.o' failed -------------------->8----------------- In this change we disable struct arch_global_data in ASM which fixes the issue above. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2016-06-13arc: Update data accessors with use of memory barriersAlexey Brodkin
Memory barriers are proven to be a requirement for both compiler and real hardware to properly serialize access to critical data. For example if CPU or data bus it uses may do reordering of data accesses absence of memory barriers might easily lead to very subtle and hard to debug data corruptions. This implementation was heavily borrowed from up to date Linux kernel. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2016-04-11arc: Add virt_to_phys() stubAlexey Brodkin
Commit cf7c93cdd755 "usb: ehci: Implement V2P mapping" introduced usage of virt_to_phys() in ehci-hcd. Since there was no implementation of virt_to_phys() for ARC compilation of the ehci-generic driver failed. This change adds virt_to_phys() stub for ARC so now USB driver for AXS101 board could be built again. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Hans de Goede <hdegoede@redhat.com> Acked-by: Marek Vasut <marex@denx.de>
2016-04-11arc: get rid of running_on_hwAlexey Brodkin
ISS is obsolete now and nSIM is used for simulation instead. In its turn nSIM properly handles baud-rate settings so get rid of now useless check. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2016-02-20arc: cache - utilize IO coherency (AKA IOC) engineAlexey Brodkin
With release of ARC HS38 v2.1 new IO coherency engine could be built-in ARC core. This hardware module ensures coherency between DMA-ed data from peripherals and L2 cache. With L2 and IOC enabled there's no overhead for L2 cache manual maintenance which results in significantly improved IO bandwidth. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2016-02-20arc: cache - accommodate different L1 cache line lengthsAlexey Brodkin
ARC core could be configured with different L1 and L2 (AKA SLC) cache line lengths. At least these values are possible and were really used: 32, 64 or 128 bytes. Current implementation requires cache line to be selected upon U-Boot configuration and then it will only work on matching hardware. Indeed this is quite efficient because cache line length gets hardcoded during code compilation. But OTOH it makes binary less portable. With this commit we allow U-Boot to determine real L1 cache line length early in runtime and use this value later on. This extends portability of U-Boot binary a lot. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2015-11-18arc: add empty asm/processor.h to satisfy compilation of USB codeAlexey Brodkin
common/usb.c unconditionally includes <asm/processor.h> And now to allow USB support on ARC boards we have to have that header. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2015-11-18arc: add stubs for map_physmem() and unmap_physmem()Alexey Brodkin
Up until now there was no need in those stubs. But since following commit compilation of U-Boot on ARC is broken: ------------------------>8---------------------- commit 7861204c9af7fec1ea9b41541c272516235a6c93 Author: Stephen Warren <swarren@wwwdotorg.org> Date: Sat Oct 3 13:56:46 2015 -0600 itest: make memory access work under sandbox itest accesses memory, and hence must map/unmap it. Without doing so, it accesses invalid addresses and crashes. Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Reviewed-by: Simon Glass <sjg@chromium.org> ------------------------>8---------------------- That's because CMD_ITEST is enabled by default in common/Kconfig and now map_physmem()/unmap_physmem() is used there. So this patch adds missing stubs for ARC. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Stephen Warren <swarren@wwwdotorg.org>
2015-11-05arc: Use the generic bitops headersFabio Estevam
The generic bitops headers are required when calling logarithmic functions, such as ilog2(). Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2015-07-01arc: significant cache reworkAlexey Brodkin
[1] Align cache management functions to those in Linux kernel. I.e.: a) Use the same functions for all cache ops (D$ Inv/Flush) b) Split cache ops in 3 sub-functions: "before", "lineloop" and "after". That way we may re-use "before" and "after" functions for region and full cache ops. [2] Implement full-functional L2 (SLC) management. Before SLC was simply disabled early on boot. It's also possible to enable or disable L2 cache from config utility. [3] Disable/enable corresponding caches early on boot. So if U-Boot is configured to use caches they will be used at all times (this is useful in partucular for speed-up of relocation). Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2015-04-03arc: add support for SLC (System Level Cache, AKA L2-cache)Alexey Brodkin
ARCv2 cores may have built-in SLC (System Level Cache, AKA L2-cache). This change adds functions required for controlling SLC: * slc_enable/disable * slc_flush/invalidate For now we just disable SLC to escape DMA coherency issues until either: * SLC flush/invalidate is supported in DMA APIin U-Boot * hardware DMA coherency is implemented (that might be board specific so probably we'll need to have a separate Kconfig option for controlling SLC explicitly) Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2015-04-03arc: get rid of CONFIG_SYS_GENERIC_GLOBAL_DATAAlexey Brodkin
As discussed on mailing list we're drifting away from CONFIG_SYS_GENERIC_GLOBAL_DATA in favour to use of board_init_f_mem() for global data. So do this for ARC architecture. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2015-04-03arc: clean-up init procedureAlexey Brodkin
Intention behind this work was elimination of as much assembly-written code as it is possible. In case of ARC we already have relocation fix-up implemented in C so why don't we use C for U-Boot copying, .bss zeroing etc. It turned out x86 uses pretty similar approach so we re-used parts of code in "board_f.c" initially implemented for x86. Now assembly usage during init is limited to stack- and frame-pointer setup before and after relocation. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Simon Glass <sjg@chromium.org>
2015-03-28generic-board: select SYS_GENERIC_BOARD for some architecturesMasahiro Yamada
We have done with the generic board conversion for all the boards of ARC, Blackfin, M68000, MicroBlaze, MIPS, NIOS2, Sandbox, X86. Let's select SYS_GENERIC_BOARD for those architectures, so we can tell which architecture has finished the conversion at a glance. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Alexey Brodkin <abrodkin@synopsys.com>
2015-03-05use ASM_NL instead of '; ' for assembler new line character in the macroChen Gang
For some assemblers, they use another character as newline in a macro (e.g. arc uses '`'), so for generic assembly code, need use ASM_NL (a macro) instead of ';' for it. Basically this is the same patch as applied to Linux kernel - http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/include/linux/linkage.h?id=9df62f054406992ce41ec4558fca6a0fa56fffeb but modified a bit to fit in U-Boot. Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@ti.com>
2015-02-13arc: introduce U-Boot port for ARCv2 ISAAlexey Brodkin
ARC HS and ARC EM are new cores based on ARCv2 ISA which is binary incompatible with ISAv1 (AKA ARCompact). Significant difference between ISAv2 and v1 is implementation of interrupt vector table. In v1 it is implemented in the same way as on many other architectures - as a special location where user may put whether code executed in place (if machine word of space is enough) or jump to a full-scale interrupt handler. In v2 interrupt table is just an array of adresses of real interrupt handlers. That requires a separate section for IVT that is not encoded as code by assembler. This change adds support for following cores: * ARC EM6 (simple 32-bit microcontroller without MMU) * ARC HS36 (advanced 32-bit microcontroller without MMU) * ARC HS38 (advanced 32-bit microcontroller with MMU) As a part of ARC HS38 new version of MMU (v4) was introduced. Also this change adds AXS131 board which is the same DW ARC SDP base board but with ARC HS38 CPU tile. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2015-02-09arc: hard-code CONFIG_ARCH_EARLY_INIT_R in asm/config.hAlexey Brodkin
Common arch_early_init_r() is used in "arc/lib/cpu.c" for all ARC boards so there's no sense in separate per-board definitions. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2015-02-09arc: hard-code CONFIG_SYS_GENERIC_BOARD into asm/config.hAlexey Brodkin
There're no other options for ARC except "generic board" so ther's no point to define CONFIG_SYS_GENERIC_BOARD per board. We now have it set fo all ARC boards. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2015-02-09arc: select cache settings via menuconfigAlexey Brodkin
This change allows to keep board description clean and minimalistic. This is especially helpful if one board may house different CPUs with different features. It is applicable to both FPGA-based boards or those that have CPUs mounted on interchnagable daughter-boards. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2015-02-09arc: define and use PTAG AUX regs for MMUv3 onlyAlexey Brodkin
DC_PTAG and IC_PTAG registers only exist in MMUv3. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2015-02-09arc: add more flavours of ARC700 series CPUAlexey Brodkin
Now we may select a particular version of ARC700: * ARC750D or * ARC770D It allows more flexible (or more fine tuned) configuration of U-Boot. Before that change we relied on minimal configuration but now we may use specific features of each CPU. Moreover allows us to escape manual selection of options that exist in both CPUs but may have say different version like MMUv2 in ARC750D vs MMUv3 in ARC770D. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2015-01-15arc: relocate - minor refactoring and clean-upAlexey Brodkin
* use better symbols for relocatable region boundaries ("__image_copy_start" instead of "CONFIG_SYS_TEXT_BASE") * remove useless debug messages because they will only show up in case of both problem (when normal "if" branch won't be taken) and DEBUG take place which is pretty rare situation. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2015-01-15arc: introduce separate section for interrupt vector tableIgor Guryanov
Even though existing implementation works fine in preparation to submission of ARCv2 architecture we need this change. In case of ARCv2 interrupt vector table consists of just addresses of corresponding handlers. And if those addresses will be in .text section then assembler will encode them as everything in .text section as middle-endian and then on real execution CPU will read swapped addresses and will jump into the wild. Once introduced new section is situated so .text section remains the first which allows us to use common linker option for linking everything to a specified CONFIG_SYS_TEXT_BASE. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Igor Guryanov <guryanov@synopsys.com>
2015-01-15arc: check caches existence before useIgor Guryanov
Some cache operations ({i|d}cache_{enable|disable|status} or flush_dcache_all) are built and used even if CONFIG_SYS_{I|D}CACHE_OFF is set. This is required for force disable of caches on early boot. What if something was executed before U-boot and enabled caches (low-level bootloaders, previously run kernel etc.)? But if CPU doesn't really have caches any attempt to access cache-related AUX registers triggers instruction error exception. So for convenience we'll try to avoid exceptions by checking if CPU actually has caches (we check separately data and instruction cache existence) at all. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Igor Guryanov <guryanov@synopsys.com>
2014-08-26arc: Fix printf size_t format related warnings (again...)Vasili Galka
The basic idea: Define size_t using the __SIZE_TYPE__ compiler-defined type. For detailed explanation see similar patch for the nios2 arch: http://patchwork.ozlabs.org/patch/379938/ Signed-off-by: Vasili Galka <vvv444@gmail.com> Cc: Alexey Brodkin <alexey.brodkin@synopsys.com>
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