Age | Commit message (Collapse) | Author | |
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2012-04-16 | ARM1136: MX35: Make asm routines volatile in cache ops | Stefano Babic | |
As well as pushed for ARM926EJS, we certainly don't want the compiler to reorganise the code for dcache flushing Fix checkpatch warnings as well. Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Marek Vasut <marex@denx.de> CC: Albert Aribaud <albert.u.boot@aribaud.net> | |||
2012-04-16 | ARM1136: add cache flush and invalidate operations | Anatolij Gustschin | |
Since commit 5c1ad3e6f8ae578bbe30e09652f1531e9bc22031 (net: fec_mxc: allow use with cache enabled) the FEC_MXC driver uses flush_dcache_range() and invalidate_dcache_range() functions. This driver is also configured for ARM1136 based 'flea3' and 'mx35pdk' boards which currently do not build as there are no ARM1136 specific flush_dcache_range() and invalidate_dcache_range() functions. Add various ARM1136 cache functions to fix building for 'flea3' and 'mx35pdk'. Signed-off-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> CC: Mike Frysinger <vapier@gentoo.org> CC: Marek Vasut <marex@denx.de> Acked-by: Marek Vasut <marex@denx.de> | |||
2010-06-01 | ARM1136: Fix cache_flush() error and correct cpu_init_crit() comments | George G. Davis | |
The ARM1136 cache_flush() function uses the "mcr p15, 0, rn, c7, c7, 0" instruction which means "Invalidate Both Caches" when in fact the intent is to clean and invalidate all caches. So add an "mcr p15, 0, %0, c7, c10, 0" instruction to "Clean Entire Data Cache" prior to the "Invalidate Both Caches" instruction to insure that memory is consistent with any dirty cache lines. Also fix a couple of "flush v*" comments in ARM1136 cpu_init_crit() so that they correctly describe the actual ARM1136 CP15 C7 Cache Operations used. Signed-off-by: George G. Davis <gdavis@mvista.com> | |||
2010-04-13 | arm: Move cpu/$CPU to arch/arm/cpu/$CPU | Peter Tyser | |
Signed-off-by: Peter Tyser <ptyser@xes-inc.com> |