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path: root/arch/arm/cpu/armv7/am33xx/mem.c
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2013-03-22Initialise correct GPMC WAITx irq for AM33xxMark Jackson
Currently WAIT0 irq is reset and then WAIT1 irq is enabled. Fix it such that WAIT0 irq is enabled instead. Signed-off-by: Mark Jackson <mpfj@newflow.co.uk> Acked-by: Peter Korsgaard <jacmet@sunsite.dk>
2012-12-10am33xx: NAND supportIlya Yanok
TI AM33XX has the same GPMC controller as OMAP3 so we could just use the existing omap_gpmc driver. This patch adds adds required definitions/intialization. Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>