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Without this patch is DRAM size one line below DRAM:
which is not nice
Origin:
I2C: ready
DRAM: Memory: ECC disabled
1 GiB
MMC: zynq_sdhci: 0
Fixed by this patch:
I2C: ready
DRAM: ECC disabled 1 GiB
MMC: zynq_sdhci: 0
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Tested-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
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Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Hans de Goede <hdegoede@redhat.com>
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Do the same as the Linux kernel does, this fixes the SoC hanging on reset
about 50% of the time.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
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Add support for the i2c controller found on all Allwinner sunxi SoCs,
this is the same controller as found on the Marvell orion5x and kirkwood
SoC families, with a slightly different register layout, so this patch uses
the existing mvtwsi code.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Acked-By: Prafulla Wadaskar <prafulla@marvell.com>
Acked-by: Heiko Schocher <hs@denx.de>
[ ijc -- updated u-boot-spl-fel.lds ]
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Commit 3d622b78 (mx6: soc: Introduce set_ldo_voltage()) introduces
set_ldo_voltage() function that can be used to set the voltages
of any of the three LDO regulators controlled by the PMU_REG_CORE register.
Prior to this commit there was a single set_vddsoc() which only configured the
VDDSOC regulator.
Update the comments to align with the new set_ldo_voltage() implementation.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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DIV_SELECT is used as Fout = Fin * div_select / 2.0, so we should do
the shift after the multiply to avoid rounding errors
Signed-off-by: Andre Renaud <andre@bluewatersys.com>
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Mark rc as __maybe_unused since it is infact unused on systems with neither
EMAC nor GMAC.
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Tom Rini <trini@ti.com>
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* This is done by limiting the ARM's bandwidth and setting DSS priority in
the EMIF controller to ensure underflows do not occur.
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The code intends for the CM_DLL_READYST to be set, but
actually polls till any bit is set since the logical
AND is used instead of the bitwise one is used. Fix it.
cc: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
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Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
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Add support for the Allwinner A13 and A10s SoCs also know as the Allwinner
sun5i family, and the A13-OLinuXinoM A13 based and r7-tv-dongle A10s based
boards.
The only differences compared to the already supported sun4i and sun7i
families are all in the DRAM controller initialization:
-Different hcpr values
-Different MBUS settings
-Some other small initialization changes
Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net>
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Oliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
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Add support for the Allwinner A10 SoC also known as the Allwinner sun4i family,
and add the Cubieboard board which uses the A10 SoC.
Compared to sun7 only the DRAM controller is a bit different:
-Controller reset bits are inverted, but only for Rev. A
-Different hpcr values
-No MBUS on sun4i
-Various other initialization changes
Signed-off-by: Henrik Nordstrom <henrik@henriknordstrom.net>
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Oliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
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There is no way to reset the cpu, so use the watchdog for this.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
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Adjust the u-boot-spl.lds linker script to match the changes made in the
41623c91b09a0c865fab41acdaff30f060f29ad6 "arm: move exception handling out
of start.S files" commit.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
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To move the arch common function away from board folder to
arch/arm/cpu/armv7/socfpga folder. Its to avoid code duplication
for other non Altera dev kit which is using socfpga device.
Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Cc: Dinh Nguyen <dinguyen@altera.com>
Acked-by: Detlev Zundel <dzu@denx.de>
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Scan Manager driver will be called to configure the IOCSR
scan chain. This configuration will setup the IO buffer settings
Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Wolfgang Denk <wd@denx.de>
CC: Pavel Machek <pavel@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
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This is not only more readable but also prevents a warning
about a missing prototype. The prototypes which are actually
missing are added.
cc: Albert Aribaud <albert.u.boot@aribaud.net>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Reviewed-by: Tom Rini <trini@ti.com>
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Conflicts:
boards.cfg
Conflict was trivial between goni maintainer change and
lager_nor removal.
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Macros defined in exynos5_setup.h specific to SMDK5420
are required for Peach-Pit too. Hence, replacing
CONFIG_SMDK5420 with CONFIG_EXYNOS5420 to enable these
macros for all the boards based on Exynos5420.
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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gpmc timeout is disabled and the reset counter
is set to 0. However, if later a driver activates
the timeout setting the reset to a valid value,
the old reset value with zero is still valid
for the first access. In fact, the timeout block
loads the reset counter after a successful access.
Found on a am335x board with a FPGA connected
to the GPMC bus together with the NAND.
When the FPGA driver in kernel activates
the timeout, the system hangs at the first access
by the NAND driver.
Signed-off-by: Stefano Babic <sbabic@denx.de>
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Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
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Signed-off-by: Felipe Balbi <balbi@ti.com>
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Move AEMIF driver to drivers/memory/ti-aemif.c along with AEMIF
definitions collected in arch/arm/include/asm/ti-common/ti-aemif.h
Acked-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
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The definitions inside emif_defs.h concern davinci nand driver and
should be in it's header. So create header file for davinci nand
driver and move definitions from emif_defs.h and nand_defs.h to it.
Acked-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
[trini: Fixup more davinci breakage]
Signed-off-by: Tom Rini <trini@ti.com>
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If CONFIG_(NAND|NOR|ONENAND) is not defined, no configuration is set
for GPMC on chip select #0---size is 0. In this case, the GPMC
configuration should be reset but not enabled. Enabling causes the
Gumstix DuoVero board to hang when entering Linux.
Signed-off-by: Ash Charles <ashcharles@gmail.com>
[trini: Switch to testing base as GPMC_SIZE_256M is 0x0]
Signed-off-by: Tom Rini <trini@ti.com>
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The calling code seems a bit in doubt about the return
value of fdtdec_lookup_phandle. Since it returns a negative
value on error (and fdt_node_offset_by_phandle as well),
check for that.
cc: Wei Ni <wni@nvidia.com>
Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
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According to:
http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/log/?h=imx_v2009.08_3.0.35_4.1.0
ENGR00287268 mx6: fix the secure boot issue on the new tapout chip
commit 424cb1a79e9f5ae4ede9350dfb5e10dc9680e90b
newer i.MX6 silicon revisions have an updated ROM and HAB API table.
Please see also:
i.MX Applications Processors Documentation
Engineering Bulletins
EB803, i.MX 6Dual/6Quad Applications Processor Silicon Revsion 1.2 to 1.3 Comparison
With this change the secure boot status is correctly displayed
Signed-off-by: Stefano Babic <sbabic@denx.de>
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Commit 41623c91 moved exception handlers to ".vectores" section
but it missed to adjust Zynq linker script.
Zynq boards hang up after relocation because "_start" symbol
does not point to the correct address and gd->relocaddr gets insane.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Michal Simek <monstr@monstr.eu>
Tested-by: Michal Simek <monstr@monstr.eu>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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For at91 armv7 SoC (SAMA5D3x), only LCD and macb used DMA.
Now as the lcd and macb driver already support dcache. So we can
enable dcache now.
Also we can enable icache without any problem.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
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Sometimes Read DQ and DQS are not in phase. Since, this
phase shift differs from board to board, we need to
calibrate it at DRAM init phase, that's read DQ calibration.
This patch adds SW Read DQ calibration routine to compensate
this skew.
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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when CLKM is running. If we stop CLKM when sampling it the glitches
all go away, so we'll do that as per Samsung suggestion.
We also check the "is it locked" bits of PHY_CON13 and loop until they
show the the value sampled actually represents a locked value. It
doesn't appear that the glitching and "is it locked" are related, but
it seems wise to wait until the PHY tells us the value is good before
we use it. In practice we will not loop more than a couple times (and
usually won't loop at all).
Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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This patch intends to remove all code which enables hardware read
leveling. All characterization environments may not cope up with
h/w read leveling enabled, so we must disable this.
Also, disabling h/w read leveling improves the MIF LVcc value
(LVcc value is the value at which DDR will fail to work properly).
Improving LVcc means we have enough voltage margin for MIF.
When h/w leveling is enabled, we have almost zero volatge margin.
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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Passing fewer arguments is better and mem_iv_size is never
used. Let's keep only one argument and make it cleaner.
Signed-off-by: Hatim Ali <hatim.rv@samsung.com>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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This reverts commit eb0dd9986c3883820ff888c3738b013c0a7d918c.
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Signed-off-by: Vasili Galka <vvv444@gmail.com>
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Enable the cache for all devices, unless CONFIG_SYS_DCACHE_OFF is defined.
This speeds up the Beaglebone Black boot considerable.
(Tested only on Beaglebone Black with SD card boot)
Signed-off-by: Simon Glass <sjg@chromium.org>
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Similar to OMAP4/5 we need to scale the voltage up prior to changing the
clock frequencies up higher. Add a similar hook to start with.
Signed-off-by: Tom Rini <trini@ti.com>
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After enabling a module, SW has to wait on IDLEST bit
until it is Fully functional. This wait is missing for UART module
and there is a immediate access of UART registers after this. So there
is a chance of hang on this module( This can happen when we are running
from MPU SRAM). So waiting for IDLEST bit.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
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Currently PWREMU_MGMT is not configured in the Linux generic UART
driver as this register seems to be specific TI UART IP. So this
needs to be enabled in u-boot to use UART1 from kernel space.
Acked-By: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
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With the changes to the i2c framework (and adopting the omap24xx_i2c
driver to them) we can no longer call i2c functions prior to gd having
been set and cleared. When SPL booting, this is handled by setting gd
to point to SRAM in s_init. However in the cases where we are loaded
directly by ROM (memory mapped NOR or QSPI) we need to make use of the
normal hooks to slightly delay these calls.
Signed-off-by: Tom Rini <trini@ti.com>
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We have two contexts for booting these platforms. One is SPL which is
roughly: reset, cpu_init_crit, lowlevel_init, s_init, sdram_init, _main,
board_init_f from SPL, ... then U-Boot loads. The other is a
memory-mapped XIP case (NOR or QSPI) where we do not run an SPL. In
this case we go, roughly: reset, cpu_init_crit, lowlevel_init, s_init,
_main, regular board_init_f.
In the first case s_init will set a valid gd and then be able to call
sdram_init which in many cases will need i2c (which needs a valid gd for
gd->cur_i2c_bus). In this second case we must (and are able to and
should) defer sdram_init() into dram_init() called by board_init_f as gd
will have been set in _main and cleared in board_init_f.
Signed-off-by: Tom Rini <trini@ti.com>
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The ePOS EVM and EVM SK have QSPI as an option to boot. Add a qspiboot
target that utilizes QSPI for env and so forth as an example of best
practices. As QSPI is booted from directly we need to chang
CONFIG_SYS_TEXT_BASE.
Note that on ePOS EVM the QSPI and NAND are mutually exclusive choices
we need to handle that elsewhere, once NAND support is also added.
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
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GPMC_NAND_ECC_LP_x16_LAYOUT
OMAP3 used GPMC_NAND_ECC_LP_x8_LAYOUT and GPMC_NAND_ECC_LP_x16_LAYOUT macros
to configure GPMC controller for x7 or x8 bit device connected to its interface.
Now this information is encoded in CONFIG_SYS_NAND_DEVICE_WIDTH macro, so above
macros can be completely removed.
Signed-off-by: Pekon Gupta <pekon@ti.com>
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