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2012-09-01mx5/6: Fix cpu_mmc_init() return valueBenoît Thébaudeau
Do not pretend to have initialized mmc successfully if CONFIG_FSL_ESDHC is not defined. Instead, only implement a custom cpu_mmc_init() when it does something. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
2012-09-01imx-common/cmd_bmode.c: add imx bmode (bootmode) commandTroy Kisky
This is useful for forcing the ROM's usb downloader to activate upon a watchdog reset. Or, you can boot from either SD Card. Currently, support added for MX53 and MX6Q Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Note: MX53 support untested. Acked-by: Stefano Babic <sbabic@denx.de>
2012-09-01mx5: cosmetic: Clean up lowlevel_initBenoît Thébaudeau
Coding style cleanup: - Remove useless parentheses. - Use tabs for indentations and alignments. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
2012-09-01mx5/6 timer: Round up tick_to_time() valueBenoît Thébaudeau
Round up tick_to_time() value instead of truncating it. This avoids stopping waits instantly for low usec values, and this generally guarantees that the code always waits for at least the requested duration. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
2012-09-01mx5: Enable dcacheBenoît Thébaudeau
Now that the main i.MX features work fine with dcache enabled, enabled it by default if CONFIG_SYS_DCACHE_OFF is not defined. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
2012-09-01arm:exynos: Enable data cache at exynos based processors.Łukasz Majewski
This patch enables the L1 data cache for systems based on Samsung Exynos processor. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-09-01EXYNOS5: support display port phy control functionDonghwa Lee
This patch support display port phy control function. Signed-off-by: Donghwa Lee <dh09.lee@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-09-01EXYNOS5: support display system register controlDonghwa Lee
This patch supports display block system regisger control. Signed-off-by: Donghwa Lee <dh09.lee@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-09-01EXYNOS5: support exynos5 lcd clock controlDonghwa Lee
This patch support exynos5 lcd clock control. Signed-off-by: Donghwa Lee <dh09.lee@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-09-01ARM: EXYNOS: fixed compiler warning messageJaehoon Chung
Removed [-Wuninitialized] warning message. The fout_sel is assigned to "-1" by default. And start, gpio_func is initialized to 0. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-09-01arm/s5pxx: Fix get_timer_masked to get the time.Zhong Hongbo
In general, The get_timer_masked function get the system time, no the number of ticks. Such as the nand_wait_ready will use get_timer_masked to delay the operations. And change the system time to adopt to the CONFIG_SYS_HZ. Signed-off-by: Hongbo Zhong <bocui107@gmail.com> Tested-by: Jaehoon Chung<jh80.chung@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-09-01EXYNOS5 : Modify pinnumx settings as per Exynos5250 Rev 1.0Rajeshwari Shinde
This patch modifies the pinmux settings of MMC and UART as per Exynos5250 Rev 1.0. It also corrects the gpio offset calculations. Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-09-01EXYNOS5: CLOCK: Add BPLL supportRajeshwari Shinde
This patch adds support for BPLL clock. Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-09-01EXYNOS5: CLOCK: Modify MPLL clock out for Exynos5250 Rev 1.0Rajeshwari Shinde
MPLL clock-out of Exynos5250 Rev 1.0 is always at 1.6GHz. Adjust the divisor value to get 800MHz as needed by devices like UART etc Signed-off-by: Hatim Ali <hatim.rv@samsung.com> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2012-09-01arm: bugfix: save_boot_params_default accesses uninitalized stack when -O0Tetsuyuki Kobayashi
save_boot_params_default() in cpu.c accesses uninitialized stack area when it compiled with -O0 (not optimized). This patch removes save_boot_params_default() and put the equivalent in start.S Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp> Acked-by: Tom Rini <trini@ti.com>
2012-09-01tegra20: Remove armv4t build flagsAllen Martin
These flags were necessary when building tegra20 as a single binary that supported ARM7TDMI and Cortex A9. Now that the ARM7TDMI support is split into a separate SPL, this is no longer necessary. Signed-off-by: Allen Martin <amartin@nvidia.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-09-01tegra20: enable SPL for tegra20 boardsAllen Martin
Add SPL options to tegra20 config files and enable SPL build for tegra20 boards. Also remove redundant code from u-boot that is not contained in SPL. Signed-off-by: Allen Martin <amartin@nvidia.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-09-01tegra20: move tegra20 SoC code to arch/arm/cpu/tegra20-commonAllen Martin
In preparation for splitting out the armv4t code from tegra20, move the tegra20 SoC code to arch/arm/cpu/tegra20-common. This code will be compiled armv4t for the arm7tdmi and armv7 for the cortex A9. Signed-off-by: Allen Martin <amartin@nvidia.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-09-01tegra20: rename tegra2 -> tegra20Allen Martin
This is make naming consistent with the kernel and devicetree and in preparation of pulling out the common tegra20 code. Signed-off-by: Allen Martin <amartin@nvidia.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Tested-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
2012-09-01snowball: Adding board specific cache cleanup routineMathieu J. Poirier
Following ARM's reference manuel for initializing the cache - the kernel won't boot otherwise. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: John Rigby <john.rigby@linaro.org>
2012-09-01armv7: Adding cpu specific cache managmenentMathieu J. Poirier
Some CPU (i.e u8500) need more cache management before launching the Linux kernel. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: John Rigby <john.rigby@linaro.org>
2012-09-01u8500: Enabling power to MMC device on AB8500 V2Mathieu J. Poirier
Register mapping has changed on power control chip between the first and second revision. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: John Rigby <john.rigby@linaro.org> Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01u8500: Moving processor-specific functions to cpu area.Mathieu J. Poirier
Functions such as providing power to the MMC device and reading the processor version register should be in the cpu area for access by multiple u8500-based boards. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: John Rigby <john.rigby@linaro.org> Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01snowball: Moving to ux500.v2 addess scheme for PRCMU accessMathieu J. Poirier
Addresses between ux500.v1 and ux500.v2 have changed slightly, hence mandating a review of the PRCMU access methods. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: John Rigby <john.rigby@linaro.org>
2012-09-01snowball: Adding CPU clock initialisationMathieu J. Poirier
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: John Rigby <john.rigby@linaro.org>
2012-09-01snowball: Adding architecture dependent initialisationMathieu J. Poirier
Enabling timers and clocks in PRCMU and cleaning up mailbox. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: John Rigby <john.rigby@linaro.org>
2012-09-01u8500: Moving prcmu to cpu directoryMathieu J. Poirier
This is to allow the prcmu functions to be used by multiple u8500-based processors. Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: John Rigby <john.rigby@linaro.org>
2012-09-01am33xx evm: Update secure_emif_sdram_config during ddr initSatyanarayana, Sandhya
This patch updates secure_emif_sdram_config with the same value written to sdram_config during ddr3 initialization. During suspend/resume, this value is copied into sdram_config. With this, a write to sdram_config at the end of resume sequence which triggers an init sequence can be avoided. Without this register write in place, the DDR_RESET line goes low for a few cycles during resume which is a violation of the JEDEC spec. Signed-off-by: Satyanarayana, Sandhya <sandhya.satyanarayana@ti.com>
2012-09-01armv7: Make lowlevel_init.S's lowlevel_init do ABI compatible stackTom Rini
Make sure that when we setup the stack before calling s_init() we have the stack have 8-byte alignment for ABI compliance. Tested-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01omap4/5/am33xx: Make lowlevel_init available to all armv7 platformsTom Rini
Make the lowlevel_init function that these platforms have which just sets up the stack and calls a C function available to all armv7 platforms. As part of this we change some of the macros that are used to be more clear. Previously (except for am335x evm) we had been setting CONFIG_SYS_INIT_SP_ADDR to a series of new defines that are equivalent to simply referencing NON_SECURE_SRAM_END. On am335x evm we should have been doing this initially and do now. Cc: Sricharan R <r.sricharan@ti.com> Tested-by: Allen Martin <amartin@nvidia.com> Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01am33xx: Add support, update omap3 McSPI driverTom Rini
Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01am33xx: Correct MMC1, remove MMC2 supportTom Rini
- Correct the MMC1 base offset - Remove MMC2 (that area is reserved and not MMC2). - Add the real BOOT_DEVICE_MMC2 value Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01imx: Use a clear identification of an unidentified CPU typeOtavio Salvador
In case an unidentified CPU type is detected it now returns i.MX??, in a const char. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com>
2012-09-01dm: Move OMAP GPIO driver to drivers/gpio/Marek Vasut
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: U-Boot DM <u-boot-dm@lists.denx.de> Cc: Tom Rini <trini@ti.com> Acked-by: Tom Rini <trini@ti.com> Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01am33xx: Rework pinmux functionsTom Rini
- Move definition of the EEPROM contents to <asm/arch/sys_proto.h> - Make some defines a little less generic now. - Pinmux must be done by done by SPL now. - Create 3 pinmux functions, uart0, i2c0 and board. - Add pinmux specific to Starter Kit EVM for MMC now. Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01am33xx evm: Add CONFIG_CMD_EEPROM and relatedTom Rini
am33xx boards have at least one eeprom and in the case of beaglebones with capes, more. Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01am33xx: Add support for TI AM335x StarterKit EVMTom Rini
- Board requires gpio0 #7 to be set to power DDR3. - Board uses DDR3, add a way to determine which DDR type to call config_ddr with. - Both of the above require filling in the header structure early, move it into the data section. Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01am33xx: Remove board/ti/am335x/evm.cTom Rini
The intention has always been (and boards are to support) an i2c EEPROM that will identify what hardware they are, allowing a single binary to support multiple boards. As such, remove the 'evm.c' file as there is nothing EVM centric in it currently, only SoC peripheral configuration. Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01am33xx: Add DDR3 (Micron MT41J128M16JT-125) timings and supportTom Rini
Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01am33xx: Rework config_ddr to make DDR3 support easier.Tom Rini
In order to support DDR3 as well as DDR2, we need to perform the same init sequence, but with different values. So change config_ddr() to toggle setting pointers/etc for what DDR2 wants, and then calling. Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01am33xx: Move some variables in emif4.c, mark them static.Tom Rini
We need vtpreg and ddrctrl but no longer need a second ddrregs. Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01am33xx: Correct and clean up ddr_regs structTom Rini
The ddr_regs struct was incorrectly offset after the dt0wiratio0 entry. Correct this by documenting a missing register that will be used at some point in the future (when write leveling is supported). Further, the cmdNcs{force,delay} fields are undocumented and we have been setting them to zero, remove. Next, setting of the 'DATAn_REG_PHY_USE_RANK0_DELAYS field belongs with the rest of the ddr_data entries, so program it there. Finally, comment on how we are configuring the DATA1 registers that correspond to the DATA0 (dt0) registers defined in the struct. Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01am33xx: Do not touch 'ratio1' fieldsTom Rini
The various ratio1 fields are not documented in any of the documentation I can find. Removing these and testing has yielded success, so remove the code that sets them and move their locations into the reserved fields. Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01am33xx: Rework config_io_ctrl slightlyTom Rini
This function sets a number of related registers to the same value (the registers in question all have the same field descriptions and are related in operation). Rather than defining a struct and setting the value repeatedly, just pass in the value. Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01am33xx: Use emif_regs struct for storing initialization valuesTom Rini
Rather than defining our own structs to note what to use when programming the EMIF and related re-use the emif_regs struct. Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01am33xx: Turn a number of 'int' functions to 'void'Tom Rini
A number of memory initalization functions were int and always returned 0. Further it's not feasible to be doing error checking here, so simply turn them into void functions. Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01am33xx: Document what we're doing with ddrctrl->ddrckectrlTom Rini
- Remove the call to set ddrctrl->ddrioctrl as it's all zeros. - Comment what we're really setting in ddrctrl->ddrckectrl which is that we're operating in the normal mode where EMIF/PHY clock is controlled by the PHY. Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01am33xx: Clean up unused DDR defines, prefix more with 'DDR2'Tom Rini
- Remove a handful of unused defines. - Prefix more values with 'DDR2' as DDR3 will require different values. Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01am33xx: Move the call to ddr_pll_config, make it take the frequencyTom Rini
Depending on if we have DDR2 or DDR3 on the board we will need to call ddr_pll_config with a different value. This call can be delayed slightly to the point where we know which type of memory we have. Signed-off-by: Tom Rini <trini@ti.com>
2012-09-01am33xx: Pass to config_ddr the type of memory that is connectedTom Rini
We need to pass in the type of memory that is connected to the board. The only reliable way to do this is to know what type of board we are running on (which later will be knowable in s_init()). For now, pass in the value of DDR2. Signed-off-by: Tom Rini <trini@ti.com>
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