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2019-06-19armv8: ls1046afrwy: Add support for LS1046AFRWY platformVabhav Sharma
LS1046AFRWY board supports LS1046A family SoCs. This patch add base support for this board. Board support's 4GB ddr memory, i2c, micro-click module,microSD card, serial console,qspi nor flash,ifc nand flash,qsgmii network interface, usb 3.0 and serdes interface to support two x1gen3 pcie interface. Signed-off-by: Camelia Groza <camelia.groza@nxp.com> Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Pramod Kumar <pramod.kumar_1@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19armv8: fsl-lsch2: add clock support for the second eSDHCYinbo Zhu
Layerscape began to use two eSDHC controllers, for example, LS1012A. They are same IP block with same reference clock. This patch is to add clock support for the second eSDHC. Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19arm: fsl-layerscape: add 0x3040 serdes1 settings for LS1046AMaciej Pijanowski
Signed-off-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com> Cc: piotr.krol@3mdeb.com Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19arm: fsl-layerscape: fix 0x3363 serdes1 settings for ls1046aMaciej Pijanowski
As per LS1046A hardware manual, SGMII.9 and SGMII.10 present on lane D and lane C respectively for 0x3363 protocol. So fix serdes1 settings for ls1046a. Signed-off-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19armv8: fsl-layerscape: fix config dependency for layerscape pci codeAlex Marginean
Fixes a link error on layerscape platform, linking fails with CONFIG_PCI set and CONFIG_PCI_LAYERSCAPE unset. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19armv8: fsl-layerscape: Change bootcmd update logicPankit Garg
Change bootcmd update logic when CONFIG_ENV_ADDR is not defined Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19armv8: fsl-layerscape: Update qspi clk cfgPankit Garg
Update qspi clock configuration in TFABOOT in case of all boot sources except qspi boot source. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19armv8/fsl-layerscape: Add loop to check L3 dcache statusMeenakshi Aggarwal
Flushing L3 cache may need variable time depending upon cache line allocation. Coming up with a proper timeout value would be best handled by simulations under multiple scenarios in your actual system. >From the purely HN-F point of view, the flush would take ~15 cycles for a clean line, and ~22 cycles for a dirty line. For the dirty line case, there are many variables outside the HN-F that will increase the duration per line. For example, a *DBIDResp from the SN-F/SBSX, memory controller latency, SN-F/SBSX RetryAck responses, CCN ring congestion, CCN ring hops, etc, etc. The worst-case timeout would have to factor in all of these variables plus the HN-F cycles for every line in the L3, and assuming all lines are dirty In case if L3 is not flushed properly, system behaviour will be erratic, so remove timeout and add loop to check status of L3 cache. System will stuck in while loop if there is some issue in L3 cache flushing. Signed-off-by: Udit Kumar <udit.kumar@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19armv8: fsl-lsch3: add clock support for the second eSDHCYangbo Lu
Layerscape began to use two eSDHC controllers, for example, LS1028A. They are same IP block with same reference clock. This patch is to add clock support for the second eSDHC. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19armv8: ls1028a: Add other serdes protocal supportXiaowei Bao
Add other serdes protocal support. Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19armv8: ls1028a: enable workaround for USB errarum A-009007Yinbo Zhu
Rx Compliance tests may fail intermittently at high jitter frequencies using default register values. So program register USB_PHY_RX_OVRD_IN_HI in certain sequence to make the Rx compliance test pass. Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-06-19armv8: ls1028a: enable workaround for USB erratum A-008997Ran Wang
Enable workaround for USB erratum A-008997. Here PCSTXSWINGFULL registers has been moved to DSCR as compared to other Layerscape SoCs where it was in SCFG. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22armv8: fsl-layerscape: Set env_loc to ENVL_NOWHERE with CONFIG_ENV_IS_NOWHERE.Udit Agarwal
ENVL_NOWHERE is dependent on CONFIG_ENV_IS_NOWHERE and not on CONFIG_CHAIN_OF_TRUST so return ENVL_NOWHERE when CONFIG_ENV_IS_NOWHERE is enabled Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22armv8: ls1028a: Add NXP LS1028A SoC supportYuantian Tang
Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22kconfig: add dependency PCIE_LAYERSCAPE_GEN4 for FSL_PCIE_COMPATHou Zhiqiang
The LX2160A PCIe is using driver PCIE_LAYERSCAPE_GEN4 instead of PCIE_LAYERSCAPE. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22armv8: lx2160a: add MMU table entries for PCIeHou Zhiqiang
The lx2160a have up to 6 PCIe controllers and have different address and size of PCIe region. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-22armv8: layerscape: use PCIe address macro for precompile PCIe MMU entryHou Zhiqiang
Change to use PCIe address macro to determine if precompile the PCIe MMU table entry. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-18CONFIG_SPL_SYS_[DI]CACHE_OFF: addTrevor Woerner
While converting CONFIG_SYS_[DI]CACHE_OFF to Kconfig, there are instances where these configuration items are conditional on SPL. This commit adds SPL variants of these configuration items, uses CONFIG_IS_ENABLED(), and updates the configurations as required. Acked-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Trevor Woerner <trevor@toganlabs.com> [trini: Make the default depend on the setting for full U-Boot, update more zynq hardware] Signed-off-by: Tom Rini <trini@konsulko.com>
2019-03-03armv8: fsl-layerscape: fix SEC QI ICID setupLaurentiu Tudor
The SEC QI ICID setup in the QIIC_LS register is actually an offset that is being added to the ICID coming from the qman portal. Setting it with a non-zero value breaks SMMU setup as the resulting ICID is not known. On top of that, the SEC QI ICID must match the qman portal ICIDs in order to share the isolation context. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: Horia Geanta <horia.geanta@nxp.com> Reviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-02-19armv8: ls1043a: move SCSI_AHCI and SCSI to arm/KconfigPeng Ma
remove SCSI and SCSI_AHCI configs for ls1043ardb due to no sata interface support. this changed is to fixed the ls1043ardb compile warning as fallows: ===================== WARNING ====================== This board does not use CONFIG_DM_SCSI. Please update the storage controller to use CONFIG_DM_SCSI before the v2019.07 release. Failure to update by the deadline may result in board removal.See doc/driver-model/MIGRATION.txt for more info. ==================================================== Signed-off-by: Peng Ma <peng.ma@nxp.com> [PK: reword the patch subject] Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-02-19armv8: layerscape: move CONFIG_LAYERSCAPE to KconfigRajesh Bhagat
Moves CONFIG_LAYERSCAPE for all NXP Layerscape platforms. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-02-19armv8: layerscape: move TZASC and TZPC configs to KconfigRajesh Bhagat
Moves FSL_TZASC_400 and FSL_TZPC_BP147 configs to Kconfig for LS1088A and LS2088A platforms. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-02-19armv8: emc2305: add support for fan controllerMeenakshi Aggarwal
Add support for fan controller emc2305. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-02-19armv8: fsl-layerscape: reorder rgmii dpmacs' enablementPankaj Bansal
some dpmacs in armv8a based freescale layerscape SOCs can be configured via both serdes(sgmii, xfi, xlaui etc) bits and via EC*_PMUX(rgmii) bits in RCW. e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits Now if a dpmac is enabled by serdes bits then it takes precedence over EC*_PMUX bits. i.e. in LX2160A if we select serdes protocol that configures dpmac17 as SGMII and set the EC1_PMUX as RGMII, then the dpmac is SGMII and not RGMII. Therefore, move the fsl_rgmii_init after fsl_serdes_init. in fsl_rgmii_init function of SOC, we will check if the dpmac is enabled or not? if it is (fsl_serdes_init has already enabled the dpmac), then don't enable it. Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-02-19armv8, lx2160a: Initialize ethernet array in serdes_initPriyanka Jain
Add code to initial ethernet interface arrays with corresponding dpmac-id values in serdes_init function for LX2160A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-01-17armv8: ls1043a: correct the PCIe INTx fixupHou Zhiqiang
On LS1043A rev1.0 there are 4 interrupt pins for INTx, and on rev1.1 there is only 1 for INTx, so the current fixup is inverse of the fact. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2019-01-17armv8: ls1043a: add SVR definitions for 23x23 package siliconHou Zhiqiang
LS1043A/LS1023A 23x23 package silicon has different SVR:VAR_PER. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2019-01-17armv8: ls2088ardb: Add TFABOOT supportRajesh Bhagat
TFABOOT support includes: - ls2088ardb_tfa_defconfig to be loaded by trusted firmware - environment address and size changes for TFABOOT - define BOOTCOMMAND for TFABOOT - remove EL3 specific erratas for TFABOOT Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2019-01-17armv8: ls1088ardb: Add TFABOOT supportPankit Garg
TFABOOT support includes: - ls1088ardb_tfa_defconfig to be loaded by trusted firmware - environment address and size changes for TFABOOT - MC address changes for TFABOOT - define BOOTCOMMAND for TFABOOT - ifc chip select changes for TFABOOT Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2019-01-17armv8: fsl-layerscape: fixes for TFABOOT frameworkRajesh Bhagat
Fixes for TFABOOT framework - update eMMC bootsrc to SD_MMC - Increase buffer size for mcinitcmd from 256 to 512 - Fix mcinitcmd and bootcmd for Secure Boot Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2019-01-01watchdog: imx: add config to disable wdog resetXiaoliang Yang
Add Kconfig option WATCHDOG_RESET_DISABLE to disable watchdog reset in imx_watchdog driver, so that the watchdog will not be fed in u-boot if CONFIG_WATCHDOG_RESET_DISABLE is enabled. Signed-off-by: Xiaoliang Yang <xiaoliang.yang_1@nxp.com>
2019-01-01watchdog: driver support for fsl-lsch2Xiaoliang Yang
Support watchdog driver for fsl-lsch2. It's disabled in default. If you want to use it, please enable CONFIG_IMX_WATCHDOG. Define CONFIG_WATCHDOG_TIMEOUT_MSECS to set watchdog timeout. Signed-off-by: Xiaoliang Yang <xiaoliang.yang_1@nxp.com>
2018-12-06armv8: lx2160a: Add LX2160A SoC SupportPriyanka Jain
LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06armv8:fsl-layerscape: Add support for Chassis 3.2Priyanka Jain
NXP layerscape architecture Chassis 3.2 builds upon chassis3 architecture with changes like DDR Memory map change, removal of IFC and support of upto 8 I2C controller. Patch add README.lsch3_2 and the above changes under macro CONFIG_NXP_LSCH3_2. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06armv8: lsch3: Add support of serdes3 modulePriyanka Jain
Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06armv8: fsl-layerscape: add support of MC framework for TFAPankit Garg
Add support of MC framework for TFA Make MC framework independent of boot source. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06armv8: fsl-layerscape: Update parsing boot sourceYork Sun
Workaround of erratum A010539 clears the RCW source field in PORSR1 register, causing failure of detecting boot source using this method. Use SMC call if U-Boot runs at EL2. If SMC is not implemented or running at EL3, continue to read PORSR1 and presume QSPI as boot source if erratum workaround A010539 is enabled and RCW source is cleared. Signed-off-by: York Sun <york.sun@nxp.com>
2018-12-06armv8: layerscape: skip OCRAM init for TFABOOTRajesh Bhagat
OCRAM initialization is performed by TFA, Hence skipped from u-boot. Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06armv8: layerscape: add SMC calls for DDR size and bank infoRajesh Bhagat
Adds SMC calls for getting DDR size and bank info for TFABOOT. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06armv8: fsl-layerscape: bootcmd identification for TFABOOTPankit Garg
Adds bootcmd identificaton on basis on boot source, valid in TFABOOT configuration. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> [YS: remove unnecessary braces] Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06armv8: layerscape: remove EL3 specific erratas for TFABOOTRajesh Bhagat
Removes EL3 specific erratas for TFABOOT, And now taken care in TFA. ARM_ERRATA_855873, SYS_FSL_ERRATUM_A008850, SYS_FSL_ERRATUM_A008511, SYS_FSL_ERRATUM_A008336, SYS_FSL_ERRATUM_A009663, SYS_FSL_ERRATUM_A009803, SYS_FSL_ERRATUM_A009942, SYS_FSL_ERRATUM_A010165 Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06armv8: fsl-layerscape: identify boot source from PORSR registerRajesh Bhagat
PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06armv8: layerscape: Add TFABOOT supportRajesh Bhagat
Adds TFABOOT support config option and add generic code to enable execution from DDR. Signed-off-by: York Sun <york.sun@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
2018-12-06armv8: fsl-layerscape: change tlb base from OCRAM to DDR in EL < 3Pankit Garg
Change tlb base address from OCRAM to DDR when exception level is less than 3. Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06armv8: layerscape: Enable routing SError exceptionYork Sun
In case SError happens at EL2, if SCR_EL3[EA] is not routing it to EL3, and SCR_EL3[RW] is set to aarch64, setting HCR_EL2[AMO] routes the exception to EL2. Otherwise this exception is not taken. Signed-off-by: York Sun <york.sun@nxp.com>
2018-12-04move data structure out of cpu.hYork Sun
Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com>
2018-09-29Merge tag 'fsl-qoriq-for-v2018.11-rc1' of git://git.denx.de/u-boot-fsl-qoriqTom Rini
Switch to driver model for eSDHC on Layerscape SoCs including LS1021A, LS1043A, LS1046A, LS1088A, LS2088A. Switch to driver model for SATA on LS1021A and LS1043A. Add support for LS1012AFRWY rev C board. Enable SMMU for LS1043A.
2018-09-27armv8: ls1043a: add icid setup supportLaurentiu Tudor
Reuse the existing ICID setup code done for LS1046A smmu enablement and add the equivalent setup for LS1043A chips. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-09-27armv8/ls1088a/ls2088a: esdhc: Add esdhc clock supportYinbo Zhu
This patch adds esdhc clock support for ls1088a and ls2088a. Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-09-27ppa/fm/qe: use block layer in ppa/fm/qe driverYinbo Zhu
At present the MMC subsystem maintains its own list of MMC devices. This cannot work with driver model when CONFIG_BLK is enabled, use blk_dread to replace previous mmc read interface, use mmc_get_blk_desc to get the mmc device property. Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> [York S: reformatted commit message] Reviewed-by: York Sun <york.sun@nxp.com>
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