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2017-10-09armv8: Apply workaround for USB erratum A-009007 to LS1088ARan Wang
Rx Compliance tests may fail intermittently at high jitter frequencies using default register values. Program register USB_PHY_RX_OVRD_IN_HI in certain sequence to make the Rx compliance test pass. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-22armv8: fsl: i2c: Put I2C related code under CONFIG_SYS_I2CSriram Dash
I2C code is put under CONFIG_SYS_I2C. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-22armv8: fsl: ifc: Put IFC related code under CONFIG_FSL_IFCSriram Dash
IFC code is put under CONFIG_FSL_IFC Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-22armv8: fsl-layerscape: Put SATA code under SATA configsAshish Kumar
It is not necessary for every SoC to have 2 SATA controller. So put SATA1, SATA2 code under respective defines. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-15blk: Remove various places that do flush cache after readBin Meng
All these places seem to inherit the codes from the MMC driver where a FIXME was put in the comment. However the correct operation after read should be cache invalidate, not flush. The underlying drivers should be responsible for the cache operation. Remove these codes completely. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: York Sun <york.sun@nxp.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: York Sun <york.sun@nxp.com>
2017-09-11armv8: fsl-layerscape: Add back L3 flushing for all exception levelsYork Sun
CCN-504 HPF registers were believed to be accessible only from EL3. However, recent tests proved otherwise. Remove checking for exception level to re-enable L3 cache flushing for all levels. Signed-off-by: York Sun <york.sun@nxp.com> Tested-by: Zhao Qiang <qiang.zhao@nxp.com>
2017-09-11armv8: fsl-layerscape: Fix MC reserved memory calculationYork Sun
In case high region memory doesn't have enough space for Management Complex (MC), the return value should indicate a failure so the caller can handle it accordingly. Signed-off-by: York Sun <york.sun@nxp.com> Reported-by: Ebony Zhu <ebony.zhu@nxp.com>
2017-09-11armv8: Add workaround for USB erratum A-009007Ran Wang
Rx Compliance tests may fail intermittently at high jitter frequencies using default register values. Program register USB_PHY_RX_OVRD_IN_HI in certain sequence to make the Rx compliance test pass. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Suresh Gupta <suresh.bhagat@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com> [YS: Reordered Kconfig options] Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-11armv8: Add workaround for USB erratum A-008997Ran Wang
Low Frequency Periodic Signaling(LFPS) Peak-to-Peak Differential Output Voltage Test Compliance fails using default transmitter settings Change config of transmitter signal swings by setting register PCSTXSWINGFULL to 0x47 to pass compliance tests. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com> [YS: Reordered Kconfig options] Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-11armv8: Add workaround for USB erratum A-009798Ran Wang
The default setting for USB High Speed Squelch Threshold results in a threshold close to or lower than 100mV. This leads to Receiver Compliance test failure for a 100mV threshold. Shift the threshold from ~100mV towards ~130mV by setting SQRXTUNE to 0x0 to pass USB High Speed Receiver Sensitivity Compliance test. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com> Signed-off-by: Ran Wang <ran.wang_1@nxp.com> [YS: Reordered Kconfig options] Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-11armv8: Add workaround for USB erratum A-009008Ran Wang
USB High Speed (HS) EYE Height Adjustment USB HS speed eye diagram fails with the default value at many corners, particularly at a high temperature Optimal eye at TXREFTUNE value to 0x9 is observed, change set the same value. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> [YS: Reordered Kconfig options] Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-11armv8: fsl-layerscape: Support to add RGMII for ls1088aqdsAshish Kumar
This patch adds support for RGMII protocol NXP's LDPAA2 support RGMII protocol. LS1088A is the first Soc supporting both RGMII and SGMII. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-11armv8: ls1088ardb: Add support for LS1088ARDB platformAshish Kumar
LS1088A is an ARMv8 implementation. The LS1088ARDB is an evaluatoin platform that supports the LS1088A family SoCs. This patch add basic support of the platform. Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> [YS: Disabled NAND in board header file] Reviewed-by: York Sun <york.sun@nxp.com> WIP: disable NAND for LS1088ARDB
2017-09-11armv8: ls1088a: Add NXP LS1088A SoC supportAshish Kumar
LS1088A is compliant with the Layerscape Chassis Generation 3 with eight ARM v8 Cortex-A53 cores in 2 cluster, CCI-400, one 64-bit DDR4 SDRAM memory controller with ECC, Data path acceleration architecture 2.0 (DPAA2), Ethernet interfaces (SGMIIs, RGMIIs, QSGMIIs, XFIs), QSPI, IFC, PCIe, SATA, USB, SDXC, DUARTs etc. Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> [YS: Revised commit message] Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-11armv8: fsl: Use correct conditional compile for ls1012aRan Wang
According current code base, CONFIG_LS1012A should be CONFIG_ARCH_LS1012A, or function fsl_fdt_disable(blob) will be wrongly called to disable all dwc3 USB nodes on LS1012A, which cause Linux USB function stop working at all. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-11armv8: fsl-lsch3: Make CCN-504 related code conditionalAshish Kumar
LS2080 family has CCN-504 cache coherent interconnet. Other SoCs in LSCH3 family may have differnt interconnect. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: revised commit message] Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-11LS2080ARDB: QSPI boot: Secure Boot image validationUdit Agarwal
Adds header address for PPA to be validated during ESBC phase for ARCH_LS2088 and QSPI_BOOT. Moves sec_init prior to ppa_init(). It must be initialized before the PPA. Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> [YS: revised commit message] Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-11SECURE_BOOT: Unify memory map for Layerscape based platformsSumit Garg
Unify memory map for Layerscape based platforms. This patch includes changes in bootscript, bootscript header and PPA header addresses change as per unified memory map. Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Tested-by: Vinitha Pillai <vinitha.pillai@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-09-11fsl-layerscape: Consolidate registers space defination for CCI-400 busAshish Kumar
CoreLink Cache Coherent Interconnect (CCI) provides full cache coherency between two clusters of multi-core CPUs and I/O coherency for devices and I/O masters. This patch add new config option SYS_FSL_HAS_CCI400 and moves existing register space definaton of CCI-400 bus to fsl_immap to be shared. CONFIG_SYS_CCI400_ADDR is replaced with SYS_CCI400_OFFSET in Kconfig. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> [YS: revised commit message, squashed patches for armv8 and armv7] Reviewed-by: York Sun <york.sun@nxp.com>
2017-08-26ARMv8/sec_firmware : Update chosen/kaslr-seed with random numberRuchika Gupta
kASLR support in kernel requires a random number to be passed via chosen/kaslr-seed propert. sec_firmware generates this random seed which can then be passed in the device tree node. sec_firmware reserves JR3 for it's own usage. Node for JR3 is removed from device-tree. Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
2017-08-16env: Rename getenv/_f() to env_get()Simon Glass
We are now using an env_ prefix for environment functions. Rename these two functions for consistency. Also add function comments in common.h. Quite a few places use getenv() in a condition context, provoking a warning from checkpatch. These are fixed up in this patch also. Suggested-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Simon Glass <sjg@chromium.org>
2017-08-13spl: add hierarchical defaults for SPL_LDSCRIPTPhilipp Tomsich
With SPL_LDSCRIPT moved to Kconfig (and this being a 'string' config node), all the lingering definitions in header files will cause warnings/errors due to the redefinition of the configuration item. As we don't want to pollute the defconfig files (and values should usually be identical for entire architectures), the defaults are moved into Kconfig. Kconfig will always pick the first default that matches, so please keep these values at the end of each file (to allow any board-specific Kconfig, which will be included earlier) to override with an unconditional default setting. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-11Convert CONFIG_CMD_PCI to KconfigSimon Glass
This converts the following to Kconfig: CONFIG_CMD_PCI Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-08-09armv8/fsl-lsch2: correct the config description of DSPI clock dividerHou Zhiqiang
It is derived from Platform clock instead of Platform PLL frequency. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-08-01armv8: Remove duplicate definition for IH_ARCH_ARM and IH_ARCH_ARM64Alison Wang
The duplicate definitions for IH_ARCH_ARM and IH_ARCH_ARM64 are removed. The definitions in <image.h> are used. According to this modification, the comparison between os arch and cpu arch is done in C programming instead of ASM programming. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-07-11armv8: fsl-layerscape: use get_nand_dev_by_index()Grygorii Strashko
As part of preparation for nand DM conversion the new API has been introduced to remove direct access to nand_info array. So, use it here instead of accessing to nand_info array directly. Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: York Sun <york.sun@nxp.com> Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
2017-07-11dm: scsi: Document and rename the scsi_scan() parameterSimon Glass
The 'mode' parameter is actually a flag to determine whether to display a list of devices found during the scan. Rename it to reflect this, add a function comment and adjust callers to use a boolean. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-07-11Convert CONFIG_SCSI to KconfigSimon Glass
This converts the following to Kconfig: CONFIG_SCSI Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-06-05common: freescale: Move arch-specific declarationsSimon Glass
The declarations should not be in common.h. Move them to the arch-specific headers. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Fixup thinko defined(FSL_LSCH3) -> defined(CONFIG_FSL_LSCH3)] Signed-off-by: Tom Rini <trini@konsulko.com>
2017-06-03Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini
2017-06-01armv8: layerscape: Enabling loading PPA during SPL stageYork Sun
Loading PPA in SPL puts the rest of U-Boot (including RAM version loaded later) in EL2 with MMU and cache enabled. Once PPA is loaded, PSCI is available. Signed-off-by: York Sun <york.sun@nxp.com>
2017-06-01armv8: layerscape: Make U-Boot EL2 safeYork Sun
When U-Boot boots from EL2, skip some lowlevel init code requiring EL3, including CCI-400/CCN-504, trust zone, GIC, etc. These initialization tasks are carried out before U-Boot runs. This applies to the RAM version image used for SPL boot if PPA is loaded first. Signed-off-by: York Sun <york.sun@nxp.com>
2017-06-01armv8: ls2080aqds: Add support for SD bootSantan Kumar
Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-06-01armv8: ls2080a: Reorganise NAND_BOOT code in config flagSantan Kumar
Add CONFIG_NAND_BOOT config flag to organise NAND_BOOT specific code in config flag like -nand-boot specfic errata errata_rcw_src() -CONFIG_SYS_NAND_U_BOOT_DST,etc Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-06-01fdt: Rename a few functions in fdt_supportSimon Glass
These two functions have an of_ prefix which conflicts with naming used in of_addr. Rename them: fdt_read_number fdt_support_bus_default_count_cells Signed-off-by: Simon Glass <sjg@chromium.org>
2017-05-23armv8: ls2080ardb, ls2080aqds: Adjust memory map for NOR-bootSantan Kumar
This patch adjusts memory map for images on LS2080ARDB and LS2080AQDS NOR flash as below Image Flash Offset RCW+PBI 0x00000000 Boot firmware (U-Boot) 0x00100000 Boot firmware Environment 0x00300000 PPA firmware 0x00400000 PHY firmware 0x00980000 DPAA2 MC 0x00A00000 DPAA2 DPL 0x00D00000 DPAA2 DPC 0x00E00000 Kernel.itb 0x01000000 Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-05-23armv8: layerscape: Adjust memory mapping for Flash/SD card on LS1043AAlison Wang
This patch is to adjust the memory mapping for FLash/SD card on LS1043AQDS and LS1043ARDB, such as PPA firmware load address, FMAN firmware load address, QE firmware load address, U-Boot start address on serial flash and environment address. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-05-23armv8: fsl-layerscape: Add NXP LS2081A, LS2041A SoC supportPriyanka Jain
The QorIQ LS2081A SoC has eight 64-bit ARM v8 Cortex A72 cores and is built on layerscape architecture. It is 40-pin derivative of LS2084A (non-AIOP personality of LS2088A). So feature-wise it is same as LS2084A. LS2041A is a 4-core personality of LS2081A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-05-23armv8: ls2080ardb: Add QSPI-boot supportPriyanka Jain
QSPI-boot is supported on LS2088ARDB RevF board with LS2088A SoC. LS2088ARDB RevF Board has limitation that QIXIS can not be accessed. CONFIG_FSL_QIXIS is not enabled. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-04-24arm: psci: make psci usable on single core socsYuantian Tang
PSCI can be used on both multiple and single core socs. Current implementation only allows PSCI to work on multiple core socs. This patch removes this restriction so that PSCI can work on single core socs as well. Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-04-24armv8: fsl-layerscape: Add validation of PPA image from NAND and SDSumit Garg
Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Tested-by: Vinitha Pillai <vinitha.pillai@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-04-24armv8: fsl-layerscape: Support loading PPA header from eMMC/SD and NAND FlashSumit Garg
Add Kconfig option to support loading PPA header from eMMC/SD and NAND Flash. Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Tested-by: Vinitha Pillai <vinitha.pillai@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-04-17armv8/fsl-layerscape: fdt: avoid incorrect fixing with CONFIG_SYS_CLK_FREQYangbo Lu
Current sysclk fixing would fix all clocks with 'fixed-clock' compatible. This patch is to fix sysclk by path to avoid any incorrect fixing. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-04-17armv8: fsl-lsch3: Instantiate TZASC configuration in 2 groupsAshish kumar
Number of TZASC instances may vary across NXP SoCs. So put TZASC configuration under instance specific defines. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-04-17armv8: ls2080a: Add serdes2 protocol 0x51 supportSantan Kumar
Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-04-17arm64/ls1046a: Enable ERRATUM_A008850 for ls1046a SoCShengzhou Liu
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-04-17armv8: ls1043a: Drop macro CONFIG_LS1043AYork Sun
Use CONFIG_ARCH_LS1043A instead. Signed-off-by: York Sun <york.sun@nxp.com>
2017-04-17armv8: ls2080a: Drop macro CONFIG_LS2080AYork Sun
Use CONFIG_ARCH_LS2080A instead. Signed-off-by: York Sun <york.sun@nxp.com>
2017-04-17arm: ls1043ardb: Add SD secure boot targetRuchika Gupta
- Add SD secure boot target for ls1043ardb. - Implement FSL_LSCH2 specific spl_board_init() to setup CAAM stream ID and corresponding stream ID in SMMU. - Change the u-boot size defined by a macro for copying the main U-Boot by SPL to also include the u-boot Secure Boot header size as header is appended to u-boot image. So header will also be copied from SD to DDR. - CONFIG_MAX_SPL_SIZE is limited to 90KB. SPL is copied to OCRAM (128K) where 32K are reserved for use by boot ROM and 6K for secure boto header. - Error messages during SPL boot are limited to error code numbers instead of strings to reduce the size of SPL image. Signed-off-by: Vinitha Pillai-B57223 <vinitha.pillai@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2017-04-17armv8: SECURE_BOOT: Enable chain of trust on LS1012A platformVinitha Pillai-B57223
Define bootscript and its header addresses for QSPI target Also add PPA header address in Kconfig Signed-off-by: Vinitha Pillai <vinitha.pillai@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
generated by cgit (git 2.34.1) at 2025-01-30 20:21:04 +0000