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2015-10-29armv8/ls1043a: Enable secondary coresHou Zhiqiang
After the secondary cores enter U-Boot, use CONFIG_ARMV8_MULTIENTRY to make secondary cores excute in spin loop. Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-29armv8/ls1043ardb: esdhc: Add esdhc support for ls1043ardbYangbo Lu
This patch adds esdhc support for ls1043ardb. Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-29armv8/ls1043a: Add Fman supportShaohui Xie
Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-29armv8/ls1043ardb: Add nand boot supportGong Qianyu
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-29armv8/ls1043ardb: Add LS1043ARDB board supportMingkai Hu
LS1043ARDB Specification: ------------------------- Memory subsystem: * 2GByte DDR4 SDRAM (32bit bus) * 128 Mbyte NOR flash single-chip memory * 512 Mbyte NAND flash * 16 Mbyte high-speed SPI flash * SD connector to interface with the SD memory card Ethernet: * XFI 10G port * QSGMII with 4x 1G ports * Two RGMII ports PCIe: * PCIe2 (Lanes C) to mini-PCIe slot * PCIe3 (Lanes D) to PCIe slot USB 3.0: two super speed USB 3.0 type A ports UART: supports two UARTs up to 115200 bps for console Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
2015-10-29armv8/fsl_lsch2: Add fsl_lsch2 SoCMingkai Hu
Freescale LayerScape with Chassis Generation 2 is a set of SoCs with ARMv8 cores and 2rd generation of Chassis. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-29armv8/fsl_lsch3: Change arch to fsl-layerscapeMingkai Hu
There are two LS series processors are built on ARMv8 Layersacpe architecture currently, LS2085A and LS1043A. They are based on ARMv8 core although use different chassis, so create fsl-layerscape to refactor the common code for the LS series processors which also paves the way for adding LS1043A platform. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-26armv8/fsl-lsch3: fdt: Check the pointer returned from call to a function may ↵Alison Wang
be NULL Pointer 'reg' returned from call to function 'fdt_getprop' may be NULL, will be passed to function and may be dereferenced there by passing argument 1 to function 'of_read_number'. So check pointer 'reg' first. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-15armv8/mmu: Set bits marked RES1 in TCRThierry Reding
For EL3 and EL2, the documentation says that bits 31 and 23 are reserved but should be written as 1. For EL1, only bit 23 is not reserved, so only write bit 31 as 1. Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-10-14Merge remote-tracking branch 'u-boot/master'Albert ARIBAUD
2015-09-16armv8: Make COUNTER_FREQUENCY optionalThierry Reding
Some platforms have the means to determine the counter frequency at runtime, so give them an opportunity to do so. Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2015-09-12arm: armv8 correct value passed to __asm_dcache_allPeng Fan
>From source code comments: "x0: 0 flush & invalidate, 1 invalidate only" Current value 0xffff can make invalidate work, since we only judge whether input value is 0 or not, see following code: " tbz w1, #0, 1f dc isw, x9 b 2f 1: dc cisw, x9 /* clean & invalidate by set/way */ 2: subs x6, x6, #1 /* decrement the way */ " Later we may add "2 clean only" support. So following the comments, correct value from 0xffff to 1. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: York Sun <yorksun@freescale.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
2015-09-01armv8: fsl-lsch3: Rewrite MMU translation table entriesAlison Wang
This patch rewrites MMU translation table entries. To start, all table entries are written as "invalid", then "device-ngnrnr" and "normal" are written to the entries to enable access to specific addresses. Signed-off-by: Alison Wang <alison.wang@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
2015-09-01armv8: fsl-lsch3: Initiaze 4 MACs per QSGMII in dpmac_infoPrabhakar Kushwaha
Every QSGMII SerDes Protocol usage 4 MACs. So add/repeat QSGMII information for 4 MACs in dpmac_info strucuture. Signed-off-by: King Chung Lo@freescale.com <KingChungLo@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-09-01armv8: ls2085a: Update serdes1_cfg_tbl for 0x33 & 0x35 protocolPrabhakar Kushwaha
Update 0x33 and 0x35 serdes protocol as per updated SoC document in array serdes1_cfg_tbl. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-09-01armv8: Add framework for CCN-504 interconnect configurationBhupesh Sharma
This patch adds a minimal framework for Dickens CCN-504 interconnect configuration - mainly related to adding Clusters/cores to snoop/DVM domain and setting QoS of the RN-I ports. LS2085A platform makes use of these configurations to support better network data performance and to boot a SMP Linux. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-08-19zynqmp: usb: Add usb dwc3 driver support for zynqmpSiva Durga Prasad Paladugu
Added usb dwc3 driver support for zynqmp this also supports the DFU and LTHOR to download the linux images on to RAM and cen be booted from those linux images. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-08-19ARM: zynqmp: Add platform specific arch_get_page_tableMichal Simek
Based on the patch: "armv8: caches: Added routine to set non cacheable region" (sha1: dad17fd51027ad02ac8f02deed186d08109d61fd) it is necessary to add platform specific hook. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-08-19zynqmp: Enable U-Boot run in EL3Michal Simek
Enable Secure IOU setup to enable U-Boot to run in EL3 without setting from ATF. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-08-12hisilicon: hi6220: Add a hi6220 pinmux driver.Peter Griffin
This patch adds basic pinmux support for the hi6220 SoC, which is found on the hikey board. Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
2015-08-12ARM: cache: implement a default weak flush_cache() functionWu, Josh
Current many cpu use the same flush_cache() function, which just call the flush_dcache_range(). So implement a weak flush_cache() for all the cpus to use. In original weak flush_cache() in arch/arm/lib/cache.c, there has some code for ARM1136 & ARM926ejs. But in the arch/arm/cpu/arm1136/cpu.c and arch/arm/cpu/arm926ejs/cache.c, there implements a real flush_cache() function as well. That means the original code for ARM1136 & ARM926ejs in weak flush_cache() of arch/arm/lib/cache.c is totally useless. So in this patch remove such code in flush_cache() and only call flush_dcache_range(). Signed-off-by: Josh Wu <josh.wu@atmel.com>
2015-08-12ARM: cache: add an empty stub function for invalidate/flush dcacheWu, Josh
Since some driver like ohci, lcd used dcache functions. But some ARM cpu don't implement the invalidate_dcache_range()/flush_dcache_range() functions. To avoid compiling errors this patch adds an weak empty stub function for all ARM cpu in arch/arm/lib/cache.c. And ARM cpu still can implemnt its own cache functions on the cpu folder. Signed-off-by: Josh Wu <josh.wu@atmel.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-31armv8: caches: Added routine to set non cacheable regionSiva Durga Prasad Paladugu
Added routine mmu_set_region_dcache_behaviour() to set a particular region as non cacheable. Define dummy routine for mmu_set_region_dcache_behaviour() to handle incase of dcache off. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
2015-07-29Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini
2015-07-28armv8/cache: Fix page table creationThierry Reding
While generating the page tables, a running integer index is shifted by SECTION_SHIFT (29) and causes overflow for any integer bigger than 7. The page tables therefore alias to the same 8 sections and cause U-Boot to hang once the MMU is enabled. Fix this by making the index a 64-bit unsigned integer and so avoid the overflow. swarren notes: currently "i" ranges from 0..8191 on all ARM64 boards, and "j" varies depending on RAM size; from 4 to 11 for a board with 4GB at physical address 2GB, as some Tegra boards have. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2015-07-28zynqmp: Add support for IP detection via SLCRMichal Simek
SLCR can be used for IP configuration setting. Add SLCR skeleton to enable run time checking. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28zynqmp: mp: Simplify set_r5_start handlingMichal Simek
Pass directly boot_addr which is LOVEC (0) or HIVEC (0xffff0000). No reason to use magic values 0 and 1. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28zynqmp: Define ep config for ZynqMPSiva Durga Prasad Paladugu
Define a new config "zynqmp_ep" for ZynqMP instead of xilinx_zynqmp. This defconfig supports all emulation platforms of ZynqMP. Also renamed TARGET_XILINX_ZYNQMP to ARCH_ZYNQMP. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-28zynqmp: Kconfig: Move zynqmp KconfigSiva Durga Prasad Paladugu
Move the zynqmp Kconfig from board to arch as there may be different boards under same architecture. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-07-20armv8/fsl-lsch3: Fix TCR_EL3 for the final MMU setup.Zhichun Hua
When final MMU table is setup in DDR, TCR attributes must match those of the memroy for cacheability and shareability. Signed-off-by: Zhichun Hua <zhichun.hua@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
2015-07-20armv8/ls2085a: Enable DSPI get input clk form 'mxc_get_clock'Haikun Wang
Signed-off-by: Haikun Wang <haikun.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-20armv8/fsl-lsch3: device tree fixups for PCI stream IDsStuart Yoder
This patch adds the infrastructure to update device tree nodes to convey SMMU stream IDs in the device tree. Fixups are implemented for PCI controllers initially. Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-20arm/errata: Update required bits for A57 cores erratasBhupesh Sharma
This patch updates the setting of required bits for A57 cores erratas - 828024 and 826974 Signed-off-by: Bhupesh Sharma <bhupesh.sharma at freescale.com> Signed-off-by: Dai Haruki <dai.haruki at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-20armv8/ls2085a: Update SoC README for DDR layoutPrabhakar Kushwaha
Update SoC README to provide details of - Memory regions - Memory used by MC and Debug server Signed-off-by: Bhupesh Sharma <bhupesh.sharma at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-20armv8/fsl-ch3: Add support to print SoC personalityPrabhakar Kushwaha
This patch adds support to print out the SoC personality. Freescale LS20xx SoCs (compliant to Chassis-3 specifications) can have 6 personalities: LS2045AE, LS2045A, LS2080AE, LS2080A, LS2085AE and LS2085A Signed-off-by: Bhupesh Sharma <bhupesh.sharma at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-07-20armv8/fsl-lsch3: Fix DDR speed messageYork Sun
DDR speed should be in MT/s, not MHz. Signed-off-by: York Sun <yorksun at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
2015-07-20armv8/ls2085a: call ft_pcie_setup() to change dts statusPrabhakar Kushwaha
call ft_pci_setup() to disable PCIe dts node if corresponding PCIe controller is disabled according to RCW Signed-off-by: Minghuan Lian <Minghuan.Lian at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
2015-04-29zynqmp: Add support for emulation platform - VeloceMichal Simek
Add support for Veloce - zynqmp emulation platform. Platform doesn't support SDHCI. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-04-29zynqmp: Add support for R5 sw loadingMichal Simek
Add support for loading sw for R5 with enabling for zynqmp. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
2015-04-29zynqmp: caches: Enable dcache for zynqmpSiva Durga Prasad Paladugu
Define the mmu table till 2MB granularity enable dcaches for zynqmp. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-04-23armv8/fsl-lsch3: Implement workaround for I2C erratum A009203York Sun
This erratum requires setting GLITCH_EN bit in debug register to enable digital filter to improve clock stability. Signed-off-by: York Sun <yorksun@freescale.com> CC: Heiko Schocher <hs@denx.de>
2015-04-23ls2085a: esdhc: Add esdhc support for ls2085aYangbo Lu
This patch adds esdhc support for ls2085a. Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
2015-04-23armv8/ls2085ardb: Enable NAND SPL supportScott Wood
Enable NAND boot support using SPL framework. To boot from NAND, either use DIP switches on board, or "qixis_reset nand" command. Details of forming NAND image can be found in README. Signed-off-by: Scott Wood <scottwood@freescale.com> [York Sun: Remove +S from defconfig after commit 252ed872] Signed-off-by: York Sun <yorksun@freescale.com>
2015-04-23armv8/ls2085aqds: NAND boot supportScott Wood
This adds NAND boot support for LS2085AQDS, using SPL framework. Details of forming NAND image can be found in README. Signed-off-by: Scott Wood <scottwood@freescale.com> [York Sun: Remove +S from defconfig after commit 252ed872] Signed-off-by: York Sun <yorksun@freescale.com>
2015-04-23driver/ifc: Add 64KB page supportJaiprakash Singh
IFC has two register pages.Till IFC version 1.4 each register page is 4KB each.But IFC ver 2.0 register page size is 64KB each.IFC regiters structure is break into two viz FCM and RUNTIME.FCM(Flash control machine) registers are defined in PAGE0 and controls IFC generic functionality. RUNTIME registers are defined in PAGE1 and controls NAND and GPCM funcinality. FCM and RUNTIME structures defination is common for IFC version 1.4 and 2.0. Signed-off-by: Jaiprakash Singh <b44839@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
2015-04-23armv8/ls2085ardb: Add support of LS2085ARDB platformYork Sun
The LS2085ARDB is a evaluation platform that supports LS2085A family SoCs. This patch add sbasic support for the platform. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
2015-04-23armv8/ls2085aqds: Add support of LS2085AQDS platformYork Sun
The LS2085AQDS is an evaluatoin platform that supports the LS2085A family SoCs. This patch add basic support of the platform. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
2015-04-23driver/ldpaa: Add support of WRIOP static data structurePrabhakar Kushwaha
Wire rate IO Processor (WRIOP) provide support of receive and transmit ethernet frames from the ethernet MAC. Here Each WRIOP block supports upto 64 DPMACs. Create a house keeping data structure to support upto 16 DPMACs and store external phy related information. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
2015-04-23armv8/fsl-ch3: Add support to print RCW configurationBhupesh Sharma
This patch adds support to print out the Reset Configuration Word information. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
2015-04-23drivers/fsl-mc: Changed MC firmware loading for new boot architectureJ. German Rivera
Changed MC firmware loading to comply with the new MC boot architecture. Flush D-cache hierarchy after loading MC images. Add environment variables "mcboottimeout" for MC boot timeout in milliseconds, "mcmemsize" for MC DRAM block size. Check MC boot status before calling flib functions. Signed-off-by: J. German Rivera <German.Rivera@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
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