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Call i2c initialization in spl_board_init only if I2C
is configured for the board.
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Tom Rini <tom.rini@gmail.com>
CC: Wolfgang Denk <wd@denx.de>
CC: Simon Schwarz <simonschwarzcor@gmail.com>
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Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Tom Rini <tom.rini@gmail.com>
CC: Wolfgang Denk <wd@denx.de>
CC: Simon Schwarz <simonschwarzcor@gmail.com>
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This only outputs "Assuming u-boot.bin..." if debug is active.
Signed-off-by: Simon Schwarz <simonschwarzcor@gmail.com>
CC: Tom Rini <tom.rini@gmail.com>
CC: Stefano Babic <sbabic@denx.de>
CC: Wolfgang Denk <wd@denx.de>
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This adds Linux booting to the SPL
This depends on CONFIG_MACH_TYPE patch by Igor Grinberg
(http://article.gmane.org/gmane.comp.boot-loaders.u-boot/105809)
Related CONFIGs:
CONFIG_SPL_OS_BOOT
Activates/Deactivates the OS booting feature
CONFIG_SPL_OS_BOOT_KEY
defines the IO-pin number u-boot switch - if pressed u-boot is
booted
CONFIG_SYS_NAND_SPL_KERNEL_OFFS
Offset in NAND of direct boot kernel image to use in SPL
CONFIG_SYS_SPL_ARGS_ADDR
Address where the kernel boot arguments are expected - this is
normaly RAM-begin + 0x100
Signed-off-by: Simon Schwarz <simonschwarzcor@gmail.com>
CC: Tom Rini <tom.rini@gmail.com>
CC: Stefano Babic <sbabic@denx.de>
CC: Wolfgang Denk <wd@denx.de>
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This implements booting of Linux from NAND in SPL
Related config parameters:
CONFIG_SYS_NAND_SPL_KERNEL_OFFS
Offset in NAND of direct boot kernel image to use in SPL
CONFIG_SYS_SPL_ARGS_ADDR
Address where the kernel boot arguments are expected - this is
normally RAM-start + 0x100 (on ARM)
Signed-off-by: Simon Schwarz <simonschwarzcor@gmail.com>
CC: Tom Rini <tom.rini@gmail.com>
CC: Stefano Babic <sbabic@denx.de>
CC: Wolfgang Denk <wd@denx.de>
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Change the parent UART clock to be PLL2, so that U-boot can also boot
a Freescale 2.6.35 kernel for mx53.
FSL kernel and U-boot changed the UART parent from PLL3 to PLL2 to avoid
conflicts with IPU clocks, so that the video resolution can be changed
without affecting the UART clock.
On a 2.6.35 kernel the serial console is messed up after IPU driver is loaded
and this patch fixes this problem.
Tested on a mx53loco board booting a FSL kernel and also a mainline kernel.
Reported-by: Otavio Salvador <otavio@ossystems.com.br>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
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Instead of hardcoding the mx6 silicon revision, read it in run-time.
Also, besides the silicon version print the mx6 variant type: quad,dual/solo
or solo-lite.
Tested on a mx6qsabrelite, where it shows:
CPU: Freescale i.MX6Q rev1.0 at 792 MHz
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Acked-by: Jason Liu <r64343@freescale.com>
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Instead of compiling the function and using the result as a constant, simply use
the constant.
NOTE: This patch works around bug:
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=52546
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@ti.com>
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Cut down the VDDIO/VDDA regulator stabilization delays to 500 uS. That should be
enough according to the datasheet and bootlets.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Robert Deliën <robert@delien.nl>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Matthias Fuchs <matthias.fuchs@esd.eu>
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After booting mx6qsabrelite from POR the following is reported:
CPU: Freescale i.MX61 family rev1.0 at 792 MHz
Reset cause: unknown reset
This is because both the POR and WDOG bits are set after reset.
Fix this by also checking both bits in the POR case.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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Enables all fourteen address lines for DRAM
Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
Tested-by: Marek Vasut <marek.vasut@gmail.com>
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Add missing reset reason 7 to get_reset_cause().
Signed-off-by: Helmut Raiger <helmut.raiger@hale.at>
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IxEthAcc.c: In function ‘ixEthAccInit’:
IxEthAcc.c:105:21: warning: comparison between ‘IxEthDBStatus’ and ‘enum <anonymous>’ [-Wenum-compare]
IxEthDBAPISupport.c: In function ‘ixEthDBPortAddressSet’:
IxEthDBAPISupport.c:633:18: warning: variable ‘ackPortAddressLock’ set but not used [-Wunused-but-set-variable]
IxQMgrDispatcher.c: In function ‘ixQMgrLLPShow’:
IxQMgrDispatcher.c:1194:18: warning: variable ‘q’ set but not used [-Wunused-but-set-variable]
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Bryan Hundven <bryanhundven@gmail.com>
Cc: Michael Schwingen <rincewind@discworld.dascon.de>
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Add -EB flag to LD to switch endianness of the linker. This should make armeb
targets buildable again. Also, make use of U-Boot's internal libgcc instead of
toolchain's one, this works around the use of libraries from GCC, which might be
little endian.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Bryan Hundven <bryanhundven@gmail.com>
Cc: Michael Schwingen <rincewind@discworld.dascon.de>
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Adds support for loading U-Boot from UART using YMODEM protocol.
If YMODEM support is enabled in SPL and the romcode indicates
that SPL loaded via UART then SPL will wait for start of a
YMODEM transfer via the console port.
Signed-off-by: Matt Porter <mporter@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
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Acked-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Tom Rini <trini@ti.com>
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This patch fixes erroneous 32-bit access to registers
hw_clkctrl_frac0 and hw_clkctrl_frac1.
Signed-off-by: Robert Delien <robert@delien.nl>
Acked-by: Marek Vasut <marex@denx.de>
Tested-by: Marek Vasut <marex@denx.de>
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This patch renames mx28_register to mx28_register_32 in order to
prepare for the introduction of an 8-bit register, mx28_register_8.
Signed-off-by: Robert Delien <robert@delien.nl>
Acked-by: Marek Vasut <marex@denx.de>
Tested-by: Marek Vasut <marex@denx.de>
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Reformat the data so it's easier to navigate through them.
Signed-off-by: Marek Vasut <marex@denx.de>
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Currently, only USB Host 1 is supported.
Cc: Remy Bohmer <linux@bohmer.net>
Signed-off-by: Wolfgang Grandegger <wg@denx.de>
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definitions
This patch replaces the use of magice numbers for scratch register
addresses with earlier defined register definitions.
Signed-off-by: Robert Delien <robert@delien.nl>
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Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
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Common code has a mdelay() func, so use that instead of the usb-specific
wait_ms() func. This also fixes the build errors:
ohci-hcd.c: In function 'submit_common_msg':
/usr/local/src/u-boot/blackfin/include/usb.h:202:44: sorry, unimplemented: inlining failed in call to 'wait_ms': function body not available
ohci-hcd.c:1519:9: sorry, unimplemented: called from here
/usr/local/src/u-boot/blackfin/include/usb.h:202:44: sorry, unimplemented: inlining failed in call to 'wait_ms': function body not available
ohci-hcd.c:1816:10: sorry, unimplemented: called from here
/usr/local/src/u-boot/blackfin/include/usb.h:202:44: sorry, unimplemented: inlining failed in call to 'wait_ms': function body not available
ohci-hcd.c:1827:10: sorry, unimplemented: called from here
/usr/local/src/u-boot/blackfin/include/usb.h:202:44: sorry, unimplemented: inlining failed in call to 'wait_ms': function body not available
ohci-hcd.c:1844:10: sorry, unimplemented: called from here
/usr/local/src/u-boot/blackfin/include/usb.h:202:44: sorry, unimplemented: inlining failed in call to 'wait_ms': function body not available
ohci-hcd.c:1563:11: sorry, unimplemented: called from here
/usr/local/src/u-boot/blackfin/include/usb.h:202:44: sorry, unimplemented: inlining failed in call to 'wait_ms': function body not available
ohci-hcd.c:1583:9: sorry, unimplemented: called from here
make[1]: *** [ohci-hcd.o] Error 1
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Acked-by: Marek Vasut <marex@denx.de>
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All boards are using the gen_atmel_mci driver now, so no need
to carry the old driver around.
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
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Boards can select either the 'built-in' parser or the hush parser. We
should not call builtin_run_command() if we are using the hush parser.
We use run_command() instead, since it knows how to call the correct
parser.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Mike Frysinger <vapier@gentoo.org>
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The current run_command() is only one of the parsing options - the other
is hush. We should not call run_command() when the hush parser is being
used. So we rename this function to better explain its purpose.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Mike Frysinger <vapier@gentoo.org>
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Signed-off-by: Thomas Weber <weber@corscience.de>
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Mainline kernel for OMAP3 doesn't enable L2 cache
It expects L2$ to be enabled by ROM-code/bootloader.
Leaving L2$ enabled can be troublesome in cases where
the L2 cache is not under CP15 control, such as in
Cortex-A9. This problem is explained in detail in
the commit dc7100f4080952798413fb63bb4134b22c57623a
However, this problem doesn't apply to Cortex-A8
because L2$ in Cortex-A8 is under CP15 control and
hence the generic armv7 maintenance opertions work
for it.
As such we can make an exception for OMAP3 and
leave the L2$ enabled when we jump to kernel. This
is done by removing the strongly-linked implementation
of v7_outer_cache_disable() and allowing it to fall
back to the weakly linked implementation that doesn't
do anything.
Signed-off-by: Aneesh V <aneesh@ti.com>
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davinci_dm6467Tevm
In commit 2d575e46859dd9127a9cec731ace77523e6ea2ab a separate header
file was introduced for the DM6467T EVM, include/configs/davinci_dm6467Tevm.h.
The substantial difference between the davinci_dm6467evm and the
davinci_dm6467Tevm configuration is a single bit in the hardware revision
that is passed to the Linux kernel and davinci_dm6467evm has
REFCLK_FREQ = 27000000 where as davinci_dm6467Tevm.h has a
REFCLK_FREQ = 33000000.
This patch removes include/configs/davinci_dm6467Tevm.h. Instead the
include/configs/davinci_dm6467evm.h configuration is used for DM6467T EVMs and
renamed CFG_REFCLK_FREQ to CONFIG_REFCLK_FREQ and CONFIG_REFCLK_FREQ is defined
in boards.cfg.
Signed-off-by: Prabhakar Lad <prabhakar.csengg@gmail.com>
Cc: Tom Rini <trini@ti.com>
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check for the return status for eth_getenv_enetaddr_by_index()
and eth_setenv_enetaddr() functions and print appropriate message
on failure.
Signed-off-by: Manjunath Hadli <manjunath.hadli@ti.com>
Cc: Tom Rini <trini@ti.com>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Wolfgang Denk <wd@denx.de>
Acked-by: Mike Frysinger <vapier@gentoo.org>
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CONFIG_DISPLAY_CPUINFO is selected
get_reset_cause() function is only used inside print_cpuinfo(), so let it be
defined only when CONFIG_DISPLAY_CPUINFO is selected.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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Signed-off-by: Stefano Babic <sbabic@denx.de>
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Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
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This patch fixes booting i.MX28 CPUs via USB download.
In this mode the CPU's bootrom implements a USB HID device that
accepts a bootstream.
When downloading the bootstream via USB, first the SPL code is
received and executed. Then the u-boot image is received and
called.
The USB bootmode is interrupt driven.
This patch fixes two things:
1) The ARM's fast interrupt mode is disabled when the SPL code
has been run. So save and restore the CPSR register.
2) Save and restore c1 control register: the exception vector
location needs to be set back to bootrom space to make the USB
interrupts work again. The SPL code needs to change this
option for the ram size probing.
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
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The DC power STS shouldn't be checked if booting off 5V supply.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Robert Deliën <robert@delien.nl>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Matthias Fuchs <matthias.fuchs@esd.eu>
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commit f31a911fe (arm, post: add missing post_time_ms for arm)
enables get_ticks and get_tbclk for all arm based boards,
MX5/MX6 have not yet implemented.
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Dirk Behme <dirk.behme@de.bosch.com>
CC: Jason Liu <jason.hui@linaro.org>
CC: Marek Vasut <marek.vasut@gmail.com>
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Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Helmut Raiger <helmut.raiger@hale.at>
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commit f31a911fe (arm, post: add missing post_time_ms for arm)
enables get_ticks and get_tbclk for all arm based boards,
MX5/MX6 have not yet implemented.
Signed-off-by: Stefano Babic <sbabic@denx.de>
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This patch moves hawkboard to the new spl infrastructure from the
older nand_spl one.
Removed the hawkboard_nand_config build option -- The spl code now
gets compiled with hawkboard_config, after building the main u-boot
image, using the CONFIG_SPL_TEXT_BASE. Modified the README.hawkboard
to reflect the same.
Signed-off-by: Sughosh Ganu <urwithsughosh@gmail.com>
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Christian Riesch <christian.riesch@omicron.at>
Cc: Sudhakar Rajashekhara <sudhakar.raj@ti.com>
Cc: Tom Rini <trini@ti.com>
Acked-by: Christian Riesch <christian.riesch@omicron.at>
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Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Acked-by: Heiko Schocher <hs@denx.de>
Tested-by: Heiko Schocher <hs@denx.de>
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The V bit of the c1 register of CP15 should not be cleared on DA850
SoCs since they have no valid memory at 0x00000000. This patch
introduces a configuration option CONFIG_SYS_EXCEPTION_VECTORS_HIGH
that allows setting the correct value for the V bit.
Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Reported-by: Sughosh Ganu <urwithsughosh@gmail.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Sughosh Ganu <urwithsughosh@gmail.com>
Cc: Heiko Schocher <hs@denx.de>
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The current implementation invalidates the data cache before turning it
off and causes problems on the hawkboard. See the discussion in
http://lists.denx.de/pipermail/u-boot/2012-January/115212.html
According to the ARM926EJ-S Technical Reference Manual, the cache should
be flushed instead.
Also fix the comments to match code.
Signed-off-by: Sughosh Ganu <urwithsughosh@gmail.com>
Rebased and corrected commit message.
Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Acked-by: Heiko Schocher <hs@denx.de>
Tested-by: Heiko Schocher <hs@denx.de>
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This patch reverts commit ca4b55800ed74207c35271bf7335a092d4955416
"arm, arm926ejs: always do cpu critical inits" since it impacts all
arm926ejs based configurations and caused problems, e.g., with
the hawkboard.
Instead the patch removes the CONFIG_SKIP_LOWLEVEL_INIT defines
from the board configurations that need low level initialization.
Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Heiko Schocher <hs@denx.de>
Acked-by: Heiko Schocher <hs@denx.de>
Tested-by: Heiko Schocher <hs@denx.de>
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The low level initialization code in
arch/arm/cpu/arm926ejs/davinci/lowlevel_init.S was written for
DM644X SoCs only. This patch makes the lowlevel_init function in this
file a dummy function for SoCs other than DM644X.
Signed-off-by: Christian Riesch <christian.riesch@omicron.at>
Cc: Tom Rini <trini@ti.com>
Cc: Sergey Kubushyn <ksi@koi8.net>
Acked-by: Heiko Schocher <hs@denx.de>
Tested-by: Heiko Schocher <hs@denx.de>
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We do not have thermal management or Smartreflex
enabled at U-Boot level. So, it's better to stick
to OPP100 for MPU instead of the OPP Turbo that is
used now. Adjust the VDD_MPU accordingly.
Tested-by: Sebastien Jan <s-jan@ti.com>
Signed-off-by: Aneesh V <aneesh@ti.com>
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add support for printing various clock frequency info found
in SOC such as ARM core frequency, DSP core frequency and DDR
frequency as part of bdinfo command.
Signed-off-by: Manjunath Hadli <manjunath.hadli@ti.com>
Cc: Tom Rini <trini@ti.com>
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remove the macro CONFIG_DISPLAY_CPUINFO as it is no longer
required. This is because clock info will be printed as part
'bdinfo' command and also remove support print_cpuinfo() as it will
no longer be called.
Signed-off-by: Manjunath Hadli <manjunath.hadli@ti.com>
Cc: Tom Rini <trini@ti.com>
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Signed-off-by: Peter Meerwald <p.meerwald@bct-electronic.com>
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usb dpll configuration is done only part of non-essential
dppl configuration however if CONFIG_USB_EHCI_OMAP is defined
we may have to configure usb dpll's for proper functioning
of usb modules. So move the usb dppl configuration to a new func.
and utilise the same during essential dpll configuration.
Signed-off-by: Govindraj.R <govindraj.raja@ti.com>
Tested-by: Stefano Babic <sbabic@denx.de>
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Adding ehci clock enabling mechanism part of clock framework.
When essential clocks are enabled during init phase usb host
clocks can also be enabled from clock framework.
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Govindraj.R <govindraj.raja@ti.com>
Tested-by: Stefano Babic <sbabic@denx.de>
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