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2014-09-13kconfig: remove redundant "string" type in arch and board KconfigsMasahiro Yamada
Now the types of CONFIG_SYS_{ARCH, CPU, SOC, VENDOR, BOARD, CONFIG_NAME} are specified in arch/Kconfig. We can delete the ones in arch and board Kconfig files. This commit can be easily reproduced by the following command: find . -name Kconfig -a ! -path ./arch/Kconfig | xargs sed -i -e ' /config[[:space:]]SYS_\(ARCH\|CPU\|SOC\|\VENDOR\|BOARD\|CONFIG_NAME\)/ { N s/\n[[:space:]]*string// } ' Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-09-12Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini
2014-09-09Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'Albert ARIBAUD
2014-09-08arm: ls102xa: Add Freescale LS102xA SoC supportWang Huan
The QorIQ LS1 family is built on Layerscape architecture, the industry's first software-aware, core-agnostic networking architecture to offer unprecedented efficiency and scale. Freescale LS102xA is a set of SoCs combines two ARM Cortex-A7 cores that have been optimized for high reliability and pack the highest level of integration available for sub-3 W embedded communications processors with Layerscape architecture and with a comprehensive enablement model focused on ease of programmability. Signed-off-by: Alison Wang <alison.wang@freescale.com> Signed-off-by: Jason Jin <jason.jin@freescale.com> Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2014-09-05arm: exynos: Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420Ajay Kumar
Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420 needed by exynos video driver. Also, configure ACLK_400_DISP1 as the parent for MUX_ACLK_400_DISP1_SUB_SEL. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-09-05arm: exynos: Add RPLL for Exynos5420Ajay Kumar
RPLL is needed to drive the LCD panel on Exynos5420 based boards. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-09-05odroid: kconfig: add odroid_defconfigPrzemyslaw Marczak
This config is valid for two devices: - Odroid X2, - Odroid U3. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Tom Rini <trini@ti.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-09-05arch:exynos: boot mode: add get_boot_mode(), code cleanupPrzemyslaw Marczak
This patch introduces code clean-up for exynos boot mode check. It includes: - removal of typedef: boot_mode - move the boot mode enum to arch-exynos/power.h - add bootmode for sequence: eMMC 4.4 ch4 / SD ch2 - add new function: get_boot_mode() for OM[5:1] pin check - update spl boot code Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Changes v5: - exynos: boot mode: add missing bootmode (1st:EMMC 4.4 / 2nd:SD ch2) Changes v6: - none changes v7: - change boot mode name: BOOT_MODE_MMC to BOOT_MODE_SD Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-09-05exynos: pinmux: fix the gpio names for exynos4x12 mmcPrzemyslaw Marczak
This change fixes the bad gpio configuration for the exynos dwmmc. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Beomho Seo <beomho.seo@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-09-04ARM: DRA72: DDR3: Add emif settings for 666MHz clockR Sricharan
On DRA72x, EMIF supports DDR3 upto 667MHz. Adding the required settings for DDR3 at 666MHz and enabling it. Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2014-09-04keystone2: use readl/writel functions instead of redefinitionKhoronzhuk, Ivan
There is no reason to redefine pure readl/writel functions. So remove this redundancy. Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> Acked-by: Vitaly Andrianov <vitalya@ti.com>
2014-09-04ARM: keystone: clock: use correct BWADJ field mask for PASSPLLCTL0Khoronzhuk, Ivan
The mask for BWADJ field of PASSPLLCTL0 register has to be 0xff, but by mistake, here is used shift instead of mask, so correct it. Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-08-30nomadik: kconfig: move board select menu and common settingsMasahiro Yamada
Becuase the board select menu in arch/arm/Kconfig is too big, move the Nomadik board select menu to nomadik/Kconfig. Move also common settings (CONFIG_SYS_CPU="arm926ejs" and CONFIG_SYS_SOC="nomadik"). Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-08-30highbank: kconfig: move common settingsMasahiro Yamada
Move Highbank-specific settings to highbank/Kconfig. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Rob Herring <robh@kernel.org>
2014-08-30orion5x: kconfig: move board select menu and common settingsMasahiro Yamada
Becuase the board select menu in arch/arm/Kconfig is too big, move the Orion5x board select menu to orion5x/Kconfig. Move also common settings (CONFIG_SYS_CPU="arm926ejs" and CONFIG_SYS_SOC="orion5x"). Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
2014-08-30keystone: kconfig: move board select menu and common settingsMasahiro Yamada
Becuase the board select menu in arch/arm/Kconfig is too big, move the Keystone board select menu to keystone/Kconfig. Move also common settings (CONFIG_SYS_CPU="armv7" and CONFIG_SYS_SOC="keystone"). Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Reviewed-by: Tom Rini <trini@ti.com> Cc: Vitaly Andrianov <vitalya@ti.com>
2014-08-30omap5: kconfig: move board select menu and common settingsMasahiro Yamada
Becuase the board select menu in arch/arm/Kconfig is too big, move the OMAP5 board select menu to omap5/Kconfig. Move also common settings (CONFIG_SYS_CPU="armv7" and CONFIG_SYS_SOC="omap5"). Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Reviewed-by: Tom Rini <trini@ti.com> Cc: Lokesh Vutla <lokeshvutla@ti.com>
2014-08-30omap4: kconfig: move board select menu and common settingsMasahiro Yamada
Becuase the board select menu in arch/arm/Kconfig is too big, move the OMAP4 board select menu to omap4/Kconfig. Move also common settings (CONFIG_SYS_CPU="armv7" and CONFIG_SYS_SOC="omap4"). Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Reviewed-by: Tom Rini <trini@ti.com> Cc: Lokesh Vutla <lokeshvutla@ti.com>
2014-08-30omap3: kconfig: move board select menu and common settingsMasahiro Yamada
Becuase the board select menu in arch/arm/Kconfig is too big, move the OMAP3 board select menu to omap3/Kconfig. Move also common settings (CONFIG_SYS_CPU="armv7" and CONFIG_SYS_SOC="omap3 Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Reviewed-by: Tom Rini <trini@ti.com>
2014-08-30davinci: kconfig: move board select menu and common settingsMasahiro Yamada
Becuase the board select menu in arch/arm/Kconfig is too big, move the Davinci board select menu to davinci/Kconfig. Move also common settings (CONFIG_SYS_CPU="arm926ejs" and CONFIG_SYS_SOC="davinci"). Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Reviewed-by: Tom Rini <trini@ti.com> Cc: Heiko Schocher <hs@denx.de> Cc: Sandeep Paulraj <s-paulraj@ti.com>
2014-08-30exynos: kconfig: move board select menu and common settingsMasahiro Yamada
Becuase the board select menu in arch/arm/Kconfig is too big, move the Exynos board select menu to exynos/Kconfig. Consolidate also common settings (CONFIG_SYS_CPU="armv7" and CONFIG_SYS_SOC="exynos"). Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Minkyu Kang <mk7.kang@samsung.com>
2014-08-30kirkwood: kconfig: refactor Kconfig and defconfigMasahiro Yamada
Becuase the board select menu in arch/arm/Kconfig is too big, move the KirkWood board select menu to kirkwood/Kconfig. Consolidate also common settings (CONFIG_SYS_CPU="arm926ejs" and CONFIG_SYS_SOC="kirkwood"). Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Prafulla Wadasdkar <prafulla@marvell.com> Cc: Luka Perkov <luka@openwrt.org>
2014-08-30versatile: kconfig: move common settingsMasahiro Yamada
Move Versatile-specific settings to versatile/Kconfig. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-08-30rmobile: kconfig: move board select menu and common settingsMasahiro Yamada
Becuase the board select menu in arch/arm/Kconfig is too big, move the Rmobile board select menu to rmobile/Kconfig. Consolidate also common settings (CONFIG_SYS_CPU="armv7" and CONFIG_SYS_SOC="rmobile"). Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2014-08-30tegra: kconfig: move board select menu and common settingsMasahiro Yamada
Becuase the board select menu in arch/arm/Kconfig is too big, move the Tegra board select menu to tegra/Kconfig. Insert the Tegra SoC select menu between the arch select and the board select. Architecture select |-- Tegra Platform (Tegra) |- Tegra SoC select (Tegra20 / 30 / 114 / 124) |- Board select Consolidate also common settings (CONFIG_SYS_CPU="armv7" and CONFIG_SYS_SOC="tegra*") and always "select" CONFIG_SPL as follows: config TEGRA bool select SPL Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Stephen Warren <swarren@nvidia.com> Cc: Tom Warren <twarren@nvidia.com>
2014-08-30zynq: kconfig: move board select menu and common settingsMasahiro Yamada
Becuase the board select menu in arch/arm/Kconfig is too big, move the Zynq board select menu to zynq/Kconfig. Consolidate also common settings (CONFIG_SYS_CPU="armv7" and CONFIG_SYS_SOC="zynq"). Refactor board/xilinx/zynq/MAINTAINERS too. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Tested-by: Michal Simek <michal.simek@xilinx.com>
2014-08-30arm: Add missing .vectors section to linker scriptsBenoît Thébaudeau
Commit 41623c9 'arm: move exception handling out of start.S files' missed some linker scripts. Hence, some boards no longer had exception handling linked since this commit. Restore the original behavior by adding the .vectors section to these linker scripts. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau.dev@gmail.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
2014-08-30arm: bcmnsp: Add bcmnsp u-architectureScott Branden
Base support for the Broadcom NSP SoC. Based on iproc-common and the SoC specific reset function. Signed-off-by: Scott Branden <sbranden@broadcom.com> Signed-off-by: Steve Rae <srae@broadcom.com>
2014-08-30arm: bcmcygnus: Add bcmcygnus u-architectureScott Branden
Base support for the Broadcom Cygnus SoC. Based on iproc-common and the SoC specific reset function. Signed-off-by: Scott Branden <sbranden@broadcom.com> Signed-off-by: Steve Rae <srae@broadcom.com>
2014-08-30arm: iproc: Initial commit of iproc architecture codeScott Branden
The iproc architecture code is present in several Broadcom chip architectures, including Cygnus and NSP. Signed-off-by: Scott Branden <sbranden@broadcom.com> Signed-off-by: Steve Rae <srae@broadcom.com>
2014-08-30arm: bcm281xx: Add Ethernet Clock supportJiandong Zheng
Enable Ethernet clock when Broadcom StarFighter2 Ethernet block (CONFIG_BCM_SF2_ETH) is enabled. Signed-off-by: Jiandong Zheng <jdzheng@broadcom.com> Signed-off-by: Steve Rae <srae@broadcom.com>
2014-08-30arm: ep9315: Add .vectors section to lds and remove obsolete ldsSergey Kostanbaev
However ep9315 don't use interrupt vectors during startup, but _startup symbol is used inside uboot to calculate actual monitor size. Signed-off-by: Sergey Kostanbaev <sergey.kostanbaev@gmail.com> Cc: albert.u.boot@aribaud.net
2014-08-30socfpga: initialize designware ethernetPavel Machek
Enable initialization fo designware ethernet controller. With this patch, ethernet works in my configuration, provided I set ethernet address in the environment. Signed-off-by: Pavel Machek <pavel@denx.de>
2014-08-29socfpga: Fix SOCFPGA build error for Altera dev kitChin Liang See
To fix the build error when build for Altera dev kit, not virtual target. At same time, set the build for Altera dev kit as default instead virtual target. With that, U-Boot is booting well and SPL still lack of few drivers. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Pavel Machek <pavel@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
2014-08-29socfpga: fix clock manager register definitionPavel Machek
Structure defining clock manager hardware was wrong, leading to wrong registers being accessed and hang in MMC init. This fixes structure to match hardware. Signed-off-by: Pavel Machek <pavel@denx.de>
2014-08-29Merge branch 'master' of git://git.denx.de/u-boot-tiTom Rini
2014-08-29Merge branch 'zynq' of git://www.denx.de/git/u-boot-microblazeTom Rini
2014-08-29Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini
2014-08-29Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini
2014-08-25ARM: DRA: Enable VTT regulatorLokesh Vutla
DRA7 evm REV G and later boards uses a vtt regulator for DDR3 termination and this is controlled by gpio7_11. Configuring gpio7_11. The pad A22(offset 0x3b4) is used by gpio7_11 on REV G and later boards, and left unused on previous boards, so it is safe enough to enable gpio on all DRA7 boards. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2014-08-25ARM: DRA7: Enable software leveling for dra7Sricharan R
Currently hw leveling is enabled by default on DRA7/72. But the hardware team suggested to use sw leveling as hw leveling is not characterized and seen some test case failures. So enabling sw leveling on all DRA7 platforms. Signed-off-by: Sricharan R <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2014-08-25keystone2: use EFUSE_BOOTROM information to configure PLLsVitaly Andrianov
This patch reads EFUSE_BOOTROM register to see the maximum supported clock for CORE and TETRIS PLLs and configure them accordingly. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-08-20mx6sx: Adjust enable_fec_anatop_clock() for mx6soloxFabio Estevam
Configure and enable the ethernet clock for mx6solox. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
2014-08-20ARM: mx6: Handle the MMDCx_MDCTL COL field capricesMarek Vasut
The COL field value cannot be easily calculated from the desired column number. Instead, there are special cases for that, see the datasheet, MMDCx_MDCTL field description, field COL . Cater for those special cases. Signed-off-by: Marek Vasut <marex@denx.de>
2014-08-20mx6: add support of multi-processor commandGabriel Huau
This allows u-boot to load different OS or Bare Metal application on different cores of the i.MX6 SoC. For example: running Android on cpu0 and a RT OS like QNX/FreeRTOS on cpu1. Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr> Acked-by: Stefano Babic <sbabic@denx.de>
2014-08-19ARM: zynq: Remove spl.hMichal Simek
Do not specify own zynq specific SPL macros because there is no need for that. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-08-18ARM: tegra: Use mem size from MC rather than ODMDATAStephen Warren
In at least Tegra124, the Tegra memory controller (MC) has a register that controls the memory size. Read this to determine the memory size rather than requiring this to be redundantly encoded into the ODMDATA. This way, changes to the BCT (i.e. MC configuration) automatically updated SW's view of the memory size, without requiring manual changes to the ODMDATA. Future work potentially required: * Clip the memory size to architectural limits; U-Boot probably doesn't and won't support either LPAE or Tegra's "swiss cheese" memory layout, at least one of which would be required for >2GB RAM. * Subtract out any carveout required by firmware on future SoCs. Based-on-work-by: Tom Warren <twarren@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-08-18ARM: tegra: Disable VPRBryan Wu
On Tegra114 and Tegra124 platforms, certain display-related registers cannot be accessed unless the VPR registers are programmed. For bootloader, we probably don't care about VPR, so we disable it (which counts as programming it, and allows those display-related registers to be accessed). This patch is based on the commit 5f499646c83ba08079f3fdff6591f638a0ce4c0c in Chromium OS U-Boot project. Signed-off-by: Andrew Chew <achew@nvidia.com> Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com> Signed-off-by: Bryan Wu <pengw@nvidia.com> [acourbot: ensure write went through, vpr.c style changes] Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Cc: Tom Warren <TWarren@nvidia.com> Cc: Stephen Warren <swarren@nvidia.com> Cc: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
2014-08-12sunxi: dram: Autodetect DDR3 bus width and densitySiarhei Siamashka
In the case if the 'dram_para' struct does not specify the exact bus width or chip density, just use a trial and error method to find a usable configuration. Because all the major bugs in the DRAM initialization sequence are now hopefully fixed, it should be safe to re-initialize the DRAM controller multiple times until we get it configured right. The original Allwinner's boot0 bootloader also used a similar autodetection trick. The DDR3 spec contains the package pinout and addressing table for different possible chip densities. It appears to be impossible to distinguish between a single chip with 16 I/O data lines and a pair of chips with 8 I/O data lines in the case if they provide the same storage capacity. Because a single 16-bit chip has a higher density than a pair of equivalent 8-bit chips, it has stricter refresh timings. So in the case of doubt, we assume that 16-bit chips are used. Additionally, only Allwinner A20 has all A0-A15 address lines and can support densities up to 8192. The older Allwinner A10 and Allwinner A13 can only support densities up to 4096. We deliberately leave out DDR2, dual-rank configurations and the special case of a 8-bit chip with density 8192. None of these configurations seem to have been ever used in real devices. And no new devices are likely to use these exotic configurations (because only up to 2GB of RAM can be populated in any case). This DRAM autodetection feature potentially allows to have a single low performance fail-safe DDR3 initialiazation for a universal single bootloader binary, which can be compatible with all Allwinner A10/A13/A20 based devices (if the ifdefs are replaced with a runtime SoC type detection). Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2014-08-12sunxi: dram: Derive write recovery delay from DRAM clock speedSiarhei Siamashka
The write recovery time is 15ns for all JEDEC DDR3 speed bins. And instead of hardcoding it to 10 cycles, it is possible to set tighter timings based on accurate calculations. For example, DRAM clock frequencies up to 533MHz need only 8 cycles for write recovery. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Hans de Goede <hdegoede@redhat.com>