summaryrefslogtreecommitdiff
path: root/arch/arm/cpu
AgeCommit message (Collapse)Author
2013-04-12arm: relocate_code(): Remove useless relocation offset computationBenoît Thébaudeau
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-04-12arm1136: Remove redundant relocate_code() returnBenoît Thébaudeau
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-04-12arm: relocate_code() is no longer noreturnBenoît Thébaudeau
Commit e05e5de7fae5bec79617e113916dac6631251156 made ARM's relocate_code() return to its caller, but it did not update its declaration accordingly. Fixing this function declaration fixes dropped C code following calls to relocate_code(). Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
2013-04-12arm: start.S: Fix _TEXT_BASE for SPLBenoît Thébaudeau
_TEXT_BASE must be set to CONFIG_SPL_TEXT_BASE for generic SPL, and to CONFIG_SYS_TEXT_BASE for non-SPL builds. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Reviewed-by: Tom Rini <trini@ti.com>
2013-04-12imx: mx5: lowlevel_init: Simplify codeBenoît Thébaudeau
Don't use several instructions to build constant values. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Acked-by: Stefano Babic <sbabic@denx.de>
2013-04-08OMAP3/4/5/AM33xx: Correct logic for checking FAT or RAW MMCTom Rini
In the case of booting from certain peripherals, such as UART, we must not see what the device descriptor says for RAW or FAT mode because in addition to being nonsensical, it leads to a hang. This is why we have a test currently for the boot mode being within range. The problem however is that on some platforms we get MMC2_2 as the boot mode and not the defined value for MMC2, and in others we get the value for MMC2_2. This is required to fix eMMC booting on omap5_uevm. Tested on am335x_evm (UART, NAND, SD), omap3_beagle (NAND, SD on classic, SD only on xM rev C5) and omap5_uevm (SD, eMMC). Signed-off-by: Tom Rini <trini@ti.com>
2013-04-08arm: omap4: Fix SDRAM AUTO DETECTIONLokesh Vutla
Commit "8602114 omap: emif: configure emif only when required" breaks SDRAM_AUTO_DETECTION. The issue is dmm_init() depends on emif_sizes[](SDRAM Auto detection) done in do_sdram_init(). The above commit moves dmm_init() above do_sdram_init() because of which dmm_init() uses uninitialized emif_sizes[]. So instead of using global emif_sizes[], get sdram details locally and calculate emif sizes. Reported-by: Michael Cashwell <mboards@prograde.net> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2013-04-08OMAP: Fix copy-paste bug that did not enable UART4 clockLubomir Popov
V2 fixes line wrap issue of the patch itself. UART3 was enabled twice instead of UART4. One more cosmetic change in a comment on EMIF clock. Signed-off-by: Lubomir Popov <lpopov@mm-sol.com> Reviewed-by: R Sricharan <r.sricharan@ti.com>
2013-04-08omap2420-h4: Fix get_timer() and CONFIG_SYS_HZHunter, Jon
The function get_timer() should return time in ms and CONFIG_SYS_HZ should be set to 1000 by default. Fix both of these items. Signed-off-by: Jon Hunter <jon-hunter@ti.com>
2013-04-08omap_gpmc: change nandecc commandAndreas Bießmann
With uppcoming BCH support on OMAP devices we need to decide between differnt algorithms when switching the ECC engine. Currently we support 1-bit hammign and 8-bit BCH on HW backend. In order to switch between differnet ECC algorithms we need to change the interface of omap_nand_switch_ecc() also. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Cc: Tom Rini <trini@ti.com> Cc: Thomas Weber <thomas.weber.linux@googlemail.com>
2013-04-08asm/omap_gpmc.h: consolidate common definesAndreas Bießmann
arch/arm/include/asm/arch-am33xx/omap_gpmc.h and arch/arm/include/asm/arch-omap3/omap_gpmc.h are almost the same, consolidate the common parts into a new header. Introduce a new asm/omap_gpmc.h which defines the command part and pulls in the architecture specific one. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Cc: Tom Rini <trini@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
2013-04-08am335x: Enable MMC1 clockTom Rini
We must not assume ROM has enabled the clock for MMC1. Reported-by: Koen Kooi <koen@dominion.thruhere.net> Signed-off-by: Tom Rini <trini@ti.com> Acked-by: Peter Korsgaard <jacmet@sunsite.dk>
2013-04-04Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'Albert ARIBAUD
2013-04-04Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD
2013-04-04ARM: bcm2835: fix get_timer() to return msStephen Warren
Apparently, CONFIG_SYS_HZ must be 1000. Change this, and fix the timer driver to conform to this. Have the timer implementation export a custom API get_timer_us() for use by the BCM2835 MMC API, which needs us resolution for a HW workaround. Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
2013-04-03mx6: Fix get_board_rev() for the mx6 solo caseFabio Estevam
When booting a Freescale kernel 3.0.35 on a Wandboard solo, the get_board_rev() returns 0x62xxx, which is not a value understood by the VPU (Video Processing Unit) library in the kernel and causes the video playback to fail. The expected values for get_board_rev are: 0x63xxx: For mx6quad/dual 0x61xxx: For mx6dual-lite/solo So adjust get_board_rev() accordingly and make it as weak function, so that we do not need to define it in every mx6 board file. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Dirk Behme <dirk.behme@de.bosch.com> Acked-by: Eric Nelson <eric.nelson@boundarydevices.com>
2013-04-01Exynos: pwm: Remove dead code of function exynos5_get_pwm_clkAkshay Saraswat
As we shall now be using clock_get_periph_rate function. We find no reason for keeping code in function exynos5_get_pwm_clk. Hence, removing it. Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-04-01Exynos: pwm: Use generic api to get pwm clk freqPadmavathi Venna
Use generic api to get the pwm clock frequency Test with command "sf probe 1:0; time sf read 40008000 0 1000". Try with different numbers of bytes and see that sane values are obtained Build and boot U-boot with this patch, backlight works properly. Signed-off-by: Padmavathi Venna <padma.v@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-04-01Exynos: clock: Add generic api to get the clk freqPadmavathi Venna
Add generic api to get the frequency of the required peripherial. This API gets the source clock frequency and returns the required frequency by dividing with first and second dividers based on the requirement. Test with command "sf probe 1:0; time sf read 40008000 0 1000". Try with different numbers of bytes and see that sane values are obtained Build and boot U-boot with this patch, backlight works properly. Signed-off-by: Padmavathi Venna <padma.v@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-04-01Exynos: Tidy up the pwm_config function in the exynos pwm driverGabe Black
Some small fixes in the exynos pwm driver: 1. NS_IN_HZ is non-sensical since these are not compatible units. This constant actually describes the number of nanoseconds in a second. Renamed it to NS_IN_SEC. Also dropped the unnecessary parenthesis. 2. The variable "period" is not used to hold a period, it's used to hold a frequency. Renamed it to "frequency". 3. tcmp is an unsigned value, so (tcmp < 0) will never be true and the if which checks that condition will never execute. Also, there should be no problem if the pwm never switches, so there's no reason to subtract one from tcmp and therefore no reason to compare it against zero. Removed both ifs. If they weren't removed, tcmp should be a signed value. 4. Add a check for a 0 period. Test with command "sf probe 1:0; time sf read 40008000 0 1000". Try with different numbers of bytes and see that sane values are obtained Build and boot U-boot with this patch, backlight works properly. Signed-off-by: Gabe Black <gabeblack@google.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-04-01Exynos: Avoid a divide by zero by specifying a non-zero period for pwm 4Gabe Black
The pwm_config function in the exynos pwm driver divides by its period period parameter. A function was calling pwm_config with a 0ns period and a 0ns duty cycle. That doesn't actually make any sense physically, and results in a divide by zero in the driver. This change changes the parameters to be a 100000ns period and duty cycle. Test with command "sf probe 1:0; time sf read 40008000 0 1000". Try with different numbers of bytes and see that sane values are obtained Build and boot U-boot with this patch, backlight works properly. Signed-off-by: Gabe Black <gabeblack@google.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-04-01Exynos: pwm: Fix two bugs in the exynos pwm configuration codeGabe Black
First, the "div" value was being used incorrectly to compute the frequency of the PWM timer. The value passed in is a constant which reflects the value that would be found in a configuration register, 0 to 4. That should correspond to a scaling factor of 1, 2, 4, 8, or 16, 1 << div, but div + 1 was being used instead. Second, the reset value of the timers were being calculated to give an overall frequency, thrown out, and set to a maximum value. This was done so that PWM 4 could be used as the system clock by counting down from a high value, but it was applied indiscriminantly. It should at most be applied only to PWM 4. This change also takes the opportunity to tidy up the pwm_init function. Test with command "sf probe 1:0; time sf read 40008000 0 1000". Try with different numbers of bytes and see that sane values are obtained Build and boot U-boot with this patch, backlight works properly. Signed-off-by: Gabe Black <gabeblack@google.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-04-01Exynos: Add timer_get_us functionChe-Liang Chiou
timer_get_us returns the time in microseconds since a certain reference point of history. However, it does not guarantee to return an accurate time after a long period; instead, it wraps around (that is, the reference point is reset to some other point of history) after some periods. The frequency of wrapping around is about an hour (or 2^32 microseconds). Test with command "sf probe 1:0; time sf read 40008000 0 1000". Try with different numbers of bytes and see that sane values are obtained Signed-off-by: Che-Liang Chiou <clchiou@chromium.org> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-04-01Exynos: Change get_timer() to work correctlySimon Glass
At present get_timer() does not return sane values. It should count up smoothly in milliscond intervals. We can change the PWM to count down at 1MHz, providing a resolution of 1us and a range of about an hour between required get_timer() calls. Test with command "sf probe 1:0; time sf read 40008000 0 1000". Try with different numbers of bytes and see that sane values are obtained Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-03-28armv7: do not relocate _start twiceVincent Stehlé
The _start symbol is already relocated, so do not add the relocation the second time in c_runtime_cpu_setup. This fixes e.g. the abort exception handling path, which ended in double fault due to bad address in VBAR. Signed-off-by: Vincent Stehlé <v-stehle@ti.com> Reported-by: Lubomir Popov <lpopov@mm-sol.com>
2013-03-28ARM: mmu: Set domain permissions to client accessR Sricharan
The 'XN' execute never bit is set in the pagetables. This will prevent speculative prefetches to non executable regions. But the domain permissions are set as master in the DACR register. So the pagetable attribute for 'XN' is not effective. Change the permissions to client. This fixes lot of speculative prefetch aborts seen on OMAP5 secure devices. Signed-off-by: R Sricharan <r.sricharan@ti.com> Tested-by: Vincent Stehle <v-stehle@ti.com> Cc: Vincent Stehle <v-stehle@ti.com> Cc: Tom Rini <trini@ti.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
2013-03-27EXYNOS5: Add L2 Cache Support.Rajeshwari Shinde
This patch set adds L2 Cache Support to EXYNOS. Signed-off-by: Arun Mankuzhi <arun.m@samsung.com> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2013-03-26Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'Albert ARIBAUD
2013-03-24Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'Albert ARIBAUD
2013-03-24ti814x_evm: add ti814x evm board supportMatt Porter
Add TI814X EVM board directory, config file, and MAINTAINERS entry. Enable build. Signed-off-by: Matt Porter <mporter@ti.com> Reviewed-by: Tom Rini <trini@ti.com> [trini: Adapt to recent omap_hsmmc requirements, Matt re-tested] Signed-off-by: Tom Rini <trini@ti.com>
2013-03-24am33xx: add dmm support to emif4 libraryMatt Porter
Adds a config_dmm() routine to support TI814X DMM configuration. Signed-off-by: Matt Porter <mporter@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
2013-03-24am33xx: add ti814x specific register definitionsMatt Porter
Support the ti814x specific register definitions within arch-am33xx. Signed-off-by: Matt Porter <mporter@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
2013-03-24am33xx: refactor am33xx clocks and add ti814x supportMatt Porter
Split clock.c for am335x and ti814x and add ti814x specific clock support. Signed-off-by: Matt Porter <mporter@ti.com>
2013-03-24am33xx: refactor emif4/ddr to support multiple EMIF instancesMatt Porter
The AM33xx emif4/ddr support closely matches what is need to support TI814x except that TI814x has two EMIF instances. Refactor all the emif4 helper calls and the config_ddr() init function to use an additional instance number argument. Signed-off-by: Matt Porter <mporter@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
2013-03-24am33xx: convert defines from am33xx-specific to generic namesMatt Porter
Eliminate AM33xx specific names to prepare for TI814x support within AM33xx-land. Signed-off-by: Matt Porter <mporter@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
2013-03-24am33xx: Add required includes to some omap/am33xx codeTom Rini
- In arch/arm/cpu/armv7/omap-common/timer.c, drivers/mtd/nand/omap_gpmc.c and drivers/net/cpsw.c add #include files that the driver needs but had been relying on <config.h> to bring in. - In arch/arm/cpu/armv7/omap-common/lowlevel_init.S add <config.h> - In am335x_evm.h and pcm051.h don't globally include <asm/arch/hardware.h> and <asm/arch/cpu.h> but just <asm/arch/omap.h> as that is the only include which defines things the config uses. Cc: Lars Poeschel <poeschel@lemonage.de> Signed-off-by: Tom Rini <trini@ti.com>
2013-03-24ARM: AM33XX: Fix typo that causes an AM duplication in CPU name.Enric Balletbo i Serra
Just fix a typo displaying the CPU info. With CONFIG_DISPLAY_INFO we see something like AMAM335X-GP rev 0 instead of AM335X-GP rev 0. Signed-off-by: Enric Balletbo i Serra <eballetbo@iseebcn.com> Reviewed-by: Javier Martinez Canillas <javier@dowhile0.org>
2013-03-22ARM: implement erratum 716044 workaroundStephen Warren
Add common code to enable the workaround for ARM erratum 716044. This will be enabled for Tegra. Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-03-22am33xx:ddr:Fix config_sdram to work for all DDRSteve Kipisz
The original write to sdram_config is correct for DDR3 but incorrect for DDR2 so SPL was hanging. For DDR2, the write to sdram_config should be after the writes to ref_ctrl. This was working for DDR3 because there was a write of 0x2800 to ref_ctrl before a write to sdram_config. Tested on: GP EVM 1.1A (DDR2), GP EVM 1.5A (DDR3), Beaglebone A6 (DDR2), Beagleone Blacd A4A (DDR3) Signed-off-by: Steve Kipisz <s-kipisz2@ti.com>
2013-03-22Initialise correct GPMC WAITx irq for AM33xxMark Jackson
Currently WAIT0 irq is reset and then WAIT1 irq is enabled. Fix it such that WAIT0 irq is enabled instead. Signed-off-by: Mark Jackson <mpfj@newflow.co.uk> Acked-by: Peter Korsgaard <jacmet@sunsite.dk>
2013-03-20ARM: bcm2835: add mailbox driverStephen Warren
The BCM2835 SoC contains (at least) two CPUs; the VideoCore (a/k/a "GPU") and the ARM CPU. The ARM CPU is often thought of as the main CPU. However, the VideoCore actually controls the initial SoC boot, and hides much of the hardware behind a protocol. This protocol is transported using the SoC's mailbox hardware module. Here, we add a very simplistic driver for the mailbox module, and define a few structures for the property messages. Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
2013-03-20mxs: spl_mem_init: Align DDR2 init with FSL bootlets sourceFabio Estevam
Currently the following kernel hang happens when loading a 2.6.35 kernel from Freeescale on a mx28evk board: RPC: Registered tcp transport module. RPC: Registered tcp NFSv4.1 backchannel transport module. Bus freq driver module loaded IMX usb wakeup probe usb h1 wakeup device is registered mxs_cpu_init: cpufreq init finished ... Loading the same kernel using the bootlets from the imx-bootlets-src-10.12.01 package, the hang does not occur. Comparing the DDR2 initialization from the bootlets code against the U-boot one, we can notice some mismatches, and after applying the same initialization into U-boot the 2.6.35 kernel can boot normally. Also tested with 'mtest' command, which runs succesfully. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Otavio Salvador <otavio@ossystems.com.br> Tested-by: Marek Vasut <marex@denx.de>
2013-03-18Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini
Albert's rework of the linker scripts conflicted with Simon's making everyone use __bss_end. We also had a minor conflict over README.scrapyard being added to in mainline and enhanced in u-boot-arm/master with proper formatting. Conflicts: arch/arm/cpu/ixp/u-boot.lds arch/arm/cpu/u-boot.lds arch/arm/lib/Makefile board/actux1/u-boot.lds board/actux2/u-boot.lds board/actux3/u-boot.lds board/dvlhost/u-boot.lds board/freescale/mx31ads/u-boot.lds doc/README.scrapyard include/configs/tegra-common.h Build tested for all of ARM and run-time tested on am335x_evm. Signed-off-by: Tom Rini <trini@ti.com>
2013-03-15Replace __bss_end__ with __bss_endSimon Glass
Note this is a tree-wide change affecting multiple architectures. At present we use __bss_start, but mostly __bss_end__. This seems inconsistent and in a number of places __bss_end is used instead. Change to use __bss_end for the BSS end symbol throughout U-Boot. This makes it possible to use the asm-generic/sections.h file on all archs. Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-15Merge branch 'u-boot-tegra/master' into 'u-boot-arm/master'Albert ARIBAUD
2013-03-15Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD
2013-03-14Tegra114: Dalmore: Add pad config tables/code based on pinmux codeTom Warren
Pad config registers exist in APB_MISC_GP space, and control slew rate, drive strengh, schmidt, high-speed, and low-power modes for all of the pingroups in Tegra30. This builds off of the pinmux way of constructing init tables to configure select pads (SDIOCFG, for instance) during pinmux_init(). Currently, no padcfg entries exist. SDIO3CFG will be added when the MMC driver is added as per the TRM to work with the SD-card slot on Dalmore E1611. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
2013-03-14Tegra114: pinmux: Fix bad CAM_MCLK func 3 table entryTom Warren
This caused CAM_MCLK's pinmux reg to be locked out, since the table parsing code couldn't find a matching entry for VI_ALT3 and wrote garbage to the register. Signed-off-by: Tom Warren <twarren@nvidia.com>
2013-03-14Tegra30: Cardhu: Add pad config tables/code based on pinmux codeTom Warren
Pad config registers exist in APB_MISC_GP space, and control slew rate, drive strengh, schmidt, high-speed, and low-power modes for all of the pingroups in Tegra30. This builds off of the pinmux way of constructing init tables to configure select pads (SDIOCFG, for instance) during pinmux_init(). Currently, only SDIO1CFG is changed as per the TRM to work with the SD-card slot on Cardhu. Thanks to StephenW for the suggestion/original idea. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
2013-03-14Tegra114: pinmux: Update pinmux tables & code, fix a bug w/SDMMC3 initTom Warren
Use the latest tables & code from our internal U-Boot repo. The SDMMC3_CD, CLK_LB_IN and CLK_LB_OUT offsets in the pingroup table were off by a few indices, causing the pinmux init code to write bad data to the PINMUX_AUX_ regs. This also enabled the lock bit, which made it impossible to reconfig the pads correctly for SDMMC3 (SD card on Dalmore) operation. Also fixes SPI_CS2_N, USB_VBUS_EN0, HDMI_CEC and UART2_RXD/TXD muxes. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>