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2014-10-06arm: socfpga: misc: Align print_cpuinfo() outputPavel Machek
Cosmetic change to the print_cpuinfo() function output. Align the output with the rest of initial output produced by U-Boot. Signed-off-by: Pavel Machek <pavel@denx.de> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de>
2014-10-06arm: socfpga: misc: Add SD controller initPavel Machek
Add CPU function to register and initialize the dw_mmc SD controller. This allows us to use the HPS SDMMC block. Signed-off-by: Pavel Machek <pavel@denx.de> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de>
2014-10-06arm: socfpga: misc: Add proper ethernet initializationPavel Machek
Add function to initialize the EMAC blocks upon board startup. The preprocessor guards against building on SoCFPGA-VT and against SPL build are not needed as those are handled implicitly via both SPL framework and the socfpga_cyclone5.h config file, which will not define CONFIG_DESIGNWARE_ETH if building for SoCFPGA-VT. We cannot handle two EMAC ethernet blocks yet, therefore the ifdefs. Once there is hardware using both EMAC blocks, this ifdef will have to go. Signed-off-by: Pavel Machek <pavel@denx.de> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de>
2014-10-06arm: socfpga: reset: Add EMAC reset functionsMarek Vasut
Add functions to reset the EMAC ethernet blocks. We cannot handle two EMAC ethernet blocks yet, therefore the ifdefs. Once there is hardware using both EMAC blocks, this ifdef will have to go. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
2014-10-06arm: socfpga: timer: Pull the timer reload value from config fileMarek Vasut
The timer reload value is a property of the timer hardware and there is no reason for this to be configurable. Place this into the timer driver just like on the other hardware. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Pavel Machek <pavel@denx.de>
2014-10-06arm: socfpga: clock: Sync with reference codeMarek Vasut
Add the missing pieces from the reference clock code from Altera. This puts the code on par with the Altera U-Boot fork for all but the SDRAM self-refresh bits, which are not part of this patch. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
2014-10-06arm: socfpga: clock: Clean up bit definitionsMarek Vasut
Clean up the clock code definitions so they are aligned with mainline standards. There are no functional changes in this patch. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
2014-10-06arm: socfpga: clock: Trim down code duplicationMarek Vasut
Pull out functions to read frequency of Main clock VCO and PLL clock VCO as the code is duplicated multiple times. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Pavel Machek <pavel@denx.de>
2014-10-06arm: socfpga: clock: Add code to read clock configurationPavel Machek
Add the entire bulk of code to read out clock configuration from the SoCFPGA CPU registers. This is important for MMC, QSPI and UART drivers as otherwise they cannot determine the frequency of their upstream clock. Signed-off-by: Pavel Machek <pavel@denx.de> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> V2: Fixed the L4 MP clock divider and synced the clock code with latest rocketboards codebase (thanks Dinh for pointing this out)
2014-10-06arm: socfpga: clock: Drop nonsense inlining from clock manager codeMarek Vasut
The inlining is done by GCC when needed, there is no need to do it explicitly. Furthermore, the inline keyword does not force-inline the code, but is only a hint for the compiler. Scrub this hint. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Pavel Machek <pavel@denx.de>
2014-10-06arm: socfpga: sysmgr: Clean up system managerMarek Vasut
Clean up the system manager register definition and add the missing register definitions in place. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
2014-10-06arm: socfpga: Add watchdog disable for socfpgaPavel Machek
This adds watchdog disable. It is neccessary for running Linux kernel. Signed-off-by: Pavel Machek <pavel@denx.de> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> V2: Move RSTMGR_PERMODRST_L4WD0_LSB to reset_manager.h Reset watchdog only if CONFIG_HW_WATCHDOG is undefined (the default)
2014-10-05ARM: UniPhier: add Kconfig and defconfigMasahiro Yamada
This commit allows to build Panasonic UniPhier family: PH1-LD4, PH1-Pro4, PH1-sLD8 Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-10-05ARM: UniPhier: add UniPhier SoC support codeMasahiro Yamada
These are used by Panasonic UniPhier SoC family. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-09-29imx: mx6: Checking PLL2 PFD0 and PFD2 for periph_clk before PFD resetYe.Li
Checking the pre_periph_clk_sel and pre_periph2_clk of CCM CBCMR register, if the PLL2 PFD0 or PLL2 PFD2 is used for the clock source, do not reset this PFD to avoid system hang. Customers may set this in DDR script or use BT_FREQ to select low freq boot. Signed-off-by: Ye.Li <B37916@freescale.com>
2014-09-29arm: mxs: Wait for DRAM to startMarek Vasut
Instead of waiting for a fixed period of time and hoping for the best that the DRAM will start, read back an EMI status register which tells us exactly when the DRAM started. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
2014-09-29arm: mxs: Wait when disabling VDDMEM current limiterMarek Vasut
According to i.MX23 datasheet Table 32-17, we must wait for the supply to settle before disabling the current limiter. Indeed, not waiting a little here causes the system to crash at times. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
2014-09-26Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini
2014-09-25armv8/fsl-lsch3: Release secondary cores from boot hold off with Boot PageYork Sun
Secondary cores need to be released from holdoff by boot release registers. With GPP bootrom, they can boot from main memory directly. Individual spin table is used for each core. Spin table and the boot page is reserved in device tree so OS won't overwrite. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
2014-09-25kconfig: move CONFIG_OF_* to KconfigMasahiro Yamada
This commit moves: CONFIG_OF_CONTROL CONFIG_OF_SEPARATE CONFIG_OF_EMBED CONFIG_OF_HOSTFILE Because these options are currently not supported for SPL, the "Device Tree Control" menu does not appear in the SPL configuration. Note: zynq-common.h should be adjusted so as not to change the default value of CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Simon Glass <sjg@chromium.org> Cc: Stephen Warren <swarren@nvidia.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
2014-09-24cosmetic: replace MIN, MAX with min, maxMasahiro Yamada
The macro MIN, MAX is defined as the aliase of min, max, respectively. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-09-22imx: Support i.MX6 High Assurance Boot authenticationNitin Garg
When CONFIG_SECURE_BOOT is enabled, the signed images like kernel and dtb can be authenticated using iMX6 CAAM. The added command hab_auth_img can be used for HAB authentication of images. The command takes the image DDR location, IVT (Image Vector Table) offset inside image as parameters. Detailed info about signing images can be found in Freescale AppNote AN4581. Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
2014-09-22Merge branch 'master' of git://git.denx.de/u-boot-armStefano Babic
2014-09-21Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'Albert ARIBAUD
2014-09-19ARM: atmel: use pcr to enable or disable peripheral clockBo Shen
When use pcr (peripheral control register), then we won't need to care about the peripheral ID. Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2014-09-17ARM: keystone: ddr3: workaround for ddr3a/3b memory issueMurali Karicheri
This patch implements a workaround to fix DDR3 memory issue. The code for workaround detects PGSR0 errors and then preps for and executes a software-controlled hard reset.In board_early_init, where logic has been added to identify whether or not the previous reset was a PORz. PLL initialization is skipped in the case of a software-controlled hard reset. Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Keegan Garcia <kgarcia@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-09-17Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini
2014-09-16kconfig: armv8: move CONFIG_ARM64 to KconfigMasahiro Yamada
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-09-16arm: mx35: use common timer functionsAndrew Ruder
This patch moves mx35 to the common timer functions added in commit 8dfafdd - Introduce common timer functions <Rob Herring> The (removed) mx35 timer code (specifically __udelay()) could deadlock at the 32-bit boundary of get_ticks(). get_ticks() returned a 32-bit value cast up to a 64-bit value. If get_ticks() + tmo in __udelay() crossed the 32-bit boundary, the while condition became unconditionally true and locks the processor. Rather than patch the specific mx35 issues, simply move everything over to the common code. Signed-off-by: Andrew Ruder <andrew.ruder@elecsyscorp.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
2014-09-16arm: mx31: use common timer functionsAndrew Ruder
This patch moves mx31 to the common timer functions added in commit 8dfafdd - Introduce common timer functions <Rob Herring> The (removed) mx31 timer code (specifically __udelay()) could deadlock at the 32-bit boundary of get_ticks(). get_ticks() returned a 32-bit value cast up to a 64-bit value. If get_ticks() + tmo in __udelay() crossed the 32-bit boundary, the while condition became unconditionally true and locks the processor. Rather than patch the specific mx31 issues, simply move everything over to the common code. Signed-off-by: Andrew Ruder <andrew.ruder@elecsyscorp.com> Cc: Marek Vasut <marex@denx.de> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Wolfgang Denk <wd@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Helmut Raiger <helmut.raiger@hale.at>
2014-09-13kconfig: remove redundant "string" type in arch and board KconfigsMasahiro Yamada
Now the types of CONFIG_SYS_{ARCH, CPU, SOC, VENDOR, BOARD, CONFIG_NAME} are specified in arch/Kconfig. We can delete the ones in arch and board Kconfig files. This commit can be easily reproduced by the following command: find . -name Kconfig -a ! -path ./arch/Kconfig | xargs sed -i -e ' /config[[:space:]]SYS_\(ARCH\|CPU\|SOC\|\VENDOR\|BOARD\|CONFIG_NAME\)/ { N s/\n[[:space:]]*string// } ' Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-09-12Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini
2014-09-11imx: Fix build of mx6sxsabresdStefano Babic
Commit 224beb833e544b802f08765271cec07667d39669 add clock enabling function for FEC, but the masks are not available for SX processor and the mx6sxsabresd cannot be built clean. Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Fabio Estevam <fabio.estevam@freescale.com> CC: Nikita Kiryanov <nikita@compulab.co.il>
2014-09-09pcie_imx: Add mx6solox supportFabio Estevam
Let PCI on mx6solox also be supported. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de>
2014-09-09mx6: Fix ECSPI typo in soc_boot_modesNikolay Dimitrov
Signed-off-by: Nikolay Dimitrov <picmaster@mail.bg> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Anatolij Gustschin <agust@denx.de>
2014-09-09iMX6: Disable the L2 before chaning the PL310 latencyYe.Li
The Latency parameters of PL310 Tag RAM latency control register and Data RAM Latency control register are set in L2 cache enable. And setting these registers must have PL310 NOT enabled. But when using Plugin mode boot, the PL310 is enabled by bootrom. The patch disables the PL310 before applying this setting. Signed-off-by: Ye.Li <Ye.Li@freescale.com>
2014-09-09arm: mx6: ddr: fix cs0_end calculationNikita Kiryanov
Current way of calculation CS0_END field for MMDCx_MDASP register is problematic because in most cases the user is forced to define cs_density in an unnatural way: as value - 2, instead of value. This breaks the abstraction provided by struct mx6_ddr_sysinfo because the user is forced to be aware of the way the calculation is performed. Refactor the calculation. Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
2014-09-09arm: mx6: ddr: configure MMDC for slow_pdNikita Kiryanov
According to MX6 TRM, both MMDC and DRAM should be configured to the same powerdown precharge. Currently, mx6_dram_cfg() configures MMDC for fast pd (MDPDC[7] = 0), and the DRAM for 'slow exit (DLL off)' (MR0[12] = 0). Configure MMDC for slow pd. Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Cc: Igor Grinberg <grinberg@compulab.co.il> Acked-by: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Acked-by: Tim Harvey <tharvey@gateworks.com>
2014-09-09arm: mx6: ddr: do not write into reserved bitNikita Kiryanov
Bit 16 in mapsr register is in a reserved field. Don't write to it. Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Acked-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
2014-09-09arm: mx6: ddr: cleanupNikita Kiryanov
No functional changes. Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Acked-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
2014-09-09mx6: add clock enabling functionsNikita Kiryanov
Add functions to enable/disable clocks for UART, SPI, ENET, and MMC. Cc: Stefano Babic <sbabic@denx.de> Cc: Igor Grinberg <grinberg@compulab.co.il> Acked-by: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
2014-09-09Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'Albert ARIBAUD
2014-09-08arm: ls102xa: Add Freescale LS102xA SoC supportWang Huan
The QorIQ LS1 family is built on Layerscape architecture, the industry's first software-aware, core-agnostic networking architecture to offer unprecedented efficiency and scale. Freescale LS102xA is a set of SoCs combines two ARM Cortex-A7 cores that have been optimized for high reliability and pack the highest level of integration available for sub-3 W embedded communications processors with Layerscape architecture and with a comprehensive enablement model focused on ease of programmability. Signed-off-by: Alison Wang <alison.wang@freescale.com> Signed-off-by: Jason Jin <jason.jin@freescale.com> Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
2014-09-05arm: exynos: Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420Ajay Kumar
Add get_lcd_clk and set_lcd_clk callbacks for Exynos5420 needed by exynos video driver. Also, configure ACLK_400_DISP1 as the parent for MUX_ACLK_400_DISP1_SUB_SEL. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-09-05arm: exynos: Add RPLL for Exynos5420Ajay Kumar
RPLL is needed to drive the LCD panel on Exynos5420 based boards. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-09-05odroid: kconfig: add odroid_defconfigPrzemyslaw Marczak
This config is valid for two devices: - Odroid X2, - Odroid U3. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Tom Rini <trini@ti.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-09-05arch:exynos: boot mode: add get_boot_mode(), code cleanupPrzemyslaw Marczak
This patch introduces code clean-up for exynos boot mode check. It includes: - removal of typedef: boot_mode - move the boot mode enum to arch-exynos/power.h - add bootmode for sequence: eMMC 4.4 ch4 / SD ch2 - add new function: get_boot_mode() for OM[5:1] pin check - update spl boot code Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Changes v5: - exynos: boot mode: add missing bootmode (1st:EMMC 4.4 / 2nd:SD ch2) Changes v6: - none changes v7: - change boot mode name: BOOT_MODE_MMC to BOOT_MODE_SD Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-09-05exynos: pinmux: fix the gpio names for exynos4x12 mmcPrzemyslaw Marczak
This change fixes the bad gpio configuration for the exynos dwmmc. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Beomho Seo <beomho.seo@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2014-09-04ARM: DRA72: DDR3: Add emif settings for 666MHz clockR Sricharan
On DRA72x, EMIF supports DDR3 upto 667MHz. Adding the required settings for DDR3 at 666MHz and enabling it. Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2014-09-04keystone2: use readl/writel functions instead of redefinitionKhoronzhuk, Ivan
There is no reason to redefine pure readl/writel functions. So remove this redundancy. Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> Acked-by: Vitaly Andrianov <vitalya@ti.com>
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