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2019-01-24arm64: zynqmp: Move SoC sources to mach-zynqmpMichal Simek
Similar changes was done for Zynq in past and this patch just follow this pattern to separate cpu code from SoC code. Move arch/arm/cpu/armv8/zynqmp/* -> arch/arm/mach-zynqmp/* And also fix references to these files. Based on "ARM: zynq: move SoC sources to mach-zynq" (sha1: 0107f2403669f764ab726d0d404e35bb9447bbcc) Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-24arm64: zynqmp: Do not protect zynqmp_pmufw_version()Michal Simek
There is hard dependency for CLK_ZYNQMP to have zynqmp_pmufw_version() but also FPGA code is calling this function which is possible to use without actual CLK_ZYNQMP firmware driver to be enabled. This patch enables the case where only fixed-clock CLK setup is used. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-17armv8: ls1043a: correct the PCIe INTx fixupHou Zhiqiang
On LS1043A rev1.0 there are 4 interrupt pins for INTx, and on rev1.1 there is only 1 for INTx, so the current fixup is inverse of the fact. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2019-01-17armv8: ls1043a: add SVR definitions for 23x23 package siliconHou Zhiqiang
LS1043A/LS1023A 23x23 package silicon has different SVR:VAR_PER. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2019-01-17armv8: ls2088ardb: Add TFABOOT supportRajesh Bhagat
TFABOOT support includes: - ls2088ardb_tfa_defconfig to be loaded by trusted firmware - environment address and size changes for TFABOOT - define BOOTCOMMAND for TFABOOT - remove EL3 specific erratas for TFABOOT Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2019-01-17armv8: ls1088ardb: Add TFABOOT supportPankit Garg
TFABOOT support includes: - ls1088ardb_tfa_defconfig to be loaded by trusted firmware - environment address and size changes for TFABOOT - MC address changes for TFABOOT - define BOOTCOMMAND for TFABOOT - ifc chip select changes for TFABOOT Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2019-01-17armv8: fsl-layerscape: fixes for TFABOOT frameworkRajesh Bhagat
Fixes for TFABOOT framework - update eMMC bootsrc to SD_MMC - Increase buffer size for mcinitcmd from 256 to 512 - Fix mcinitcmd and bootcmd for Secure Boot Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2019-01-01watchdog: imx: add config to disable wdog resetXiaoliang Yang
Add Kconfig option WATCHDOG_RESET_DISABLE to disable watchdog reset in imx_watchdog driver, so that the watchdog will not be fed in u-boot if CONFIG_WATCHDOG_RESET_DISABLE is enabled. Signed-off-by: Xiaoliang Yang <xiaoliang.yang_1@nxp.com>
2019-01-01watchdog: driver support for fsl-lsch2Xiaoliang Yang
Support watchdog driver for fsl-lsch2. It's disabled in default. If you want to use it, please enable CONFIG_IMX_WATCHDOG. Define CONFIG_WATCHDOG_TIMEOUT_MSECS to set watchdog timeout. Signed-off-by: Xiaoliang Yang <xiaoliang.yang_1@nxp.com>
2018-12-06armv8: lx2160a: Add LX2160A SoC SupportPriyanka Jain
LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06armv8:fsl-layerscape: Add support for Chassis 3.2Priyanka Jain
NXP layerscape architecture Chassis 3.2 builds upon chassis3 architecture with changes like DDR Memory map change, removal of IFC and support of upto 8 I2C controller. Patch add README.lsch3_2 and the above changes under macro CONFIG_NXP_LSCH3_2. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06armv8: lsch3: Add support of serdes3 modulePriyanka Jain
Some lsch3 based SoCs like lx2160a contains three serdes modules. Add support for third serdes protocol in lsch3 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06armv8: fsl-layerscape: add support of MC framework for TFAPankit Garg
Add support of MC framework for TFA Make MC framework independent of boot source. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06armv8: sec_firmware: return job ring status as true in TFABOOTPankit Garg
Returns job ring status as true in TFABOOT, as one job ring is always reserved. Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06armv8: sec_firmware: change el2_to_aarch32 SMC IDRajesh Bhagat
Changes the el2_to_aarch32 SMC ID from 0xc000ff04 to 0xc200ff17, it is applicable to both TFA and non-TFA boot. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06armv8: fsl-layerscape: Update parsing boot sourceYork Sun
Workaround of erratum A010539 clears the RCW source field in PORSR1 register, causing failure of detecting boot source using this method. Use SMC call if U-Boot runs at EL2. If SMC is not implemented or running at EL3, continue to read PORSR1 and presume QSPI as boot source if erratum workaround A010539 is enabled and RCW source is cleared. Signed-off-by: York Sun <york.sun@nxp.com>
2018-12-06armv8: layerscape: skip OCRAM init for TFABOOTRajesh Bhagat
OCRAM initialization is performed by TFA, Hence skipped from u-boot. Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06armv8: layerscape: add SMC calls for DDR size and bank infoRajesh Bhagat
Adds SMC calls for getting DDR size and bank info for TFABOOT. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06armv8: fsl-layerscape: bootcmd identification for TFABOOTPankit Garg
Adds bootcmd identificaton on basis on boot source, valid in TFABOOT configuration. Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> [YS: remove unnecessary braces] Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06armv8: layerscape: remove EL3 specific erratas for TFABOOTRajesh Bhagat
Removes EL3 specific erratas for TFABOOT, And now taken care in TFA. ARM_ERRATA_855873, SYS_FSL_ERRATUM_A008850, SYS_FSL_ERRATUM_A008511, SYS_FSL_ERRATUM_A008336, SYS_FSL_ERRATUM_A009663, SYS_FSL_ERRATUM_A009803, SYS_FSL_ERRATUM_A009942, SYS_FSL_ERRATUM_A010165 Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06armv8: fsl-layerscape: identify boot source from PORSR registerRajesh Bhagat
PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06armv8: layerscape: Add TFABOOT supportRajesh Bhagat
Adds TFABOOT support config option and add generic code to enable execution from DDR. Signed-off-by: York Sun <york.sun@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
2018-12-06armv8: fsl-layerscape: change tlb base from OCRAM to DDR in EL < 3Pankit Garg
Change tlb base address from OCRAM to DDR when exception level is less than 3. Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-12-06armv8: layerscape: Enable routing SError exceptionYork Sun
In case SError happens at EL2, if SCR_EL3[EA] is not routing it to EL3, and SCR_EL3[RW] is set to aarch64, setting HCR_EL2[AMO] routes the exception to EL2. Otherwise this exception is not taken. Signed-off-by: York Sun <york.sun@nxp.com>
2018-12-04move data structure out of cpu.hYork Sun
Move static definitions to cpu.c file, as it doesn't allow the cpu.h file to be included in multiple c files. Signed-off-by: York Sun <york.sun@nxp.com>
2018-12-02efi_loader: PSCI reset and shutdownHeinrich Schuchardt
When an operating system started via bootefi tries to reset or power off this is done by calling the EFI runtime ResetSystem(). On most ARMv8 system the actual reset relies on PSCI. Depending on whether the PSCI firmware resides the hypervisor (EL2) or in the secure monitor (EL3) either an HVC or an SMC command has to be issued. The current implementation always uses SMC. This results in crashes on systems where the PSCI firmware is implemented in the hypervisor, e.g. qemu-arm64_defconfig. The logic to decide which call is needed based on the device tree is already implemented in the PSCI firmware driver. During the EFI runtime the device driver model is not available. But we can minimize code duplication by merging the EFI runtime reset and poweroff code with the PSCI firmware driver. As the same HVC/SMC problem is also evident for the ARMv8 do_poweroff and reset_misc routines let's move them into the same code module. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Alexander Graf <agraf@suse.de>
2018-11-26ARM: armv7: Add early stack for erratum workaroundsAndrew F. Davis
Some erratum workarounds call into C code before the stack is setup, this can lead to values pushed onto the stack being lost, firewall exceptions, and other undefined behavior. Setup a temporary stack to allow these functions to work correctly. Signed-off-by: Andrew F. Davis <afd@ti.com> Acked-by: Andreas Dannenberg <dannenberg@ti.com> Reviewed-by: Nishanth Menon <nm@ti.com>
2018-11-16ARMv8: SError exception handling in PSCI exception vectorsChee Hong Ang
Allow platform vendors to handle SError interrupt exceptions from ARMv8 PSCI exception vectors by overriding this weak function 'plat_error_handler'. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
2018-11-16ARMv8: Add EL3 exception handling for ARMv8's KconfigChee Hong Ang
Kconfig option to allow all External Abort and SError exception taken to EL3. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
2018-10-19arm: lpc32xx: remove phantom CONFIG_LPC32XX_SDRAM_ config optionVladimir Zapolskiy
The option has never existed and config whitelist script accumulates it from a comment block, wipe it out from the source code. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2018-10-19arm: lpc32xx: add CONFIG_ARCH_LPC32XX build optionVladimir Zapolskiy
The explicit arch specific build symbol allows to group supported boards, generalize common config options and it will serve as a dependency for platform only drivers. Two related board defconfigs are resynced after the change. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
2018-10-16arm64: zynqmp: Add new command for TCM initializationSiva Durga Prasad Paladugu
This patch adds new zynqmp command "zynqmp tcminit mode" to initialize TCM. TCM needs to be initialized before accessing to avoid ECC errors. This new command helps to perform the same. It also makes tcm_init() as global and uses it for doing the TCM initialization. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-10-16arm64: zynqmp: Move TCM initialization to a separate routineSiva Durga Prasad Paladugu
This patch moves TCM initialization to a separate routine to make it modular and can be reused if required. It also prints warning message now as it writes to TCM. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-10-10arm: remove prototype for get_timer_maskedPatrick Delaunay
The interruption support had be removed for ARM architecture and the function get_timer_masked() is no more used except in some the timer.c files. This patch clean each timer.c which implement this function and remove the associated prototype in u-boot-arm.h For timer.c, I don't verify if the weak version of get_timer (in lib/time.c) can be used Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-10-10arm: remove prototype for udelay_maskedPatrick Delaunay
The interruption support had be removed for ARM architecture and the function udelay_masked() is no more used except in some timer.c files and have the same content than udelay() or __udelay(). This patch update each timer.c implementing this function and remove the associated prototype in u-boot-arm.h. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-10-10arm: remove prototype for reset_timer_maskedPatrick Delaunay
Remove prototype for function only used in one file Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2018-09-29Merge tag 'fsl-qoriq-for-v2018.11-rc1' of git://git.denx.de/u-boot-fsl-qoriqTom Rini
Switch to driver model for eSDHC on Layerscape SoCs including LS1021A, LS1043A, LS1046A, LS1088A, LS2088A. Switch to driver model for SATA on LS1021A and LS1043A. Add support for LS1012AFRWY rev C board. Enable SMMU for LS1043A.
2018-09-27armv7: ls102xa: Disable QE before enter deep sleepRan Wang
Otherwise system will hang after executing wfi. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-09-27armv8: ls1043a: add icid setup supportLaurentiu Tudor
Reuse the existing ICID setup code done for LS1046A smmu enablement and add the equivalent setup for LS1043A chips. Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-09-27armv7: fsl: remove sata supportPeng Ma
Remove the old implementation in order to enable DM for sata Signed-off-by: Peng Ma <peng.ma@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-09-27armv8/ls1088a/ls2088a: esdhc: Add esdhc clock supportYinbo Zhu
This patch adds esdhc clock support for ls1088a and ls2088a. Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
2018-09-27ppa/fm/qe: use block layer in ppa/fm/qe driverYinbo Zhu
At present the MMC subsystem maintains its own list of MMC devices. This cannot work with driver model when CONFIG_BLK is enabled, use blk_dread to replace previous mmc read interface, use mmc_get_blk_desc to get the mmc device property. Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com> [York S: reformatted commit message] Reviewed-by: York Sun <york.sun@nxp.com>
2018-09-27Merge tag 'xilinx-for-v2018.11' of git://git.denx.de/u-boot-microblazeTom Rini
Xilinx changes for v2018.11 - Handle BOARD_LATE_INIT via Kconfig SPL: - Enable GZIP for all partitions types(not only for kernel) ZynqMP: - Rearrange pmufw version handling - Support newer PMUFW with improved fpga load sequence Zynq: - Cleanup config file - Simplify zybo config by enabling option via Kconfig net: - Fix gems max-speed property reading - Enable support for fixed-link phys
2018-09-26Merge tag 'signed-efi-next' of git://github.com/agraf/u-bootTom Rini
Patch queue for efi - 2018-09-26 A lot of goodness in this release. We're *very* close to running the UEFI Shell and SCT natively. The only missing piece are HII protocols. - FAT write support (needed for SCT) - improved FAT directory support (needed for SCT) - RTC support with QEMU -M virt - Sandbox support (run UEFI binaries in Linux - yay) - Proper UTF-16 support - EFI_UNICODE_COLLATION_PROTOCOL support (for UEFI Shell) - EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL support (for UEFI Shell) - Fix window size determination - Fix Tegra by explicitly unmapping RAM - Clean up handle entanglement - Lots of generic code cleanup [trini: Fixup merge conflict in include/configs/qemu-arm.h] Signed-off-by: Tom Rini <trini@konsulko.com>
2018-09-26arm64: zynqmp: Return pmufw version for zynqmp_pmufw_version()Siva Durga Prasad Paladugu
Modify the zynqmp_pmufw_version() routine to return PMUFW version so that it can be reused wherever required. Get PMUFW version from PMU only once at bootup and later just return stored value. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-09-26arm64: zynqmp: Move PM version related macros to .hSiva Durga Prasad Paladugu
This patch moves the PM version related macros to .h file so that they can be reused in other files. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-09-25arm: spear: enable SSP1, 2 and 3 clocks when SPI controller driver is builtQuentin Schulz
SPI controllers SSP1, 2 and 3 require to enable their respective clocks. Let's enable them only when the SPI controller driver is built. Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com>
2018-09-23efi_loader: simplify ifdefsStephen Warren
Use CONFIG_IS_ENABLED(EFI_LOADER) to avoid explicitly checking CONFIG_SPL too. This simplifies the conditional. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2018-09-10arm: spear: enable GPIO3 and 4 clocks when the GPIO controller driver is builtQuentin Schulz
There are multiple GPIOs that can be used with the same driver depending on the CONFIG_GPIO_BASE defined in the controller driver. GPIO3 and 4 require a clock to be enabled so let's enable them when the driver is built. Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com>
2018-09-10ARM: CPU: arm926ejs: Consolidate cache routines to common fileAdam Ford
Four different boards had different options for enabling cache that were virtually all the same. This consolidates these common functions into arch/arm/cpu/arm926ejs/cache.c This also has the positive side-effect of enabling cache on the Davinci (da850) boards. Signed-off-by: Adam Ford <aford173@gmail.com> [trini: Add mach-at91 to the list of consolidations] Signed-off-by: Tom Rini <trini@konsulko.com>
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