Age | Commit message (Collapse) | Author | |
---|---|---|---|
2019-07-25 | arm: dts: ls1028a updates for network interfaces | Alex Marginean | |
Defines LS1028A RDB SGMII port, QDS RGMII port. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> | |||
2019-06-19 | arm: ls1028a: define the integrated PCI bus (ECAM) | Alex Marginean | |
LS1028A includes an integrated PCI bus with 11 PCI functions residing on bus 0. ECAM plus the device register space takes up 256MB of address space. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> | |||
2019-06-19 | armv8: ls1028a: Add ecc address node for sata. | Peng Ma | |
Move the ecc addr from driver to dts Signed-off-by: Peng Ma <peng.ma@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> | |||
2019-05-22 | arm: dts: fsl-ls1028a: add sp805 watchdog node | Qiang Zhao | |
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> | |||
2019-05-22 | armv8: ls1028a: Add NXP LS1028A SoC support | Yuantian Tang | |
Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |