Age | Commit message (Collapse) | Author | |
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2018-07-12 | ARM: socfpga: Make DRAM node available in SPL | Marek Vasut | |
The SPL can also parse the DRAM configuration node to figure out the memory layout, make sure it is available. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> | |||
2018-05-18 | ARM: socfpga: Synchronize Arria10 DTs | Marek Vasut | |
Synchronize Altera Arria 10 DT sources with Linux 4.16.3 as of commit ef8216d28a5920022cddcb694d2d75bd1f0035ca Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> |