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2020-04-06arm64: zynqmp: Replace gpio-key,wakeup with wakeup sourceMichal Simek
The same change has been done for Zynq by commit 1241c72b6db1 ("ARM: dts: zynq: replace gpio-key,wakeup with wakeup-source property") in mainline Linux kernel. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-04-06ARM: dts: zynq: replace gpio-key,wakeup with wakeup-source propertySudeep Holla
Most of the legacy "gpio-key,wakeup" boolean property is already replaced with "wakeup-source". However few occurrences of old property has popped up again, probably from the remnants in downstream trees. Replace the legacy properties with the unified "wakeup-source" property introduced in the Linux kernel commit 700a38b27eef ("Input: gpio_keys - switch to using generic device properties") Cc: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-04-06ARM: dts: zc702: Fix I2C bus warningsQuanyang Wang
The dtc has new checks for I2C and SPI buses. Fix the warnings in node names and unit-addresses. Warning from Linux kernel: arch/arm/boot/dts/zynq-zc702.dts:187.13-190.6: Warning (i2c_bus_reg): /amba/i2c@e0004000/i2c-mux@74/i2c@7/hwmon@52: I2C bus unit address format error, expected "34" arch/arm/boot/dts/zynq-zc702.dts:191.13-194.6: Warning (i2c_bus_reg): /amba/i2c@e0004000/i2c-mux@74/i2c@7/hwmon@53: I2C bus unit address format error, expected "35" arch/arm/boot/dts/zynq-zc702.dts:195.13-198.6: Warning (i2c_bus_reg): /amba/i2c@e0004000/i2c-mux@74/i2c@7/hwmon@54: I2C bus unit address format error, expected "36" Signed-off-by: Quanyang Wang <quanyang.wang@windriver.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-04-06arm64: dts: meson: add libretech-pc supportJerome Brunet
Add support for the Amlogic based libretech-pc platform. This platform comes with 2 variant, based on the s905d or s912 SoC. Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> [narmstrong: update board/amlogic/q200/MAINTAINERS] Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-04-06arm64: dts: meson: import libretech-pc from linux v5.6-rc2Jerome Brunet
Sync the libretech-pc device tree from Linux v5.6-rc2 11a48a5a18c6 ("Linux 5.6-rc2") Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-04-06arm64: dts: meson: sync dt and bindings from v5.6-rc2Jerome Brunet
Sync the device tree and dt-bindings from Linux v5.6-rc2 11a48a5a18c6 ("Linux 5.6-rc2") The only exception to this is the mmc pinctrl pin bias of gxl SoC family. This is a fix which found its way to u-boot but not Linux yet. Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-04-05ARM: dts: stm32: Temporarily drop cd-gpios from AV96 DTMarek Vasut
The card-detect GPIO and any other GPIO access currently doesn't work in U-Boot SPL on any STM32 platform and crashes the SPL. To work around this problem on AV96 right before release, remove the cd-gpios from DT. This patch must be reverted right after release, once the proper fix for the GPIO driver, "gpio: stm32: support gpio ops in SPL", is applied. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Tom Rini <trini@konsulko.com> Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2020-04-02ARM: tegra: Add NVIDIA Jetson Nano Developer Kit supportTom Warren
The Jetson Nano Developer Kit is a Tegra X1-based development board. It is similar to Jetson TX1 but it is not pin compatible. It features 4GB of LPDDR4, a SPI NOR flash for early boot firmware and an SD card slot used for storage. HDMI 2.0 or DP 1.2 are available for display, four USB ports (3 USB 2.0 and 1 USB 3.0) can be used to attach a variety of peripherals and a PCI Ethernet controller provides onboard network connectivity. NVMe support has also been added. Env save is at the end of QSPI (4MB-8K). A 40-pin header on the board can be used to extend the capabilities and exposed interfaces of the Jetson Nano. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Tested-by: Peter Robinson <pbrobinson@gmail.com>
2020-04-02ARM: tegra: p2371-2180: add I2C nodes to DTStephen Warren
This adds to the DT the I2C controllers that connect to the board ID EEPROM, etc. With this change, you can now probe all I2C devices on a TX1 board. Signed-off-by: Tom Warren <twarren@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com>
2020-04-01Merge tag 'u-boot-stm32-20200401' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-stm - Fix device tree of Avenger96 board from Arrow Electronics and add compatibility with stm32mp15_dhcom_basic_defconfig
2020-04-01ARM: dts: stm32: Repair PMIC configuration on AV96Marek Vasut
The core and vdd PMIC buck regulators were misconfigured, which caused instability of the board and malfunction of high-speed interfaces, like the RGMII. Configure the PMIC correctly to repair these problems. Also, model the missing Enpirion EP53A8LQI on the DHCOR SoM as a fixed regulator. Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com>
2020-04-01ARM: dts: stm32: Add missing ethernet PHY reset on AV96Marek Vasut
Add PHY reset GPIO on AV96 ethernet PHY. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com>
2020-04-01ARM: dts: stm32: Repair ethernet operation on AV96Marek Vasut
The AV96 RGMII uses different pinmux for ETH_RGMII_TXD0, ETH_RGMII_RXD2 and ETH_RGMII_TX_CTL. Use the correct pinmux to make ethernet operational. Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com>
2020-04-01ARM: dts: stm32: Add alternate pinmux for ethernet RGMIIMarek Vasut
Add another mux option for DWMAC RGMII, this is used on AV96 board. Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com>
2020-04-01ARM: dts: stm32: Add configuration EEPROM on AV96Marek Vasut
The board has an EEPROM on the same I2C bus as PMIC, at address 0x53. The EEPROM contains the board MAC address. Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com> Change-Id: I340a0675c11e4599968b2e3ef0515fb8da8d7b42
2020-04-01ARM: dts: stm32: Use DT alias for the configuration EEPROMMarek Vasut
Use DT /aliases node to establish a stable phandle to the configuration EEPROM. This permits the configuration EEPROM to be moved e.g. to a different address or a different bus. Adjust the board code to handle new phandle lookup. Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com>
2020-04-01ARM: dts: stm32: Add QSPI NOR on AV96Marek Vasut
The DH Electronics DHCOR SOM has QSPI NOR on the SoM itself, add it into the DT. Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com> Change-Id: Ia7c454c496f50e3fc4851ec1154f3641c416e98e
2020-04-01ARM: dts: stm32: Repair SDMMC2 operationMarek Vasut
The eMMC uses different pinmux for the top four data lines, use such a pinmux, otherwise it takes a very long time until the test for 8bit operation times out. And this is the correct pinmux per schematic too. Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com>
2020-04-01ARM: dts: stm32: Add alternate pinmux for SDMMC2 pins 4-7Marek Vasut
Add another mux option for SDMMC2 pins 4..7, this is used on AV96 board. Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com>
2020-04-01ARM: dts: stm32: Repair SDMMC1 operation on AV96Marek Vasut
The SD uses different pinmux for the D123DIRline, use such a pinmux, otherwise there is a pinmux collision on the AV96. Add missing SD voltage regulator switch and enable SDR104 operation. Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com>
2020-04-01ARM: dts: stm32: Add alternate pinmux for SDMMC1 direction pinsMarek Vasut
Add another mux option for SDMMC1 direction pins, in particular SDMMC1_D123DIR, this is used on AV96 board. Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com>
2020-04-01ARM: dts: stm32: Repair SD1 pre-reloc pinmux DT node on AV96Marek Vasut
The sdmmc1_dir_pins_a: sdmmc1-dir-0 layout changed in commit 35a54d41d9d4 ("ARM: dts: stm32mp1: sync device tree with v5.2-rc4") such that pins{}; became pins1{};pins2{};, however the SPL extras were not updated to reflect that change. Fix this. This fixes booting from SD1 X9 slot on the AV96 board. Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> Fixes: 35a54d41d9d4 ("ARM: dts: stm32mp1: sync device tree with v5.2-rc4") Signed-off-by: Marek Vasut <marex@denx.de> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com>
2020-03-31Merge branch 'next' of git://git.denx.de/u-boot-usb into nextTom Rini
2020-03-31Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini
2020-03-31Merge branch 'master' of git://git.denx.de/u-boot-shTom Rini
- Fixes for Gen 2 V2H Blanche
2020-03-31arm: dts: agilex: Enable QSPILey Foon Tan
Enable QSPI for Agilex SoC devkit. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-03-30arm: dts: ls1028a: Use flexspi in octal I/O modeKuldeep Singh
Configure RX and TX bus-width values to use flexspi in octal I/O mode. If bus-widths are not specified, then single I/O mode is set by default. Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-03-30arm: dts: lx2160a: Use flexspi in octal I/O modeKuldeep Singh
Configure RX and TX bus-width values to use flexspi in octal I/O mode. If bus-widths are not specified, then single I/O mode is set by default. Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-03-30arm: dts: lx2160aqds: Add FSPI node propertiesKuldeep Singh
lx2160a-qds has 2 micron "mt35xu512aba" flashes of size 64M each connected on A0 and B1 i.e on CS0 and CS3. Since flashes are connected on different buses, only one flash can be probed at a time. Add fspi node properties aligned with LX2160A-RDB fspi properties. Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-03-30dm: arm64: ls1046a: add i2c DM supportBiwen Li
This supports i2c DM and enables CONFIG_DM_I2C for SoC LS1046A Signed-off-by: Biwen Li <biwen.li@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-03-30ARM: dts: rmobile: Enable IIC3 on V2H BlancheMarek Vasut
Enable IIC3 to permit access to the PMIC. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2020-03-30ARM: dts: rmobile: Add IIC3 node on Gen2 R8A7792 V2HMarek Vasut
Add IIC3 node from mainline Linux DT. This will be further updated in subsequent DT sync, however adding this node for now is sufficient and minimal change. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2020-03-26rv1108: Fix boot regressionOtavio Salvador
Since commit 79030a486128 ("rockchip: Add Single boot image (with binman, pad_cat)") the following boot regression is seen: U-Boot 2020.04-rc3-00050-gd16e18ca6c-dirty (Mar 09 2020 - 11:40:07 -0300) Model: Elgin RV1108 R1 board DRAM: 128 MiB initcall sequence 67fd12a0 failed at call 6000b927 (err=-22) This happens because the above commit missed to include the "rockchip-u-boot.dtsi" for rv1108, so include this file like it done for other Rockchip SoC dtsi's. Fixes: 79030a486128 ("rockchip: Add Single boot image (with binman, pad_cat)") Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-03-26ARM: dts: Activate pullups in the console pins on rv1108-elgin-r1Otavio Salvador
In order to make the console pins more robust to noise, activate the pullups and increase its drive strength. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-03-24ram: stm32mp1: the property st, phy-cal becomes optionalPatrick Delaunay
This parameter "st,phy-cal" becomes optional and when it is absent the built-in PHY calibration is done. It is the case in the helper dtsi file "stm32mp15-ddr.dtsi" except if DDR_PHY_CAL_SKIP is defined. This patch also impact the ddr interactive mode - the registers of the param 'phy.cal' are initialized to 0 when "st,phy-cal" is not present in device tree (default behavior when DDR_PHY_CAL_SKIP is not activated) - the info 'cal' field can be use to change the calibration behavior - cal=1 => use param phy.cal to initialize the PHY, built-in training is skipped - cal=0 => param phy.cal is absent, built-in training is used (default) Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Acked-by: Patrice Chotard <patrice.chotard@st.com>
2020-03-24ARM: dts: stm32mp1: DT alignment with Linux 5.6-rc1Patrick Delaunay
This commit manages diversity for STM32M15x SOCs with: - dedicated files to support all STM32MP15 SOCs family. The differences between those SOCs are: -STM32MP151 [1]: common file. -STM32MP153 [2]: STM32MP151 + CANs + a second CortexA7-CPU. -STM32MP157 [3]: STM32MP153 + DSI + GPU. - new files to manage security diversity on STM32MP15x SOCs. On STM32MP15xY, "Y" gives information: -Y = A means no cryp IP and no secure boot. -Y = C means cryp IP + secure boot. - stm32mp157 pinctrl files to better manage package diversity. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Acked-by: Patrice Chotard <patrice.chotard@st.com>
2020-03-17Merge tag 'ti-v2020.07-next' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-ti into next K3 J721E: * OSPI boot support * Support for loading remote cores in R5 SPL * PMIC ESM Support * Minor fixes for R5F and C7x remoteproc drivers K3 AM654: * Update AVS class 0 voltages. * Add I2C nodes DRA7xx/AM57xx: * Fixed Android boot on AM57xx AM33/AM43/Davinci: * switch to driver model for the net and mdio driver for baltos * Add DM/DTS support for omap video driver * Enable fastboot on am335x-evm
2020-03-10Merge tag 'mmc-2020-3-9' of https://gitlab.denx.de/u-boot/custodians/u-boot-mmcTom Rini
- DM support for CAxxxx SoCs - eMMC board for presidio-asic - Add defer probe for mmc sdhci - TI SoCs mmc misc update
2020-03-10arm: dts: imx8mq-evk: add phy-reset-gpios for fec1Alifer Moraes
Instead of resetting the ethernet phy through functions in imx8mq_evk.c, let the driver reset the phy via dts description adding a reset duration of 10 ms following atheros 8031's datasheet recommendation. Signed-off-by: Alifer Moraes <alifer.wsdm@gmail.com>
2020-03-09ARM: dts: imx8mm-verdin: drop rgmii_rxc_dly/txc_dlyMax Krummenacher
The FEC in the i.MX8MM doesn't support this feature. So don't pretend one can use it. Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com> Acked-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
2020-03-09ARM: dts: imx8mm-verdin: dm-spl for pinctrl_usdhc1 nodeIgor Opaniuk
Let pinctrl configuration for eMMC node (usdhc1) also be accessible in SPL. Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
2020-03-09imx: mx6ul_14x14_evk: configure for 24bpp displayAnatolij Gustschin
Before DM_VIDEO conversion this board used 24bpp display configuration, so use it again. Signed-off-by: Anatolij Gustschin <agust@denx.de> Reviewed-by: Fabio Estevam <festevam@gmail.com>
2020-03-09ARM: dts: imx6sx-sdb: Sync with kernel 5.4.16Fabio Estevam
Sync the imx6sx-sdb dts files with kernel 5.4.16. Signed-off-by: Fabio Estevam <festevam@gmail.com>
2020-03-09ARM: dts: imx6sx: Sync with kernel 5.4.16Fabio Estevam
Sync the imx6sx dts files with kernel 5.4.16. Signed-off-by: Fabio Estevam <festevam@gmail.com>
2020-03-09arm: dts: k3-j721e-r5-common-proc-board: Use unique names for dummy clocksFaiz Abbas
Update the dummy clock names to use unique identifiers. Otherwise the previous node just gets overwitten by the next one with the same name. This fixes eMMC boot not working on J721e-evm. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2020-03-09mmc: am654_sdhci: Update output tap delay writesFaiz Abbas
With the latest RIOT, there is a different otap delay value for each speed mode. Add a new binding with every supported speed mode. Also disable a given speed mode in the host caps if its corresponding otap-del-sel is not present. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-03-06arm: dts: k3-j721e-r5-common-proc-board: Add ospi1 flash nodeKeerthy
Add ospi1 flash node required for QSPI boot. Signed-off-by: Keerthy <j-keerthy@ti.com>
2020-03-06arm: dts: k3-j721e-mcu-wakeup: Add assigned-clocks/rates properties for ↵Keerthy
ospi1/qspi Add assigned-clocks/rates properties for ospi1/qspi. This is the expected rate as per ROM configuration. Signed-off-by: Keerthy <j-keerthy@ti.com>
2020-03-06arm: dts: k3-j721e: Enable ospi1/qspiKeerthy
Enable the ospi1/qspi for both r5 and a72 configurations. Signed-off-by: Keerthy <j-keerthy@ti.com>
2020-03-04Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini
- ABB SECU board - Assorted minor fixes
generated by cgit (git 2.34.1) at 2025-02-22 12:59:35 +0000