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2020-06-04Merge tag 'u-boot-atmel-fixes-2020.07-a' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-atmel First set of u-boot-atmel fixes for 2020.07 cycle This set includes just two small commits that fix a build warning and add a missing serial node.
2020-06-01Merge tag 'u-boot-stm32-20200528' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-stm - stm32mp15: fix DT on DHCOR SOM and avenger96 board - stm32mp15: re-enable KS8851 on DHCOM
2020-05-31Merge tag 'u-boot-rockchip-20200531' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip - Fix mmc of path after syncfrom kernel dts; - Add dwc3 host support with DM for rk3399; - Add usb2phy and typec phy for rockchip platform; - Migrate board list doc to rockchip.rst; - Add rk3399 Pinebook Pro board support; - Update dram_init in board_init and add memory node in SPL;
2020-05-31rockchip: Add initial support for the Pinebook Pro laptop from Pine64.Peter Robinson
Specification: - Rockchip RK3399 - 4GB Dual-Channel LPDDR4 - eMMC socket - mSD card slot - 128Mbit (16Mb) SPI Flash - AP6256 for 11AC WiFi + BT5 - 14 inch 1920*1080 eDP MiPi display - Camera - USB 3.0, 2.0 ports - Type-C port with alt-mode display (DP 1.2) and 15W charge - DC 5V/3A - optional PCIe slot for NVMe SSD drive Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Tested-by: Vagrant Cascadian <vagrant@debian.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-31arm: dts: rockchip: Add initial DT for Pinebook ProPeter Robinson
Sync initial support for Pinebook Pro device tree from Linux 5.7-rc1. Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-30ARM: dts: rk3399-evb: usb3.0 host supportFrank Wang
Configure 'tcphy1' and 'usbdrd_dwc3_1' nodes to support USB3.0 host for Rockchip RK3399 Evaluation Board. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-29arm64: dts: rk3399-nanopi4: Add u-boot,spl-boot-orderJagan Teki
Add u-boot,spl-boot-order as sdhci and sdmmc for booting from eMMC and SD card. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-29rockchip: Fix spl mmc boot device ofpathJagan Teki
Linux v5.7-rc1 dts(i) sync has changed the sdmmc node from dwmmc@fe320000 to mmc@fe320000 and this ofpath is being used in rockchip spl bootdevice code. So, update the ofpath with a new node name and prefix "same-as-spl" to missing u-boot,spl-boot-order. Bug log: U-Boot SPL 2020.07-rc2-00256-g9c5fef5774 (May 24 2020 - 20:20:43 +0530) Trying to boot from MMC2 mmc_load_image_raw_sector: mmc block read error Trying to boot from MMC1 mmc_load_image_raw_sector: mmc block read error SPL: failed to boot from all boot devices Fixes: 167efc2c7a46 ("arm64: dts: rk3399: Sync v5.7-rc1 from Linux" Signed-off-by: Suniel Mahesh <sunil@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-29arm: dts: meson-gxl: fix USB gadget by adding missing nodes for U-BootNeil Armstrong
The khadas-vim, khadas-vim2, libretech-ac & libretech-*-pc boards were missing DT tweak to enable USB gadget. Add them to their -u-boot.dtsi files and include the right gxl-u-boot.dtsi. Fixes: a19e8a0f03 ("arm: dts: meson-gxl: Add USB Gadget nodes for U-Boot") Reported-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-05-29arm: dts: khadas-vim3: include meson-g12-common-u-boot.dtsi to enable HDMI ↵Neil Armstrong
output Include the common g12 u-boot tweaks to permit enabling video output tweaks on Khadas VIM3 boards. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-05-28ARM: dts: stm32: Disable SDR104 mode on AV96Marek Vasut
Disable SDR104 mode until we know it is really stable. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-05-28ARM: dts: stm32: Repair I2C2 operation on AV96Marek Vasut
The I2C2 uses different pinmux on AV96, use correct pinmux and also add comments about the I2C being present on the "low-speed" expansion connector X6. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-05-28ARM: dts: stm32: Add alternate pinmux for I2C2 pinsMarek Vasut
Add another mux option for I2C2 pins, this is used on AV96 board. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-05-28ARM: stm32: Hog GPIO PF7 high on DHCOR to unlock SPI NOR nWPMarek Vasut
The SPI NOR nWP line is connected to GPIO PF7 on the SoM, pull the GPIO line high by default to clear SPI NOR WP. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-05-27arm: mvebu: Convert CRS305-1G-4S board to CRS3xx-98DX3236Luka Kovacic
Convert the CRS305-1G-4S board to CRS3xx-98DX3236 to enable easier implementation of new CRS3xx series boards, based on Marvell Prestera 98DX3236. Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr> Reviewed-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Jakov Petrina <jakov.petrina@sartura.hr>
2020-05-27arm: mvebu: armada-3720-uDPU: fix PHY mode definition to sgmii-2500Jakov Petrina
Commit f49ac7e1c4 switched the default PHY speed to 3.125Gbit to resolve issues with SFP modules. However, U-Boot does not have a "2500base-x" phy-mode. Resolve this by using "sgmii-2500" instead. Signed-off-by: Jakov Petrina <jakov.petrina@sartura.hr> Signed-off-by: Vladimir Vid <vladimir.vid@sartura.hr> Reviewed-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Stefan Roese <sr@denx.de>
2020-05-27arm: mvebu: ds414: add u-boot,dm-pre-reloc to spi0Ezra Buehler
Without this U-Boot-specific property, booting on the Synology DS414 (or DS214+) fails in SPL. The spi0 DT node is not scanned, as a result the SPI flash cannot be found. Signed-off-by: Ezra Buehler <ezra@easyb.ch> Reviewed-by: Stefan Roese <sr@denx.de>
2020-05-25Merge tag 'ti-v2020.07-rc3' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-ti - Enable DM_ETH on omap3_logic board - Enable Caches in SPL for K3 platforms - Enable backup boot mode support for J721E - Update the DDR timings for AM654 EVM - Add automated tests for RX-51
2020-05-22rockchip: rk3328: rock64 - fix gen3 SPL hangKurt Miller
Use the same approach as ROC-RK3328-CC which enables SPL GPIO, pinctl and regulator support. This allows the gen3 board to boot through SPL and does not break gen2 in the process. Signed-off-by: Kurt Miller <kurt@intricatesoftware.com> Acked-by: Matwey V. Kornilov <matwey.kornilov@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-22rockchip: Enable PCIe/M.2 on rk3399 board w/ M.2Jagan Teki
Enable PCIe/M.2 support on - NanoPC-T4 - ROC-RK3399-PC Mezzanine boards. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Suniel Mahesh <sunil@amarulasolutions.com> #roc-rk3399-pc Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-22rockchip: rk3399: enable spl-fifo-mode for sdmmcDeepak Das
adapting commit fa2047c47310 ("rockchip: rk3328: enable spl-fifo-mode for emmc and sdmmc") for rk3399. Since mmc to sram can't do dma, add patch to prevent aborts transferring TF-A parts. Signed-off-by: Deepak Das <deepakdas.linux@gmail.com>
2020-05-21Merge git://git.denx.de/u-boot-shTom Rini
- Enable -ffunction-sections / -fdata-sections --gc-sections to SH - RCar Gen3 updates
2020-05-20ARM: dts: rmobile: Enable eMMC DDR52 modes on Gen3 Salvator-X(S),ULCB,EbisuMarek Vasut
Enable DDR52 modes, since the SD core supports correct switching now. For completeness, list HS200 modes, however those were already enabled. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2020-05-20ARM: dts: rmobile: Reserve space in R-Car Gen3 DTsMarek Vasut
Reserve 4 kiB of space in R-Car Gen3 DTs when those DTs are compiled to permit patching in OpTee-OS /firmware node, /reserved-memory node and possibly also additional /memory@ nodes. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com>
2020-05-19ARM: omap3_logic boards: Convert to DM_ETHAdam Ford
With the converstion of SMC911x to DM, this can facilitate the omap3 boards from LogicPD (now called Beacon EmbeddedWorks) to be converted. There isn't a clean solution to doing this in phases, so the boards are all being done together to avoid breaking functionality. Because the GPMC bus hasn't been converted, the -u-boot.dtsi node needs to show the address of the ethernet controller for each board. The board file, which is common betwen the OMAP35 and DM37 SOM LV and Torpedo boards, can remove the manual ethernet initialization, but it still needs to register the address and GPMC configuration for the Ethernet controller which is now being moved around to board_late_init(). Lastly, this patch updates the various config files to add the reference for DM_ETH and remove the SMC address, which is now fetched from the newly created device tree nodes. Signed-off-by: Adam Ford <aford173@gmail.com>
2020-05-19ddr: k3-am654: EMIF Tool update to 2.02 for IO optimizations and fixesPraneeth Bajjuri
EMIF tool for AM65x [1] is now updated from rev 1.98 to 2.02 This update includes * Optimizations in IO configuration. * Fix for byte enablement in GCR registers. * Fixes for PG2.0 including ZQ control. [1]: http://www.ti.com/lit/zip/sprcah7 Acked-by: James Doublesin <doublesin@ti.com> Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>
2020-05-19arm: dts: ls2080aqds: add CONFIG_MULTI_DTB_FIT supportIoana Ciornei
Add support for selecting the appropriate DTS file depending on the SERDES protocol used. The fsl-ls2080a-qds DTS will be used by default if there isn't a DTS file specifically made for the current SERDES protocol. This patch adds the necessary DPMAC nodes (DPMAC 1-8) for protocol 42 (0x2A) on SD#1. Also, in case CONFIG_DM_ETH and CONFIG_MULTI_DTB_FIT are enabled implement the board_fit_config_name_match() function in order to choose the appropriate DTS. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-05-19arm: dts: ls1088aqds: add CONFIG_MULTI_DTB_FIT supportIoana Ciornei
Add support for selecting the appropriate DTS file depending on the SERDES protocol used. The fsl-ls2088a-qds DTS will be used by default if there isn't a DTS file specifically made for the current SERDES protocol. This patch adds support for the on-board ports (DPMAC 1,2 and 4,5) found on the SERDES protocols 21(0x15) and 29(0x1d) for SD#1. On the LS1088AQDS board EMDIO1 is used with two onboard RGMII PHYs (Realtek RTL8211FD-CG), as well as 2 input/output connectors for mezzanine cards. Configuration signals from the Qixis FPGA control the routing of the external MDIOs. Register 0x54 of the Qixis FPGA controls the routing of the EMDIO1 one of the 2 IO slots. As a consequence, a new node is added to describe register 0x54 as a MDIO mux controlled with child nodes describing all the IO slots as MDIO buses. Also, in case CONFIG_DM_ETH and CONFIG_MULTI_DTB_FIT are enabled implement the board_fit_config_name_match() function in order to choose the appropriate DTS. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-05-19arm: dts: lx2160aqds: add nodes describing possible mezzanine cardsIoana Ciornei
Add device trees describing possible uses of mezzanine cards depending on the SERDES protocol employed. This patch adds DPAA2 networking support for the following protocols on each SERDES block: * SD #1: 3, 7, 19, 20 * SD #2: 11 Each SERDES block has a different device tree file per protocol supported, where the IO SLOTs used are enabled and PHYs located on the mezzanine cards are described. Also, dpmac nodes are edited and their associated phy-connection-type and phy-handle are added. Top DTS files are also added for each combination of protocol on the 3 SERDES blocks. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Reviewed-by: Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-05-19arm: dts: lx2160aqds: add MDIO slotsIoana Ciornei
The LX2160A processor has two external MDIO interfaces, described in the DTS as emdio1 and emdio2. On the LX2160AQDS board EMDIO1 is used with two onboard RGMII PHYs (Realtek RTL8211FD-CG), as well as eight input/output connectors for mezzanine cards. Configuration signals from the Qixis FPGA control the routing of the external MDIOs. Register 0x54 of the Qixis FPGA controls the routing of the EMDIO1 one of the 8 IO slots. As a consequence, a new node is added to describe register 0x54 as a MDIO mux controlled with child nodes describing all the IO slots as MDIO buses. Also, DPMAC 17 and 18 are updated to reference the on-board PHYs. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Reviewed-by: Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-05-19arm: dts: lx2160a: add noted for dpmacs 1, 2, 5-6Ioana Ciornei
Add nodes for DPMACs 1, 2 and 5-6 which were missing from the description. These will be later used on the LX2160AQDS specific DTS. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Reviewed-by: Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-05-19treewide: Update fsl qspi node dt properties as per spi-mem driverKuldeep Singh
According to new qspi driver, some properties like "bus-num, num-cs, big-endian" are no longer used. Device endiannes can be determined from device-type data in driver. Now use board specific compatibles, generic node names and specific labels to align with linux device-tree properties. Also consolidate spi-max-frequency to 50Mhz treewide. Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-05-18ARM: dts: sama5d2: Add uart4 definitionTiaki Rice
This patch adds support for uart4 to the processor level device tree include file. Signed-off-by: Tiaki Rice <tiakirice@hotmail.com> Cc: Eugen Hristev <Eugen.Hristev@microchip.com>
2020-05-17dts: nxp2160ardb: add op-tee nodeIlias Apalodimas
A defconfig is added on lx2160ardb which allows UEFI variable management via OP-TEE. Enable the the node in the relevant DTS file. Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2020-05-15rename symbol: CONFIG_TEGRA -> CONFIG_ARCH_TEGRATrevor Woerner
Have this symbol follow the pattern of all other such symbols. Signed-off-by: Trevor Woerner <twoerner@gmail.com>
2020-05-15rename symbol: CONFIG_KIRKWOOD -> CONFIG_ARCH_KIRKWOODTrevor Woerner
Have this symbol follow the pattern of all other such symbols. This patch also removes a TODO from the code. Reviewed-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Trevor Woerner <twoerner@gmail.com>
2020-05-14Merge tag 'u-boot-stm32-20200514' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-stm - stm32mp1: migrate MTD and DFU configuration in Kconfig - stm32mp1: add command stm32prog - stm32mp1: several board and arch updates - stm32mp1: activate data cache in SPL and before relocation - Many improvment for AV96 board and DHCOR SoM (add new defconfig, DDR3 coding on DHCOR SoM, split between board and SOM Synchronize DDR setttings on DH SoMs, setting for I2C EEPROM) - clk: stm32mp1: fix CK_MPU calculation - DT alignment of stm32mp1 device tree with Linux 5.7-rc2
2020-05-14Merge tag 'rpi-next-2020.07' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-raspberrypi - fix phy configuration for RPi4's bcmgenet - sync RPi4's env size with other RPi configs - add kconfig option to reserver more pages in the EFI mem map - add support for SDMA which is used by RPi4 - fix corner case boot bug for RPi3 32-bit
2020-05-14ARM: dts: stm32mp1: DT alignment with Linux 5.7-rc2Patrick Delaunay
DT alignment with Linux 5.7-rc2, including the kernel commits 431c89e6f323 ARM: dts: stm32: use correct vqmmc regu for eMMC on stm32mp1 ED1/EV1 boards 79e965053872 ARM: dts: stm32: add disable-wp property for SD-card on STM32MP1 boards 877db62ea516 ARM: dts: stm32: add cd-gpios properties for SD-cards on STM32MP1 boards 7519e95ba5f8 ARM: dts: stm32: Do clean up in stmpic nodes on stm32mp15 boards f68e2dbc591a ARM: dts: stm32: Rename stmfx joystick pins on stm32mp157c-ev1 d6210da4f8bf ARM: dts: stm32: add cpu clock-frequency property on stm32mp15x b65b6fc56925 ARM: dts: stm32: add wakeup-source in all I2C nodes of stm32mp157c 1c1cf5996cfb ARM: dts: stm32: add i2c4 sleep pinctrl on stm32mp157c-ed1 bef15fc0fad9 ARM: dts: stm32: add i2c2/i2c5 sleep pinctrl on stm32mp157c-ev1 b7fc0a87b9ac ARM: dts: stm32: add i2c4 sleep pinctrl on stm32mp15xx-dkx a5e557655285 ARM: dts: stm32: set i2c4 bus freq to 400KHz on stm32mp15 DK boards 8bc631b650a6 ARM: dts: stm32: set i2c4 bus freq to 400KHz on stm32mp157c-ed1 fccd6a577bb3 ARM: dts: stm32: Correct stmfx node name on stm32mp157c-ev1 board cc775a83db65 ARM: dts: stm32: add resets property on all DMA nodes on stm32mp151 c5fae093511b ARM: dts: stm32: enable USB OTG Dual Role on stm32mp157c-ev1 9879e2165758 ARM: dts: stm32: add USB OTG pinctrl to stm32mp15 82ac8a81f985 ARM: dts: stm32: add USB OTG full support on stm32mp151 8714b26e2863 ARM: dts: stm32: remove useless properties in stm32mp157a-avenger96 stmpic node a7959919709e ARM: dts: stm32: Add UART8 pins A pinmux entry on stm32mp1 4d7c53a684da ARM: dts: stm32: Add USART3 pins A pinmux entry on stm32mp1 80ab128332ee ARM: dts: stm32: Add SAI2A pins B pinmux entry on stm32mp1 ab7f98c0c546 ARM: dts: stm32: Add Ethernet0 RMII pins A pinmux entry on stm32mp1 Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-05-14ARM: stm32: Hog GPIO PF7 high on DHCOM to unlock SPI NOR nWPMarek Vasut
The SPI NOR nWP line is connected to GPIO PF7 on the SoM, pull the GPIO line high by default to clear SPI NOR WP. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-05-14ARM: dts: stm32: Synchronize DDR setttings on DH SoMsMarek Vasut
Add custom DDR DRAM settings for the DHCOR and DHCOM SoMs and put them into use by the board file instead of the default ones. These new DRAM settings are a better fit for the SoMs. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-05-14ARM: dts: stm32: Fix AV96 and DHCOR splitMarek Vasut
The commit 132e5b68986d ("ARM: dts: stm32: Split AV96 into DHCOR SoM and AV96 board") was not applied correctly and in full, and omitted an important split of the SoM into 3V3 and 1V8 options. The Avenger96 board is based on the 1V8 IO option of the DHCOR SoM, however this is an optional modification of the 3V3 IO DHCOR SoM with extra on-SoM regulator to cater for the 96boards 1V8 IO requirements. Reinstate the split between the 1V8 and 3V3 IO variants. Fixes: 132e5b68986d ("ARM: dts: stm32: Split AV96 into DHCOR SoM and AV96 board") Signed-off-by: Marek Vasut <marex@denx.de> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-05-14ARM: dts: stm32mp15: use DDR3 files generated by STM32CubeMXPatrick Delaunay
Use the DDR3 dtsi files generated by STM32CubeMX 5.6.0 Speed Bin Grade = using DDR3-1066G / 8-8-8 and all others parameters at default value. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-05-14board: stm32mp1: update management of boot-ledPatrick Delaunay
Force boot-led ON and no more rely on default-state. This patch avoid device-tree modification for U-Boot. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-05-14board: stm32mp1: reserve memory for OP-TEE in device treePatrick Delaunay
Add reserve memory for OP-TEE in U-Boot and in kernel device tree: - no more reduce the DDR size in "memory" node: CONFIG_SYS_MEM_TOP_HIDE is no more used - U-Boot device-tree defines the needed "reserved-memory" for OP-TEE and U-Boot should not use this reserved memory: board_get_usable_ram_top use lmb lib to found the first free region, the not reserved memory, enough to relocate U-Boot: the needed size of U-Boot is estimated with gd->mon_len + CONFIG_SYS_MALLOC_LEN. - the optee node ("optee@...": firmware with compatible "linaro,optee-tz") and the associated "reserved-memory" are deactivated in kernel device tree when OP-TEE is not detected by U-Boot to prevent kernel issue (memory is reserved but not used, optee driver probe failed). Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-05-14ARM: stm32: Implement DDR3 coding on DHCOR SoMMarek Vasut
The DHCOR board does exist in multiple variants with different DDR3 DRAM sizes. To cater for all of them, implement DDR3 code handling. There are two GPIOs which code the DRAM size populated on the SoM, read them out and use the value to pick the correct DDR3 config. Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com>
2020-05-14ARM: dts: stm32: Rework DDR DT inclusionMarek Vasut
Adjust the DDR configuration dtsi such that they only generate the DRAM configuration node, the DDR controller node is moved into the stm32mp157-u-boot.dtsi itself. This permits including multiple DDR configuration dtsi files in board DT. Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com>
2020-05-14ARM: stm32: Implement board coding on AV96Marek Vasut
The AV96 board does exist in multiple variants. To cater for all of them, implement board code handling. There are two GPIOs which code the type of the board, read them out and use the value to pick the correct device tree from an fitImage. Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Marek Vasut <marex@denx.de> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Patrice Chotard <patrice.chotard@st.com> Change-Id: Iddb330b9a66500495885457cbe17edc0eacaaf43
2020-05-12Merge tag 'u-boot-amlogic-20200511' of ↵Tom Rini
https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic - Enable USB Host for Odroid-C2 board - Add Open-Drain/Open-Source emulation in GPIO uclass
2020-05-12arm: dts: bcm283x: Allow UARTs to work before relocationSimon Glass
At present the pinctrl nodes are not enabled in pre-relocation U-Boot so the UARTs do not correctly select the pinconfig to enable the UART pins. Fix this so that the U-Boot banner is printed. This fixes serial output on rpi_3b_32b with the following config.txt options: enable_uart=1 gpu_freq=250 Signed-off-by: Simon Glass <sjg@chromium.org> Fixes: 9821636b64 (bcm2835_pinctrl: Probe pre-reloc) Signed-off-by: Matthias Brugger <mbrugger@suse.com>
generated by cgit (git 2.34.1) at 2024-12-28 03:28:28 +0000