| Age | Commit message (Collapse) | Author |
|---|
|
Add Firefly ROC-RK3399-PC Mezzanine board which is an
extension board on top of roc-rk3399-pc.
Will drop the separate defconfig file, once we support
the board detection at runtime.
Signed-off-by: Suniel Mahesh <sunil@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
|
Sync Firefly ROC-RK3399-PC Mezzanine Board dts file
from Linux v5.7-rc1.
Signed-off-by: Suniel Mahesh <sunil@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
|
Sync rk3399 dts(i) files from v5.7-rc1 linux-next.
Reason:
To get updated PCIe nodes and properties on respective
dts(i) files.
Summary:
- sync won't include new board dts(i)
- sync will add required files used on respective dts(i)
- rk3399-puma-u-boot.dtsi spiflash label changed to norflash
- move puma.dtsi bios_enable into rk3399-puma-u-boot.dtsi
- move legacy max-frequency of sdhci into rk3399-u-boot.dtsi
- update cross-ec-[keyboard|sbs].dtsi path as per U-Boot
- keep roc-rk3399-pc dc_12v changes to -u-boot.dtsi
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
|
Move U-Boot specific properties into rk3399-evb u-boot
specific dtsi file.
This would help to sync the devicetrees from Linux whenever
required instead of adding specific nodes.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
|
Move U-Boot specific properties into rk3399-puma u-boot
specific dtsi file.
This would help to sync the devicetrees from Linux whenever
required instead of adding specific nodes.
Cc: Peter Robinson <pbrobinson@gmail.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
|
If the VBUS regulator is always-on, XHCI will fail to detect USB 3.0
devices; USB 2.0 devices will work however.
Make the VBUS regulator controllable and tie it to only the XHCI. This
makes all three USB ports usable.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
|
The ROC-RK3328-CC from Firefly and Libre Computer Project is a credit
card size development board based on the Rockchip RK3328 SoC, with:
- 1/2/4 GB DDR4 DRAM
- eMMC connector for optional module
- micro SD card slot
- 1 x USB 3.0 host port
- 2 x USB 2.0 host port
- 1 x USB 2.0 OTG port
- HDMI video output
- TRRS connector with audio and composite video output
- gigabit Ethernet
- consumer IR receiver
- debug UART pins
The ROC-RK3328-CC has the enable pin of the SD card power switch tied
to GPIO_0_D6. This pin also has the function SDMMC0_PWREN, which is
muxed by default. SDMMC0_PWREN is an active high signal controlled by
the MMC controller, however the switch enable is active low, and
pulled low (enabled) by default to make things work on boot.
As such, we need to mux away from SDMMC0_PWREN and use GPIO to enable
power to the card. The default GPIO state for the pin is pull-down and
input, which doesn't require extra configuration when paired with the
external pull-down and active low switch.
Deal with this by enabling regulator support in SPL, and setting
"u-boot,dm-spl" for the regulator and other device nodes needed for
muxing the pin.
The device tree file is synced from the Linux kernel next-20200324.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
|
This syncs rk3328 device tree files from the Linux kernel next-20200324.
The last commit to touch these files is:
b2411befed60 ("arm64: dts: add bus to rockchip amba nodenames")
Additional changes not yet in the Linux kernel include:
arm64: dts: rockchip: rk3328: drop #address-cells, #size-cells from grf node
arm64: dts: rockchip: rk3328: drop non-existent gmac2phy pinmux options
arm64: dts: rockchip: rk3328: Replace RK805 PMIC node name with "pmic"
Changes include:
- conversion of raw pin numbers to macros
- removal of deprecated RK_FUNC_* macros
- update of device tree binding headers
- new devices
- device tree cleanups
- gmac2phy disabled in -u-boot.dtsi as it is not supported in U-boot
This includes a re-ordering of the USB device nodes compared to upstream
Linux, moving the dwc2 OTG controller after the EHCI/OHCI nodes. This is
currently required as otherwise the dwc2 controller would not be able to
detect devices in some cases. This may be due to lack of USB PHY support
in U-boot.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
|
|
The "hnp-srp-disable" property for dwc2 is specific to U-boot, not part
of upstream Linux's device tree bindings.
Move it to rk3328-u-boot.dtsi to avoid losing it when syncing device
tree files.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
|
The device tree file for rk3328-evb in the Linux kernel does not have
gmac2io enabled. Instead, gmac2phy is enabled, but that is not supported
in U-boot.
Move the gmac2io related nodes to rk3328-evb-u-boot.dtsi to preserve the
current functionality. When the device tree files are synced, gmac2phy
should be marked as "broken" in -u-boot.dtsi files.
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Loic Devulder <ldevulder@suse.com>
Tested-by: Peter Geis <pgwipeout@gmail.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
|
|
USB 3.0 is only supported in U-boot, not in the Linux kernel where the
device tree files are ultimately synced from. While the xhci node was
moved, the external vbus regulator was not.
Move it as well.
Fixes: 2e91e2025c1b ("rockchip: rk3328: migrate u-boot node to -u-boot.dtsi")
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Loic Devulder <ldevulder@suse.com>
Tested-by: Peter Geis <pgwipeout@gmail.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
|
|
Add enable rng node in px30-evb-u-boot.dtsi.
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
|
Add rng node in rk3399-u-boot.dtsi and enable it in
rk3399-evb-u-boot.dtsi.
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
|
The file <board name>-u-boot.dtsi inculde automatically by the build
system, no need to add this to dts file.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
|
|
Add soc level -u-boot.dtst so that boards can share the common nodes.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
|
|
roc-rk3399-pc has an FE1.1 USB 2.0 HUB which connects two USB ports
(HOST1 and HOST2). For end devices to work we need to enable USB hub
so that HOST detects there presence and enumerates them accordingly.
This requires explicit pinctrl within gpio enablement.
Signed-off-by: Suniel Mahesh <sunil@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
|
|
The Cubieboard is a single board computer containing a
Actions S700 SoC(with 4 ARMv8 Cortex-A53 cores).
This patch adds respective defconfig alongwith .dts(copied
from Linux v5.5-rc6 with hash "b3a987b0264d").
Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
|
|
Devices like uart and clk are needed to be enabled before relocation.
this patch adds u-boot.dtsi file that mark these device as dm-pre-reloc.
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
|
|
This patch adds .dtsi file(sync with Linux 5.5-rc6 with hash "b3a987b0264d")
and required binding for S700 SoC that is a 64-bit Quad-core ARM
Cortex-A53 cores.
It also provisions dts file to be built based on selected
platform(CONFIG_MACH_S900/S700).
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
|
|
Devices like uart and clk are needed to be enabled before relocation.
This patch adds u-boot.dtsi file that mark these device as dm-pre-reloc.
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
|
|
Synchronize device tree bindings with v5.5-rc6 tag with commit id
"b3a987b0264d".
Also, it removes older clock binding defined for S900 along with undocumented
compatible string "actions,s900-serial" from serial driver and adapts clock
driver to cater to new bindings.
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
|
|
The AV96 is in fact an assembly of DH Electronics DHCOR SoM on top
of an AV96 reference board. Split the DTs to reflect that and make
sure to DHCOR SoM can be reused on other boards easily.
It is also highly recommended to configure the board for the DHCOM
make stm32mp15_dhcom_basic_defconfig
make DEVICE_TREE=stm32mp15xx-dhcor-avenger96
as that permits reusing the board code for the DH components, like
accessing and reading out the ethernet MAC from EEPROM.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Change-Id: I7db47280d4eb0d668eb4e006355240271154f97f
|
|
The PLL4 is supplying SDMMC12, SDMMC3 and SPDIF with 120 MHz and
FDCAN with 96 MHz. This isn't good for the SDMMC interfaces, which
can not easily divide the clock down to e.g. 50 MHz for high speed
SD and eMMC devices, so those devices end up running at 30 MHz as
that is 120 MHz / 4. Adjust the PLL4 settings such that both PLL4P
and PLL4R run at 100 MHz instead, which is easy to divide to 50MHz
for optimal operation of both SD and eMMC, SPDIF clock are not that
much slower and FDCAN is also unaffected.
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
|
|
Remove the unnecessary file stm32mp157-pinctrl.dtsi and
solve all issues introduced by the commit 891483186052b2598 ("Merge branch
'next'") after a conflict on the patch applied in the next branch in
commit 1a4f57c895cc ("ARM: dts: stm32mp1: DT alignment with Linux 5.6-rc1")
Need to reapplied on stm32mp15-pinctrl.dtsi the the 3 patches
applied previously on file "stm32mp157-pinctrl.dtsi" in v2020.04
- commit 4fdbe6487daa ("ARM: dts: stm32: Add alternate pinmux for SDMMC1
direction pins")'
- commit 5fdcba64027f ("ARM: dts: stm32: Add alternate pinmux for SDMMC2
pins 4-7")'
- commit 955de5111112 ("ARM: dts: stm32: Add alternate pinmux for ethernet
RGMII")'
Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
|
|
- Further cleanups for 'make refcheckdocs'
- Another BTRFS fix.
- Support for automatic decompression of images with booti as well as
unlz4 command for manual decompression.
|
|
https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic
- enable DM_RNG on meson boards
- fix SMBIOS info on Odroid-C2
- Fix video output on GXBB/GXL/GXM boards
- add USB gadget support for GXL/GXM boards
|
|
https://gitlab.denx.de/u-boot/custodians/u-boot-ti
- Fix boot on am335x guardian board
- Increase OPSI speed on AM65x and J721E devices
- Use JTAD register for identifying K3 devices.
- Update TI entry in MAINTAINERS file.
|
|
Add the USB DWC2 node to u-boot specific dtsi files since Gadget
support is not (yet) available in upstream Linux yet.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
|
|
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
|
Add dtsi file for i.MXRT1020.
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
|
|
Those two boards are supposed to be run with a single u-boot binary.
There are notable differences though - HSC uses DSA switch (which
phy_id == 0x0) and DCC (DP83848C).
After the commit 3bf135b6c367
("drivers: net: phy: Ignore PHY ID 0 during PHY probing") the PHY devices
with phy_id == 0 are not created in U-Boot anymore. This caused regression
on HSC.
To fix this problem - the fec's 'fixed-link' node has been introduced and
the phy_id is not assessed anymore. This approach works on both boards.
Signed-off-by: Lukasz Majewski <lukma@denx.de>
|
|
During the conversion of this board to DM_REGULATOR, usb-mass-storage
was broken and started failing with the following error:
=> ums 0 mmc 2
UMS: LUN 0, dev 2, hwpart 0, sector 0x0, count 0xe90000
Error enabling VBUS supply
g_dnl_register: failed!, error: -38
g_dnl_register failed
Fix this by adding the relevant GPIO to the regulator node.
Fixes: 4ca99fe81aea ("ARM: imx: dh-imx6: Enable DM regulator")
Signed-off-by: Harald Seiler <hws@denx.de>
|
|
Use DM_ETH instead of legacy networking. Add VIO as a fixed regulator
to the relevant device-trees and augment the FEC node with properties
for the reset GPIO.
It should be noted that the relevant properties for the reset GPIO
already exist in the PHY node (reset-gpios, reset-delay-us,
reset-post-delay-us) but U-Boot currently ignores those and only
supports the bus-level reset properties in the FEC node
(phy-reset-gpios, phy-reset-duration, phy-reset-post-delay).
Signed-off-by: Harald Seiler <hws@denx.de>
|
|
The detection of the revD1 version is based on the presence of the PMIC.
Currently revb1 device trees are used for mx6q/mx6dl variants, which
do not have the PMIC nodes.
This causes revD1 boards to be incorrectly be detected as revB1.
Fix this issue by using the revd1 device trees, so that the PMIC node can be
found and then the PMIC can be detected by reading its register ID.
Imported the revd1 device trees from mainline kernel version 5.7-rc1.
Reported-by: Heiko Schocher <hs@denx.de>
Reported-by: Derek Atkins <derek@ihtfp.com>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Tested-by: Derek Atkins <derek@ihtfp.com>
Tested-by: Heiko Schocher <hs@denx.de>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
|
|
Add lcdif node and its pinctrl.
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
|
Linux doesn't provide skeleton.dtsi file so let's remove its include and
provide #address-cells/size-cells = <1> that were defined in
skeleton.dtsi before.
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
|
Add lcdif node to SoC.
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
|
|
The device trees for TQMa6x SOM support variations in
- CPU type: imx6dl- or imx6q-
- MBa6 I2C bus access: -mba6a (i2c1) or -mba6b (i2c3)
(plus the respective common/module include trees)
- USBH1 is directly connected to a hub
- USBOTG is connected to a separate connector
and can act as host/device or full OTG port.
Signed-off-by: Michael Krummsdorf <michael.krummsdorf@ew.tq-group.com>
|
|
This patch add pwm support for mt7622, mt7623 and mt7629 SoCs
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
|
|
available
The Linux VPU bindings have changed and dropped the dmc register range.
Add it back in the meson-gx-u-boot.dtsi file until a proper canvas driver
is available.
Fixes: dd5f2351e9 ("arm64: dts: meson: sync dt and bindings from v5.6-rc2")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
|
|
The libretech-ac u-boot.dtsi file is missing to enabled DT nodes changes
to enable Video output on U-Boot.
Fixes: 671b1db8f8 ("arm64: dts: meson-gx: vpu should be probed before relocation")
Reported-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Tested-by: Jerome Brunet <jbrunet@baylibre.com>
|
|
The LED labels do not match the silkscreen on the board, fix it.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
|
|
Add DT entries, Kconfig entries and board-specific entries to configure
FMC2 bus and make KS8851-16MLL on that bus accessible to U-Boot.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
|
|
- Misc enhancements to Clearfog, including board variant detection
(Joel)
- Misc enhancements to Turris Mox, including generalization of the
ARMADA37xx DDR size detection (Marek)
|
|
Commit e8e9715df2d4 requires the USB3 regulator node to have the
enable-active-high property for the regulator to work properly. The
GPIO_ACTIVE_HIGH constant is not enough anymore.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Fixes: e8e9715df2d4 ("regulator: fixed: Modify enable-active-high...")
Reviewed-by: Stefan Roese <sr@denx.de>
|
|
With recent changes to the mmc subsystem (chip detect code etc) update
the sdhci node of the Turris Mox device tree.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
|
|
Using a consistent hardcoded MAC address from the DTS file causes
issues when using multiple devices on the same network segment.
Instead rely on environment configuration or random generation.
Signed-off-by: Joel Johnson <mrjoel@lixil.net>
Reviewed-by: Stefan Roese <sr@denx.de>
|
|
Sort the Armada series dts in the Makefile alphabetically
prior to adding new board support.
Signed-off-by: Josip Kelečić <josip.kelecic@sartura.hr>
Reviewed-by: Luka Kovacic <luka.kovacic@sartura.hr>
Reviewed-by: Stefan Roese <sr@denx.de>
|
|
In 1 bit mode OSPI can work at upto 50MHz, this provides better write
performance. Therefore increase frequency from 40MHz to 50MHz
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
|
In 1 bit mode OSPI can work at upto 50MHz, this provides better write
performance. Therefore increase frequency from 40MHz to 50MHz
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
